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Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
Sergei Shtylyov0ca646d2010-12-28 21:46:40 +03002 * Libata driver for the HighPoint 371N, 372N, and 302N UDMA66 ATA controllers.
Jeff Garzik669a5db2006-08-29 18:12:40 -04003 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
Sergei Shtylyov8e834c22010-12-25 22:44:01 +030011 * Portions Copyright (C) 2005-2010 MontaVista Software, Inc.
Jeff Garzik669a5db2006-08-29 18:12:40 -040012 *
13 *
14 * TODO
Jeff Garzik669a5db2006-08-29 18:12:40 -040015 * Work out best PLL policy
16 */
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <scsi/scsi_host.h>
25#include <linux/libata.h>
26
27#define DRV_NAME "pata_hpt3x2n"
Sergei Shtylyov40d69ba2011-01-10 21:39:34 +030028#define DRV_VERSION "0.3.14"
Jeff Garzik669a5db2006-08-29 18:12:40 -040029
30enum {
31 HPT_PCI_FAST = (1 << 31),
32 PCI66 = (1 << 1),
33 USE_DPLL = (1 << 0)
34};
35
36struct hpt_clock {
37 u8 xfer_speed;
38 u32 timing;
39};
40
41struct hpt_chip {
42 const char *name;
43 struct hpt_clock *clocks[3];
44};
45
46/* key for bus clock timings
47 * bit
Sergei Shtylyovfd5e62e2009-12-07 23:38:11 +040048 * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
49 * cycles = value + 1
50 * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
51 * cycles = value + 1
52 * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
Jeff Garzik669a5db2006-08-29 18:12:40 -040053 * register access.
Sergei Shtylyovfd5e62e2009-12-07 23:38:11 +040054 * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
Jeff Garzik669a5db2006-08-29 18:12:40 -040055 * register access.
Sergei Shtylyovfd5e62e2009-12-07 23:38:11 +040056 * 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
57 * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.
58 * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
59 * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
Jeff Garzik669a5db2006-08-29 18:12:40 -040060 * register access.
Sergei Shtylyovfd5e62e2009-12-07 23:38:11 +040061 * 28 UDMA enable.
62 * 29 DMA enable.
63 * 30 PIO_MST enable. If set, the chip is in bus master mode during
64 * PIO xfer.
65 * 31 FIFO enable. Only for PIO.
Jeff Garzik669a5db2006-08-29 18:12:40 -040066 */
Jeff Garzik85cd7252006-08-31 00:03:49 -040067
Jeff Garzik669a5db2006-08-29 18:12:40 -040068/* 66MHz DPLL clocks */
69
70static struct hpt_clock hpt3x2n_clocks[] = {
71 { XFER_UDMA_7, 0x1c869c62 },
72 { XFER_UDMA_6, 0x1c869c62 },
73 { XFER_UDMA_5, 0x1c8a9c62 },
74 { XFER_UDMA_4, 0x1c8a9c62 },
75 { XFER_UDMA_3, 0x1c8e9c62 },
76 { XFER_UDMA_2, 0x1c929c62 },
77 { XFER_UDMA_1, 0x1c9a9c62 },
78 { XFER_UDMA_0, 0x1c829c62 },
79
80 { XFER_MW_DMA_2, 0x2c829c62 },
81 { XFER_MW_DMA_1, 0x2c829c66 },
Bartlomiej Zolnierkiewiczd413ff32009-12-03 20:32:09 +010082 { XFER_MW_DMA_0, 0x2c829d2e },
Jeff Garzik669a5db2006-08-29 18:12:40 -040083
84 { XFER_PIO_4, 0x0c829c62 },
85 { XFER_PIO_3, 0x0c829c84 },
86 { XFER_PIO_2, 0x0c829ca6 },
87 { XFER_PIO_1, 0x0d029d26 },
88 { XFER_PIO_0, 0x0d029d5e },
Jeff Garzik669a5db2006-08-29 18:12:40 -040089};
90
91/**
92 * hpt3x2n_find_mode - reset the hpt3x2n bus
93 * @ap: ATA port
94 * @speed: transfer mode
95 *
96 * Return the 32bit register programming information for this channel
97 * that matches the speed provided. For the moment the clocks table
98 * is hard coded but easy to change. This will be needed if we use
99 * different DPLLs
100 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400101
Jeff Garzik669a5db2006-08-29 18:12:40 -0400102static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed)
103{
104 struct hpt_clock *clocks = hpt3x2n_clocks;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400105
Sergei Shtylyovb197f132010-12-28 23:11:36 +0300106 while (clocks->xfer_speed) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400107 if (clocks->xfer_speed == speed)
108 return clocks->timing;
109 clocks++;
110 }
111 BUG();
112 return 0xffffffffU; /* silence compiler warning */
113}
114
115/**
Sergei Shtylyov8e834c22010-12-25 22:44:01 +0300116 * hpt372n_filter - mode selection filter
117 * @adev: ATA device
118 * @mask: mode mask
119 *
120 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
121 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
122 */
123static unsigned long hpt372n_filter(struct ata_device *adev, unsigned long mask)
124{
125 if (ata_id_is_sata(adev->id))
126 mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA);
127
128 return mask;
129}
130
131/**
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500132 * hpt3x2n_cable_detect - Detect the cable type
133 * @ap: ATA port to detect on
Jeff Garzik669a5db2006-08-29 18:12:40 -0400134 *
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500135 * Return the cable type attached to this port
Jeff Garzik669a5db2006-08-29 18:12:40 -0400136 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400137
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500138static int hpt3x2n_cable_detect(struct ata_port *ap)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400139{
140 u8 scr2, ata66;
141 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400142
Jeff Garzik669a5db2006-08-29 18:12:40 -0400143 pci_read_config_byte(pdev, 0x5B, &scr2);
144 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
Bartlomiej Zolnierkiewicz10a9c962009-11-19 20:31:31 +0100145
146 udelay(10); /* debounce */
147
Jeff Garzik669a5db2006-08-29 18:12:40 -0400148 /* Cable register now active */
149 pci_read_config_byte(pdev, 0x5A, &ata66);
150 /* Restore state */
151 pci_write_config_byte(pdev, 0x5B, scr2);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400152
Bartlomiej Zolnierkiewiczf3b1cf42009-11-19 18:38:11 +0100153 if (ata66 & (2 >> ap->port_no))
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500154 return ATA_CBL_PATA40;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400155 else
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500156 return ATA_CBL_PATA80;
157}
Jeff Garzik669a5db2006-08-29 18:12:40 -0400158
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500159/**
160 * hpt3x2n_pre_reset - reset the hpt3x2n bus
Tejun Heocc0680a2007-08-06 18:36:23 +0900161 * @link: ATA link to reset
Alan Cox28e21c82007-04-26 00:19:25 -0700162 * @deadline: deadline jiffies for the operation
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500163 *
164 * Perform the initial reset handling for the 3x2n series controllers.
165 * Reset the hardware and state machine,
166 */
167
Tejun Heoa1efdab2008-03-25 12:22:50 +0900168static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline)
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500169{
Tejun Heocc0680a2007-08-06 18:36:23 +0900170 struct ata_port *ap = link->ap;
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500171 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Sergei Shtylyovb197f132010-12-28 23:11:36 +0300172
Jeff Garzik669a5db2006-08-29 18:12:40 -0400173 /* Reset the state machine */
Alan Cox28e21c82007-04-26 00:19:25 -0700174 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400175 udelay(100);
Tejun Heod4b2bab2007-02-02 16:50:52 +0900176
Tejun Heo9363c382008-04-07 22:47:16 +0900177 return ata_sff_prereset(link, deadline);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400178}
Jeff Garzik85cd7252006-08-31 00:03:49 -0400179
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400180static void hpt3x2n_set_mode(struct ata_port *ap, struct ata_device *adev,
181 u8 mode)
182{
183 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
184 u32 addr1, addr2;
185 u32 reg, timing, mask;
186 u8 fast;
187
188 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
189 addr2 = 0x51 + 4 * ap->port_no;
190
191 /* Fast interrupt prediction disable, hold off interrupt disable */
192 pci_read_config_byte(pdev, addr2, &fast);
193 fast &= ~0x07;
194 pci_write_config_byte(pdev, addr2, fast);
195
196 /* Determine timing mask and find matching mode entry */
197 if (mode < XFER_MW_DMA_0)
198 mask = 0xcfc3ffff;
199 else if (mode < XFER_UDMA_0)
200 mask = 0x31c001ff;
201 else
202 mask = 0x303c0000;
203
204 timing = hpt3x2n_find_mode(ap, mode);
205
206 pci_read_config_dword(pdev, addr1, &reg);
207 reg = (reg & ~mask) | (timing & mask);
208 pci_write_config_dword(pdev, addr1, reg);
209}
210
Jeff Garzik669a5db2006-08-29 18:12:40 -0400211/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400212 * hpt3x2n_set_piomode - PIO setup
213 * @ap: ATA interface
214 * @adev: device on the interface
215 *
Jeff Garzik85cd7252006-08-31 00:03:49 -0400216 * Perform PIO mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400217 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400218
Jeff Garzik669a5db2006-08-29 18:12:40 -0400219static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
220{
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400221 hpt3x2n_set_mode(ap, adev, adev->pio_mode);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400222}
223
224/**
225 * hpt3x2n_set_dmamode - DMA timing setup
226 * @ap: ATA interface
227 * @adev: Device being configured
228 *
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400229 * Set up the channel for MWDMA or UDMA modes.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400230 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400231
Jeff Garzik669a5db2006-08-29 18:12:40 -0400232static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
233{
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400234 hpt3x2n_set_mode(ap, adev, adev->dma_mode);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400235}
236
237/**
238 * hpt3x2n_bmdma_end - DMA engine stop
239 * @qc: ATA command
240 *
241 * Clean up after the HPT3x2n and later DMA engine
242 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400243
Jeff Garzik669a5db2006-08-29 18:12:40 -0400244static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
245{
246 struct ata_port *ap = qc->ap;
247 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
248 int mscreg = 0x50 + 2 * ap->port_no;
249 u8 bwsr_stat, msc_stat;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400250
Jeff Garzik669a5db2006-08-29 18:12:40 -0400251 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
252 pci_read_config_byte(pdev, mscreg, &msc_stat);
253 if (bwsr_stat & (1 << ap->port_no))
254 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
255 ata_bmdma_stop(qc);
256}
257
258/**
259 * hpt3x2n_set_clock - clock control
260 * @ap: ATA port
261 * @source: 0x21 or 0x23 for PLL or PCI sourced clock
262 *
263 * Switch the ATA bus clock between the PLL and PCI clock sources
264 * while correctly isolating the bus and resetting internal logic
265 *
266 * We must use the DPLL for
267 * - writing
268 * - second channel UDMA7 (SATA ports) or higher
269 * - 66MHz PCI
Jeff Garzik85cd7252006-08-31 00:03:49 -0400270 *
Jeff Garzik669a5db2006-08-29 18:12:40 -0400271 * or we will underclock the device and get reduced performance.
272 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400273
Jeff Garzik669a5db2006-08-29 18:12:40 -0400274static void hpt3x2n_set_clock(struct ata_port *ap, int source)
275{
Sergei Shtylyov256ace92009-12-17 01:11:27 -0500276 void __iomem *bmdma = ap->ioaddr.bmdma_addr - ap->port_no * 8;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400277
Jeff Garzik669a5db2006-08-29 18:12:40 -0400278 /* Tristate the bus */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900279 iowrite8(0x80, bmdma+0x73);
280 iowrite8(0x80, bmdma+0x77);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400281
Jeff Garzik669a5db2006-08-29 18:12:40 -0400282 /* Switch clock and reset channels */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900283 iowrite8(source, bmdma+0x7B);
284 iowrite8(0xC0, bmdma+0x79);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400285
Sergei Shtylyov256ace92009-12-17 01:11:27 -0500286 /* Reset state machines, avoid enabling the disabled channels */
287 iowrite8(ioread8(bmdma+0x70) | 0x32, bmdma+0x70);
288 iowrite8(ioread8(bmdma+0x74) | 0x32, bmdma+0x74);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400289
Jeff Garzik669a5db2006-08-29 18:12:40 -0400290 /* Complete reset */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900291 iowrite8(0x00, bmdma+0x79);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400292
Jeff Garzik669a5db2006-08-29 18:12:40 -0400293 /* Reconnect channels to bus */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900294 iowrite8(0x00, bmdma+0x73);
295 iowrite8(0x00, bmdma+0x77);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400296}
297
Alana52865c2007-01-24 11:51:38 +0000298static int hpt3x2n_use_dpll(struct ata_port *ap, int writing)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400299{
300 long flags = (long)ap->host->private_data;
Sergei Shtylyov256ace92009-12-17 01:11:27 -0500301
Jeff Garzik669a5db2006-08-29 18:12:40 -0400302 /* See if we should use the DPLL */
Alana52865c2007-01-24 11:51:38 +0000303 if (writing)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400304 return USE_DPLL; /* Needed for write */
305 if (flags & PCI66)
306 return USE_DPLL; /* Needed at 66Mhz */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400307 return 0;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400308}
309
Sergei Shtylyov256ace92009-12-17 01:11:27 -0500310static int hpt3x2n_qc_defer(struct ata_queued_cmd *qc)
311{
312 struct ata_port *ap = qc->ap;
313 struct ata_port *alt = ap->host->ports[ap->port_no ^ 1];
314 int rc, flags = (long)ap->host->private_data;
315 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);
316
317 /* First apply the usual rules */
318 rc = ata_std_qc_defer(qc);
319 if (rc != 0)
320 return rc;
321
322 if ((flags & USE_DPLL) != dpll && alt->qc_active)
323 return ATA_DEFER_PORT;
324 return 0;
325}
326
Tejun Heo9363c382008-04-07 22:47:16 +0900327static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400328{
Jeff Garzik669a5db2006-08-29 18:12:40 -0400329 struct ata_port *ap = qc->ap;
330 int flags = (long)ap->host->private_data;
Sergei Shtylyov256ace92009-12-17 01:11:27 -0500331 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400332
Sergei Shtylyov256ace92009-12-17 01:11:27 -0500333 if ((flags & USE_DPLL) != dpll) {
334 flags &= ~USE_DPLL;
335 flags |= dpll;
336 ap->host->private_data = (void *)(long)flags;
337
338 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400339 }
Tejun Heo360ff782010-05-10 21:41:42 +0200340 return ata_bmdma_qc_issue(qc);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400341}
342
343static struct scsi_host_template hpt3x2n_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900344 ATA_BMDMA_SHT(DRV_NAME),
Jeff Garzik669a5db2006-08-29 18:12:40 -0400345};
346
347/*
Sergei Shtylyov8e834c22010-12-25 22:44:01 +0300348 * Configuration for HPT302N/371N.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400349 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400350
Sergei Shtylyov8e834c22010-12-25 22:44:01 +0300351static struct ata_port_operations hpt3xxn_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900352 .inherits = &ata_bmdma_port_ops,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400353
Jeff Garzik669a5db2006-08-29 18:12:40 -0400354 .bmdma_stop = hpt3x2n_bmdma_stop,
Sergei Shtylyov256ace92009-12-17 01:11:27 -0500355
356 .qc_defer = hpt3x2n_qc_defer,
Tejun Heo9363c382008-04-07 22:47:16 +0900357 .qc_issue = hpt3x2n_qc_issue,
Jeff Garzikbda30282006-09-27 05:41:13 -0400358
Tejun Heo029cfd62008-03-25 12:22:49 +0900359 .cable_detect = hpt3x2n_cable_detect,
360 .set_piomode = hpt3x2n_set_piomode,
361 .set_dmamode = hpt3x2n_set_dmamode,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900362 .prereset = hpt3x2n_pre_reset,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400363};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400364
Sergei Shtylyov8e834c22010-12-25 22:44:01 +0300365/*
366 * Configuration for HPT372N. Same as 302N/371N but we have a mode filter.
367 */
368
369static struct ata_port_operations hpt372n_port_ops = {
370 .inherits = &hpt3xxn_port_ops,
371 .mode_filter = &hpt372n_filter,
372};
373
Jeff Garzik669a5db2006-08-29 18:12:40 -0400374/**
375 * hpt3xn_calibrate_dpll - Calibrate the DPLL loop
Jeff Garzik85cd7252006-08-31 00:03:49 -0400376 * @dev: PCI device
Jeff Garzik669a5db2006-08-29 18:12:40 -0400377 *
378 * Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this
379 * succeeds
380 */
381
382static int hpt3xn_calibrate_dpll(struct pci_dev *dev)
383{
384 u8 reg5b;
385 u32 reg5c;
386 int tries;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400387
Sergei Shtylyovb197f132010-12-28 23:11:36 +0300388 for (tries = 0; tries < 0x5000; tries++) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400389 udelay(50);
390 pci_read_config_byte(dev, 0x5b, &reg5b);
391 if (reg5b & 0x80) {
392 /* See if it stays set */
Sergei Shtylyovb197f132010-12-28 23:11:36 +0300393 for (tries = 0; tries < 0x1000; tries++) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400394 pci_read_config_byte(dev, 0x5b, &reg5b);
395 /* Failed ? */
396 if ((reg5b & 0x80) == 0)
397 return 0;
398 }
399 /* Turn off tuning, we have the DPLL set */
400 pci_read_config_dword(dev, 0x5c, &reg5c);
Sergei Shtylyovb197f132010-12-28 23:11:36 +0300401 pci_write_config_dword(dev, 0x5c, reg5c & ~0x100);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400402 return 1;
403 }
404 }
405 /* Never went stable */
406 return 0;
407}
408
409static int hpt3x2n_pci_clock(struct pci_dev *pdev)
410{
411 unsigned long freq;
412 u32 fcnt;
Alan Cox28e21c82007-04-26 00:19:25 -0700413 unsigned long iobase = pci_resource_start(pdev, 4);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400414
Alan Cox28e21c82007-04-26 00:19:25 -0700415 fcnt = inl(iobase + 0x90); /* Not PCI readable for some chips */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400416 if ((fcnt >> 12) != 0xABCDE) {
Sergei Shtylyovdfc7e3e2010-12-28 22:54:54 +0300417 int i;
418 u16 sr;
419 u32 total = 0;
420
Sergei Shtylyov40d69ba2011-01-10 21:39:34 +0300421 pr_warning(DRV_NAME ": BIOS clock data not set.\n");
Sergei Shtylyovdfc7e3e2010-12-28 22:54:54 +0300422
423 /* This is the process the HPT371 BIOS is reported to use */
424 for (i = 0; i < 128; i++) {
425 pci_read_config_word(pdev, 0x78, &sr);
426 total += sr & 0x1FF;
427 udelay(15);
428 }
429 fcnt = total / 128;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400430 }
431 fcnt &= 0x1FF;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400432
Jeff Garzik669a5db2006-08-29 18:12:40 -0400433 freq = (fcnt * 77) / 192;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400434
Jeff Garzik669a5db2006-08-29 18:12:40 -0400435 /* Clamp to bands */
436 if (freq < 40)
437 return 33;
438 if (freq < 45)
439 return 40;
440 if (freq < 55)
441 return 50;
442 return 66;
443}
444
445/**
446 * hpt3x2n_init_one - Initialise an HPT37X/302
447 * @dev: PCI device
448 * @id: Entry in match table
449 *
450 * Initialise an HPT3x2n device. There are some interesting complications
451 * here. Firstly the chip may report 366 and be one of several variants.
452 * Secondly all the timings depend on the clock for the chip which we must
453 * detect and look up
454 *
455 * This is the known chip mappings. It may be missing a couple of later
456 * releases.
457 *
458 * Chip version PCI Rev Notes
459 * HPT372 4 (HPT366) 5 Other driver
460 * HPT372N 4 (HPT366) 6 UDMA133
461 * HPT372 5 (HPT372) 1 Other driver
462 * HPT372N 5 (HPT372) 2 UDMA133
463 * HPT302 6 (HPT302) * Other driver
464 * HPT302N 6 (HPT302) > 1 UDMA133
465 * HPT371 7 (HPT371) * Other driver
466 * HPT371N 7 (HPT371) > 1 UDMA133
467 * HPT374 8 (HPT374) * Other driver
468 * HPT372N 9 (HPT372N) * UDMA133
469 *
470 * (1) UDMA133 support depends on the bus clock
Jeff Garzik669a5db2006-08-29 18:12:40 -0400471 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400472
Jeff Garzik669a5db2006-08-29 18:12:40 -0400473static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
474{
Sergei Shtylyov8e834c22010-12-25 22:44:01 +0300475 /* HPT372N - UDMA133 */
476 static const struct ata_port_info info_hpt372n = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400477 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100478 .pio_mask = ATA_PIO4,
479 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400480 .udma_mask = ATA_UDMA6,
Sergei Shtylyov8e834c22010-12-25 22:44:01 +0300481 .port_ops = &hpt372n_port_ops
Jeff Garzik669a5db2006-08-29 18:12:40 -0400482 };
Sergei Shtylyov8e834c22010-12-25 22:44:01 +0300483 /* HPT302N and HPT371N - UDMA133 */
484 static const struct ata_port_info info_hpt3xxn = {
485 .flags = ATA_FLAG_SLAVE_POSS,
486 .pio_mask = ATA_PIO4,
487 .mwdma_mask = ATA_MWDMA2,
488 .udma_mask = ATA_UDMA6,
489 .port_ops = &hpt3xxn_port_ops
490 };
491 const struct ata_port_info *ppi[] = { &info_hpt3xxn, NULL };
Sergei Shtylyov89d3b362009-11-24 22:54:49 +0400492 u8 rev = dev->revision;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400493 u8 irqmask;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400494 unsigned int pci_mhz;
495 unsigned int f_low, f_high;
496 int adjust;
Alan Cox28e21c82007-04-26 00:19:25 -0700497 unsigned long iobase = pci_resource_start(dev, 4);
Sergei Shtylyov256ace92009-12-17 01:11:27 -0500498 void *hpriv = (void *)USE_DPLL;
Tejun Heof08048e2008-03-25 12:22:47 +0900499 int rc;
500
501 rc = pcim_enable_device(dev);
502 if (rc)
503 return rc;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400504
Sergei Shtylyovb197f132010-12-28 23:11:36 +0300505 switch (dev->device) {
506 case PCI_DEVICE_ID_TTI_HPT366:
507 /* 372N if rev >= 6 */
508 if (rev < 6)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400509 return -ENODEV;
Sergei Shtylyovb197f132010-12-28 23:11:36 +0300510 goto hpt372n;
511 case PCI_DEVICE_ID_TTI_HPT371:
512 /* 371N if rev >= 2 */
513 if (rev < 2)
514 return -ENODEV;
515 break;
516 case PCI_DEVICE_ID_TTI_HPT372:
517 /* 372N if rev >= 2 */
518 if (rev < 2)
519 return -ENODEV;
520 goto hpt372n;
521 case PCI_DEVICE_ID_TTI_HPT302:
522 /* 302N if rev >= 2 */
523 if (rev < 2)
524 return -ENODEV;
525 break;
526 case PCI_DEVICE_ID_TTI_HPT372N:
527hpt372n:
528 ppi[0] = &info_hpt372n;
529 break;
530 default:
Sergei Shtylyov40d69ba2011-01-10 21:39:34 +0300531 pr_err(DRV_NAME ": PCI table is bogus, please report (%d).\n",
Sergei Shtylyovb197f132010-12-28 23:11:36 +0300532 dev->device);
533 return -ENODEV;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400534 }
535
536 /* Ok so this is a chip we support */
537
538 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
539 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
540 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
541 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
542
543 pci_read_config_byte(dev, 0x5A, &irqmask);
544 irqmask &= ~0x10;
545 pci_write_config_byte(dev, 0x5a, irqmask);
546
Alan Cox28e21c82007-04-26 00:19:25 -0700547 /*
548 * HPT371 chips physically have only one channel, the secondary one,
549 * but the primary channel registers do exist! Go figure...
550 * So, we manually disable the non-existing channel here
551 * (if the BIOS hasn't done this already).
552 */
553 if (dev->device == PCI_DEVICE_ID_TTI_HPT371) {
554 u8 mcr1;
555 pci_read_config_byte(dev, 0x50, &mcr1);
556 mcr1 &= ~0x04;
557 pci_write_config_byte(dev, 0x50, mcr1);
558 }
559
Sergei Shtylyovb197f132010-12-28 23:11:36 +0300560 /*
561 * Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or
562 * 50 for UDMA100. Right now we always use 66
563 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400564
Jeff Garzik669a5db2006-08-29 18:12:40 -0400565 pci_mhz = hpt3x2n_pci_clock(dev);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400566
Jeff Garzik669a5db2006-08-29 18:12:40 -0400567 f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */
568 f_high = f_low + 2; /* Tolerance */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400569
Jeff Garzik669a5db2006-08-29 18:12:40 -0400570 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
571 /* PLL clock */
572 pci_write_config_byte(dev, 0x5B, 0x21);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400573
Jeff Garzik669a5db2006-08-29 18:12:40 -0400574 /* Unlike the 37x we don't try jiggling the frequency */
Sergei Shtylyovb197f132010-12-28 23:11:36 +0300575 for (adjust = 0; adjust < 8; adjust++) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400576 if (hpt3xn_calibrate_dpll(dev))
577 break;
578 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
579 }
Alan Cox28e21c82007-04-26 00:19:25 -0700580 if (adjust == 8) {
Sergei Shtylyov40d69ba2011-01-10 21:39:34 +0300581 pr_err(DRV_NAME ": DPLL did not stabilize!\n");
Alan Cox28e21c82007-04-26 00:19:25 -0700582 return -ENODEV;
583 }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400584
Sergei Shtylyov40d69ba2011-01-10 21:39:34 +0300585 pr_info(DRV_NAME ": bus clock %dMHz, using 66MHz DPLL.\n", pci_mhz);
Sergei Shtylyovb197f132010-12-28 23:11:36 +0300586
587 /*
588 * Set our private data up. We only need a few flags
589 * so we use it directly.
590 */
Sergei Shtylyov60661932009-12-07 23:25:52 +0400591 if (pci_mhz > 60)
Sergei Shtylyov256ace92009-12-17 01:11:27 -0500592 hpriv = (void *)(PCI66 | USE_DPLL);
Sergei Shtylyov60661932009-12-07 23:25:52 +0400593
594 /*
595 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
596 * the MISC. register to stretch the UltraDMA Tss timing.
597 * NOTE: This register is only writeable via I/O space.
598 */
599 if (dev->device == PCI_DEVICE_ID_TTI_HPT371)
600 outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400601
Jeff Garzik669a5db2006-08-29 18:12:40 -0400602 /* Now kick off ATA set up */
Tejun Heo1c5afdf2010-05-19 22:10:22 +0200603 return ata_pci_bmdma_init_one(dev, ppi, &hpt3x2n_sht, hpriv, 0);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400604}
605
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400606static const struct pci_device_id hpt3x2n[] = {
607 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
Alan Cox28e21c82007-04-26 00:19:25 -0700608 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400609 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
610 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
611 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), },
612
613 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400614};
615
616static struct pci_driver hpt3x2n_pci_driver = {
Sergei Shtylyovb197f132010-12-28 23:11:36 +0300617 .name = DRV_NAME,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400618 .id_table = hpt3x2n,
Sergei Shtylyovb197f132010-12-28 23:11:36 +0300619 .probe = hpt3x2n_init_one,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400620 .remove = ata_pci_remove_one
621};
622
623static int __init hpt3x2n_init(void)
624{
625 return pci_register_driver(&hpt3x2n_pci_driver);
626}
627
Jeff Garzik669a5db2006-08-29 18:12:40 -0400628static void __exit hpt3x2n_exit(void)
629{
630 pci_unregister_driver(&hpt3x2n_pci_driver);
631}
632
Jeff Garzik669a5db2006-08-29 18:12:40 -0400633MODULE_AUTHOR("Alan Cox");
Sergei Shtylyov0ca646d2010-12-28 21:46:40 +0300634MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3xxN");
Jeff Garzik669a5db2006-08-29 18:12:40 -0400635MODULE_LICENSE("GPL");
636MODULE_DEVICE_TABLE(pci, hpt3x2n);
637MODULE_VERSION(DRV_VERSION);
638
639module_init(hpt3x2n_init);
640module_exit(hpt3x2n_exit);