| Ali Bahar | 0e54f60 | 2011-08-23 13:53:37 +0800 | [diff] [blame^] | 1 | /****************************************************************************** |
| 2 | * |
| 3 | * Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of version 2 of the GNU General Public License as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along with |
| 15 | * this program; if not, write to the Free Software Foundation, Inc., |
| 16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA |
| 17 | * |
| 18 | * |
| 19 | ******************************************************************************/ |
| Larry Finger | 2865d42 | 2010-08-20 10:15:30 -0500 | [diff] [blame] | 20 | #ifndef __RTL8712_GP_BITDEF_H__ |
| 21 | #define __RTL8712_GP_BITDEF_H__ |
| 22 | |
| 23 | /*GPIO_CTRL*/ |
| 24 | #define _GPIO_MOD_MSK 0xFF000000 |
| 25 | #define _GPIO_MOD_SHT 24 |
| 26 | #define _GPIO_IO_SEL_MSK 0x00FF0000 |
| 27 | #define _GPIO_IO_SEL_SHT 16 |
| 28 | #define _GPIO_OUT_MSK 0x0000FF00 |
| 29 | #define _GPIO_OUT_SHT 8 |
| 30 | #define _GPIO_IN_MSK 0x000000FF |
| 31 | #define _GPIO_IN_SHT 0 |
| 32 | |
| 33 | /*SYS_PINMUX_CFG*/ |
| 34 | #define _GPIOSEL_MSK 0x0003 |
| 35 | #define _GPIOSEL_SHT 0 |
| 36 | |
| 37 | /*LED_CFG*/ |
| 38 | #define _LED1SV BIT(7) |
| 39 | #define _LED1CM_MSK 0x0070 |
| 40 | #define _LED1CM_SHT 4 |
| 41 | #define _LED0SV BIT(3) |
| 42 | #define _LED0CM_MSK 0x0007 |
| 43 | #define _LED0CM_SHT 0 |
| 44 | |
| 45 | /*PHY_REG*/ |
| 46 | #define _HST_RDRDY_SHT 0 |
| 47 | #define _HST_RDRDY_MSK 0xFF |
| 48 | #define _HST_RDRDY BIT(_HST_RDRDY_SHT) |
| 49 | #define _CPU_WTBUSY_SHT 1 |
| 50 | #define _CPU_WTBUSY_MSK 0xFF |
| 51 | #define _CPU_WTBUSY BIT(_CPU_WTBUSY_SHT) |
| 52 | |
| 53 | /* 11. General Purpose Registers (Offset: 0x02E0 - 0x02FF)*/ |
| 54 | |
| 55 | /* 8192S GPIO Config Setting (offset 0x2F1, 1 byte)*/ |
| 56 | |
| 57 | /*----------------------------------------------------------------------------*/ |
| 58 | |
| 59 | #define GPIOMUX_EN BIT(3) /* When this bit is set to "1", |
| 60 | * GPIO PINs will switch to MAC |
| 61 | * GPIO Function*/ |
| 62 | #define GPIOSEL_GPIO 0 /* UART or JTAG or pure GPIO*/ |
| 63 | #define GPIOSEL_PHYDBG 1 /* PHYDBG*/ |
| 64 | #define GPIOSEL_BT 2 /* BT_coex*/ |
| 65 | #define GPIOSEL_WLANDBG 3 /* WLANDBG*/ |
| 66 | #define GPIOSEL_GPIO_MASK (~(BIT(0)|BIT(1))) |
| 67 | /* HW Readio OFF switch (GPIO BIT) */ |
| 68 | #define HAL_8192S_HW_GPIO_OFF_BIT BIT(3) |
| 69 | #define HAL_8192S_HW_GPIO_OFF_MASK 0xF7 |
| 70 | #define HAL_8192S_HW_GPIO_WPS_BIT BIT(4) |
| 71 | |
| 72 | #endif /*__RTL8712_GP_BITDEF_H__*/ |
| 73 | |