blob: c85d1ffcc9558b5f64ed4e9aaea1963b7c8597c2 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
3 * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
4 * Takashi Iwai <tiwai@suse.de>
5 *
6 * Most of the hardware init stuffs are based on maestro3 driver for
7 * OSS/Free by Zach Brown. Many thanks to Zach!
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 *
24 * ChangeLog:
25 * Aug. 27, 2001
26 * - Fixed deadlock on capture
27 * - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
28 *
29 */
30
31#define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
32#define DRIVER_NAME "Maestro3"
33
Linus Torvalds1da177e2005-04-16 15:20:36 -070034#include <asm/io.h>
35#include <linux/delay.h>
36#include <linux/interrupt.h>
37#include <linux/init.h>
38#include <linux/pci.h>
Tobias Klauser9d2f9282006-03-22 10:53:19 +010039#include <linux/dma-mapping.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070040#include <linux/slab.h>
41#include <linux/vmalloc.h>
Paul Gortmaker65a77212011-07-15 13:13:37 -040042#include <linux/module.h>
Clemens Ladisch81d77242006-11-06 09:26:41 +010043#include <linux/firmware.h>
Hans de Goedeeb581ad2010-04-23 05:26:42 -040044#include <linux/input.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#include <sound/core.h>
46#include <sound/info.h>
47#include <sound/control.h>
48#include <sound/pcm.h>
49#include <sound/mpu401.h>
50#include <sound/ac97_codec.h>
51#include <sound/initval.h>
Clemens Ladisch81d77242006-11-06 09:26:41 +010052#include <asm/byteorder.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070053
54MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
55MODULE_DESCRIPTION("ESS Maestro3 PCI");
56MODULE_LICENSE("GPL");
57MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
58 "{ESS,ES1988},"
59 "{ESS,Allegro PCI},"
60 "{ESS,Allegro-1 PCI},"
61 "{ESS,Canyon3D-2/LE PCI}}");
Clemens Ladisch7e0af292007-05-03 17:59:54 +020062MODULE_FIRMWARE("ess/maestro3_assp_kernel.fw");
63MODULE_FIRMWARE("ess/maestro3_assp_minisrc.fw");
Linus Torvalds1da177e2005-04-16 15:20:36 -070064
65static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
66static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
Rusty Russella67ff6a2011-12-15 13:49:36 +103067static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
68static bool external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
Linus Torvalds1da177e2005-04-16 15:20:36 -070069static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
70
71module_param_array(index, int, NULL, 0444);
72MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
73module_param_array(id, charp, NULL, 0444);
74MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
75module_param_array(enable, bool, NULL, 0444);
76MODULE_PARM_DESC(enable, "Enable this soundcard.");
77module_param_array(external_amp, bool, NULL, 0444);
78MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
79module_param_array(amp_gpio, int, NULL, 0444);
80MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
81
82#define MAX_PLAYBACKS 2
83#define MAX_CAPTURES 1
84#define NR_DSPS (MAX_PLAYBACKS + MAX_CAPTURES)
85
86
87/*
88 * maestro3 registers
89 */
90
91/* Allegro PCI configuration registers */
92#define PCI_LEGACY_AUDIO_CTRL 0x40
93#define SOUND_BLASTER_ENABLE 0x00000001
94#define FM_SYNTHESIS_ENABLE 0x00000002
95#define GAME_PORT_ENABLE 0x00000004
96#define MPU401_IO_ENABLE 0x00000008
97#define MPU401_IRQ_ENABLE 0x00000010
98#define ALIAS_10BIT_IO 0x00000020
99#define SB_DMA_MASK 0x000000C0
100#define SB_DMA_0 0x00000040
101#define SB_DMA_1 0x00000040
102#define SB_DMA_R 0x00000080
103#define SB_DMA_3 0x000000C0
104#define SB_IRQ_MASK 0x00000700
105#define SB_IRQ_5 0x00000000
106#define SB_IRQ_7 0x00000100
107#define SB_IRQ_9 0x00000200
108#define SB_IRQ_10 0x00000300
109#define MIDI_IRQ_MASK 0x00003800
110#define SERIAL_IRQ_ENABLE 0x00004000
111#define DISABLE_LEGACY 0x00008000
112
113#define PCI_ALLEGRO_CONFIG 0x50
114#define SB_ADDR_240 0x00000004
115#define MPU_ADDR_MASK 0x00000018
116#define MPU_ADDR_330 0x00000000
117#define MPU_ADDR_300 0x00000008
118#define MPU_ADDR_320 0x00000010
119#define MPU_ADDR_340 0x00000018
120#define USE_PCI_TIMING 0x00000040
121#define POSTED_WRITE_ENABLE 0x00000080
122#define DMA_POLICY_MASK 0x00000700
123#define DMA_DDMA 0x00000000
124#define DMA_TDMA 0x00000100
125#define DMA_PCPCI 0x00000200
126#define DMA_WBDMA16 0x00000400
127#define DMA_WBDMA4 0x00000500
128#define DMA_WBDMA2 0x00000600
129#define DMA_WBDMA1 0x00000700
130#define DMA_SAFE_GUARD 0x00000800
131#define HI_PERF_GP_ENABLE 0x00001000
132#define PIC_SNOOP_MODE_0 0x00002000
133#define PIC_SNOOP_MODE_1 0x00004000
134#define SOUNDBLASTER_IRQ_MASK 0x00008000
135#define RING_IN_ENABLE 0x00010000
136#define SPDIF_TEST_MODE 0x00020000
137#define CLK_MULT_MODE_SELECT_2 0x00040000
138#define EEPROM_WRITE_ENABLE 0x00080000
139#define CODEC_DIR_IN 0x00100000
140#define HV_BUTTON_FROM_GD 0x00200000
141#define REDUCED_DEBOUNCE 0x00400000
142#define HV_CTRL_ENABLE 0x00800000
143#define SPDIF_ENABLE 0x01000000
144#define CLK_DIV_SELECT 0x06000000
145#define CLK_DIV_BY_48 0x00000000
146#define CLK_DIV_BY_49 0x02000000
147#define CLK_DIV_BY_50 0x04000000
148#define CLK_DIV_RESERVED 0x06000000
149#define PM_CTRL_ENABLE 0x08000000
150#define CLK_MULT_MODE_SELECT 0x30000000
151#define CLK_MULT_MODE_SHIFT 28
152#define CLK_MULT_MODE_0 0x00000000
153#define CLK_MULT_MODE_1 0x10000000
154#define CLK_MULT_MODE_2 0x20000000
155#define CLK_MULT_MODE_3 0x30000000
156#define INT_CLK_SELECT 0x40000000
157#define INT_CLK_MULT_RESET 0x80000000
158
159/* M3 */
160#define INT_CLK_SRC_NOT_PCI 0x00100000
161#define INT_CLK_MULT_ENABLE 0x80000000
162
163#define PCI_ACPI_CONTROL 0x54
164#define PCI_ACPI_D0 0x00000000
165#define PCI_ACPI_D1 0xB4F70000
166#define PCI_ACPI_D2 0xB4F7B4F7
167
168#define PCI_USER_CONFIG 0x58
169#define EXT_PCI_MASTER_ENABLE 0x00000001
170#define SPDIF_OUT_SELECT 0x00000002
171#define TEST_PIN_DIR_CTRL 0x00000004
172#define AC97_CODEC_TEST 0x00000020
173#define TRI_STATE_BUFFER 0x00000080
174#define IN_CLK_12MHZ_SELECT 0x00000100
175#define MULTI_FUNC_DISABLE 0x00000200
176#define EXT_MASTER_PAIR_SEL 0x00000400
177#define PCI_MASTER_SUPPORT 0x00000800
178#define STOP_CLOCK_ENABLE 0x00001000
179#define EAPD_DRIVE_ENABLE 0x00002000
180#define REQ_TRI_STATE_ENABLE 0x00004000
181#define REQ_LOW_ENABLE 0x00008000
182#define MIDI_1_ENABLE 0x00010000
183#define MIDI_2_ENABLE 0x00020000
184#define SB_AUDIO_SYNC 0x00040000
185#define HV_CTRL_TEST 0x00100000
186#define SOUNDBLASTER_TEST 0x00400000
187
188#define PCI_USER_CONFIG_C 0x5C
189
190#define PCI_DDMA_CTRL 0x60
191#define DDMA_ENABLE 0x00000001
192
193
194/* Allegro registers */
195#define HOST_INT_CTRL 0x18
196#define SB_INT_ENABLE 0x0001
197#define MPU401_INT_ENABLE 0x0002
198#define ASSP_INT_ENABLE 0x0010
199#define RING_INT_ENABLE 0x0020
200#define HV_INT_ENABLE 0x0040
201#define CLKRUN_GEN_ENABLE 0x0100
202#define HV_CTRL_TO_PME 0x0400
203#define SOFTWARE_RESET_ENABLE 0x8000
204
205/*
206 * should be using the above defines, probably.
207 */
208#define REGB_ENABLE_RESET 0x01
209#define REGB_STOP_CLOCK 0x10
210
211#define HOST_INT_STATUS 0x1A
212#define SB_INT_PENDING 0x01
213#define MPU401_INT_PENDING 0x02
214#define ASSP_INT_PENDING 0x10
215#define RING_INT_PENDING 0x20
216#define HV_INT_PENDING 0x40
217
218#define HARDWARE_VOL_CTRL 0x1B
219#define SHADOW_MIX_REG_VOICE 0x1C
220#define HW_VOL_COUNTER_VOICE 0x1D
221#define SHADOW_MIX_REG_MASTER 0x1E
222#define HW_VOL_COUNTER_MASTER 0x1F
223
224#define CODEC_COMMAND 0x30
225#define CODEC_READ_B 0x80
226
227#define CODEC_STATUS 0x30
228#define CODEC_BUSY_B 0x01
229
230#define CODEC_DATA 0x32
231
232#define RING_BUS_CTRL_A 0x36
233#define RAC_PME_ENABLE 0x0100
234#define RAC_SDFS_ENABLE 0x0200
235#define LAC_PME_ENABLE 0x0400
236#define LAC_SDFS_ENABLE 0x0800
237#define SERIAL_AC_LINK_ENABLE 0x1000
238#define IO_SRAM_ENABLE 0x2000
239#define IIS_INPUT_ENABLE 0x8000
240
241#define RING_BUS_CTRL_B 0x38
242#define SECOND_CODEC_ID_MASK 0x0003
243#define SPDIF_FUNC_ENABLE 0x0010
244#define SECOND_AC_ENABLE 0x0020
245#define SB_MODULE_INTF_ENABLE 0x0040
246#define SSPE_ENABLE 0x0040
247#define M3I_DOCK_ENABLE 0x0080
248
249#define SDO_OUT_DEST_CTRL 0x3A
250#define COMMAND_ADDR_OUT 0x0003
251#define PCM_LR_OUT_LOCAL 0x0000
252#define PCM_LR_OUT_REMOTE 0x0004
253#define PCM_LR_OUT_MUTE 0x0008
254#define PCM_LR_OUT_BOTH 0x000C
255#define LINE1_DAC_OUT_LOCAL 0x0000
256#define LINE1_DAC_OUT_REMOTE 0x0010
257#define LINE1_DAC_OUT_MUTE 0x0020
258#define LINE1_DAC_OUT_BOTH 0x0030
259#define PCM_CLS_OUT_LOCAL 0x0000
260#define PCM_CLS_OUT_REMOTE 0x0040
261#define PCM_CLS_OUT_MUTE 0x0080
262#define PCM_CLS_OUT_BOTH 0x00C0
263#define PCM_RLF_OUT_LOCAL 0x0000
264#define PCM_RLF_OUT_REMOTE 0x0100
265#define PCM_RLF_OUT_MUTE 0x0200
266#define PCM_RLF_OUT_BOTH 0x0300
267#define LINE2_DAC_OUT_LOCAL 0x0000
268#define LINE2_DAC_OUT_REMOTE 0x0400
269#define LINE2_DAC_OUT_MUTE 0x0800
270#define LINE2_DAC_OUT_BOTH 0x0C00
271#define HANDSET_OUT_LOCAL 0x0000
272#define HANDSET_OUT_REMOTE 0x1000
273#define HANDSET_OUT_MUTE 0x2000
274#define HANDSET_OUT_BOTH 0x3000
275#define IO_CTRL_OUT_LOCAL 0x0000
276#define IO_CTRL_OUT_REMOTE 0x4000
277#define IO_CTRL_OUT_MUTE 0x8000
278#define IO_CTRL_OUT_BOTH 0xC000
279
280#define SDO_IN_DEST_CTRL 0x3C
281#define STATUS_ADDR_IN 0x0003
282#define PCM_LR_IN_LOCAL 0x0000
283#define PCM_LR_IN_REMOTE 0x0004
284#define PCM_LR_RESERVED 0x0008
285#define PCM_LR_IN_BOTH 0x000C
286#define LINE1_ADC_IN_LOCAL 0x0000
287#define LINE1_ADC_IN_REMOTE 0x0010
288#define LINE1_ADC_IN_MUTE 0x0020
289#define MIC_ADC_IN_LOCAL 0x0000
290#define MIC_ADC_IN_REMOTE 0x0040
291#define MIC_ADC_IN_MUTE 0x0080
292#define LINE2_DAC_IN_LOCAL 0x0000
293#define LINE2_DAC_IN_REMOTE 0x0400
294#define LINE2_DAC_IN_MUTE 0x0800
295#define HANDSET_IN_LOCAL 0x0000
296#define HANDSET_IN_REMOTE 0x1000
297#define HANDSET_IN_MUTE 0x2000
298#define IO_STATUS_IN_LOCAL 0x0000
299#define IO_STATUS_IN_REMOTE 0x4000
300
301#define SPDIF_IN_CTRL 0x3E
302#define SPDIF_IN_ENABLE 0x0001
303
304#define GPIO_DATA 0x60
305#define GPIO_DATA_MASK 0x0FFF
306#define GPIO_HV_STATUS 0x3000
307#define GPIO_PME_STATUS 0x4000
308
309#define GPIO_MASK 0x64
310#define GPIO_DIRECTION 0x68
311#define GPO_PRIMARY_AC97 0x0001
312#define GPI_LINEOUT_SENSE 0x0004
313#define GPO_SECONDARY_AC97 0x0008
314#define GPI_VOL_DOWN 0x0010
315#define GPI_VOL_UP 0x0020
316#define GPI_IIS_CLK 0x0040
317#define GPI_IIS_LRCLK 0x0080
318#define GPI_IIS_DATA 0x0100
319#define GPI_DOCKING_STATUS 0x0100
320#define GPI_HEADPHONE_SENSE 0x0200
321#define GPO_EXT_AMP_SHUTDOWN 0x1000
322
323#define GPO_EXT_AMP_M3 1 /* default m3 amp */
324#define GPO_EXT_AMP_ALLEGRO 8 /* default allegro amp */
325
326/* M3 */
327#define GPO_M3_EXT_AMP_SHUTDN 0x0002
328
329#define ASSP_INDEX_PORT 0x80
330#define ASSP_MEMORY_PORT 0x82
331#define ASSP_DATA_PORT 0x84
332
333#define MPU401_DATA_PORT 0x98
334#define MPU401_STATUS_PORT 0x99
335
336#define CLK_MULT_DATA_PORT 0x9C
337
338#define ASSP_CONTROL_A 0xA2
339#define ASSP_0_WS_ENABLE 0x01
340#define ASSP_CTRL_A_RESERVED1 0x02
341#define ASSP_CTRL_A_RESERVED2 0x04
342#define ASSP_CLK_49MHZ_SELECT 0x08
343#define FAST_PLU_ENABLE 0x10
344#define ASSP_CTRL_A_RESERVED3 0x20
345#define DSP_CLK_36MHZ_SELECT 0x40
346
347#define ASSP_CONTROL_B 0xA4
348#define RESET_ASSP 0x00
349#define RUN_ASSP 0x01
350#define ENABLE_ASSP_CLOCK 0x00
351#define STOP_ASSP_CLOCK 0x10
352#define RESET_TOGGLE 0x40
353
354#define ASSP_CONTROL_C 0xA6
355#define ASSP_HOST_INT_ENABLE 0x01
356#define FM_ADDR_REMAP_DISABLE 0x02
357#define HOST_WRITE_PORT_ENABLE 0x08
358
359#define ASSP_HOST_INT_STATUS 0xAC
360#define DSP2HOST_REQ_PIORECORD 0x01
361#define DSP2HOST_REQ_I2SRATE 0x02
362#define DSP2HOST_REQ_TIMER 0x04
363
Linus Torvalds1da177e2005-04-16 15:20:36 -0700364/*
365 * ASSP control regs
366 */
367#define DSP_PORT_TIMER_COUNT 0x06
368
369#define DSP_PORT_MEMORY_INDEX 0x80
370
371#define DSP_PORT_MEMORY_TYPE 0x82
372#define MEMTYPE_INTERNAL_CODE 0x0002
373#define MEMTYPE_INTERNAL_DATA 0x0003
374#define MEMTYPE_MASK 0x0003
375
376#define DSP_PORT_MEMORY_DATA 0x84
377
378#define DSP_PORT_CONTROL_REG_A 0xA2
379#define DSP_PORT_CONTROL_REG_B 0xA4
380#define DSP_PORT_CONTROL_REG_C 0xA6
381
382#define REV_A_CODE_MEMORY_BEGIN 0x0000
383#define REV_A_CODE_MEMORY_END 0x0FFF
384#define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040
385#define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
386
387#define REV_B_CODE_MEMORY_BEGIN 0x0000
388#define REV_B_CODE_MEMORY_END 0x0BFF
389#define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040
390#define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
391
392#define REV_A_DATA_MEMORY_BEGIN 0x1000
393#define REV_A_DATA_MEMORY_END 0x2FFF
394#define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080
395#define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
396
397#define REV_B_DATA_MEMORY_BEGIN 0x1000
398#define REV_B_DATA_MEMORY_END 0x2BFF
399#define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080
400#define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
401
402
403#define NUM_UNITS_KERNEL_CODE 16
404#define NUM_UNITS_KERNEL_DATA 2
405
406#define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
407#define NUM_UNITS_KERNEL_DATA_WITH_HSP 5
408
409/*
410 * Kernel data layout
411 */
412
413#define DP_SHIFT_COUNT 7
414
415#define KDATA_BASE_ADDR 0x1000
416#define KDATA_BASE_ADDR2 0x1080
417
418#define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000)
419#define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001)
420#define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002)
421#define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003)
422#define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004)
423#define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005)
424#define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006)
425#define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007)
426#define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008)
427
428#define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009)
429#define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A)
430
431#define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B)
432#define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C)
433#define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D)
434#define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E)
435#define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F)
436#define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010)
437#define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011)
438#define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012)
439#define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013)
440#define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014)
441
442#define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015)
443#define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016)
444
445#define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017)
446#define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018)
447
448#define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019)
449#define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A)
450
451#define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B)
452#define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C)
453#define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D)
454
455#define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E)
456#define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F)
457#define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020)
458#define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021)
459#define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022)
460
461#define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023)
462#define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024)
463#define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025)
464
465#define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026)
466#define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027)
467#define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028)
468
469#define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029)
470#define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A)
471#define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B)
472#define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C)
473#define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D)
474#define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E)
475#define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F)
476#define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030)
477#define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031)
478#define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032)
479
480#define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033)
481#define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034)
482#define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035)
483
484#define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036)
485#define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037)
486
487#define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038)
488#define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039)
489#define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A)
490
491#define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B)
492#define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C)
493#define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D)
494#define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E)
495#define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F)
496#define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040)
497
498#define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041)
499#define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042)
500#define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043)
501#define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044)
502#define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045)
503#define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046)
504
505#define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047)
506#define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048)
507#define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049)
508#define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A)
509#define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B)
510#define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C)
511
512#define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D)
513#define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E)
514#define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F)
515#define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050)
516
517#define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051)
518#define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052)
519
520#define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053)
521#define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054)
522
523#define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055)
524#define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056)
525#define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057)
526#define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058)
527#define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059)
528
529#define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A)
530#define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B)
531
532#define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C)
533#define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D)
534#define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E)
535
536#define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F)
537#define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060)
538
539#define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061)
540
541#define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062)
542#define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063)
543#define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064)
544#define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065)
545#define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066)
546#define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067)
547#define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068)
548#define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069)
549#define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A)
550#define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B)
551#define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C)
552#define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D)
553
554#define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E)
555#define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F)
556#define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070)
557#define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071)
558
559#define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072)
560#define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073)
561
562#define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074)
563#define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075)
564#define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076)
565#define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077)
566
567#define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078)
568#define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079)
569#define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A)
570#define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B)
571#define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C)
572
573/*
574 * second 'segment' (?) reserved for mixer
575 * buffers..
576 */
577
578#define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000)
579#define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001)
580#define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002)
581#define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003)
582#define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004)
583#define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005)
584#define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006)
585#define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007)
586#define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008)
587#define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009)
588#define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A)
589#define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B)
590#define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C)
591#define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D)
592#define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E)
593#define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F)
594
595#define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010)
596#define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011)
597#define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012)
598#define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013)
599#define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014)
600#define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015)
601#define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016)
602#define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017)
603#define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018)
604#define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019)
605#define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A)
606
607#define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B)
608#define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C)
609#define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D)
610#define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E)
611#define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F)
612#define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020)
613
614#define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
615#define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
616#define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
617#define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
618
619/*
620 * client data area offsets
621 */
622#define CDATA_INSTANCE_READY 0x00
623
624#define CDATA_HOST_SRC_ADDRL 0x01
625#define CDATA_HOST_SRC_ADDRH 0x02
626#define CDATA_HOST_SRC_END_PLUS_1L 0x03
627#define CDATA_HOST_SRC_END_PLUS_1H 0x04
628#define CDATA_HOST_SRC_CURRENTL 0x05
629#define CDATA_HOST_SRC_CURRENTH 0x06
630
631#define CDATA_IN_BUF_CONNECT 0x07
632#define CDATA_OUT_BUF_CONNECT 0x08
633
634#define CDATA_IN_BUF_BEGIN 0x09
635#define CDATA_IN_BUF_END_PLUS_1 0x0A
636#define CDATA_IN_BUF_HEAD 0x0B
637#define CDATA_IN_BUF_TAIL 0x0C
638#define CDATA_OUT_BUF_BEGIN 0x0D
639#define CDATA_OUT_BUF_END_PLUS_1 0x0E
640#define CDATA_OUT_BUF_HEAD 0x0F
641#define CDATA_OUT_BUF_TAIL 0x10
642
643#define CDATA_DMA_CONTROL 0x11
644#define CDATA_RESERVED 0x12
645
646#define CDATA_FREQUENCY 0x13
647#define CDATA_LEFT_VOLUME 0x14
648#define CDATA_RIGHT_VOLUME 0x15
649#define CDATA_LEFT_SUR_VOL 0x16
650#define CDATA_RIGHT_SUR_VOL 0x17
651
652#define CDATA_HEADER_LEN 0x18
653
654#define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN
655#define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1)
656#define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2)
657#define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3)
658#define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8)
659#define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10)
660#define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16)
661#define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17)
662
663#define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 )
664#define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700665#define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
666#define MINISRC_BIQUAD_STAGE 2
667#define MINISRC_COEF_LOC 0x175
668
669#define DMACONTROL_BLOCK_MASK 0x000F
670#define DMAC_BLOCK0_SELECTOR 0x0000
671#define DMAC_BLOCK1_SELECTOR 0x0001
672#define DMAC_BLOCK2_SELECTOR 0x0002
673#define DMAC_BLOCK3_SELECTOR 0x0003
674#define DMAC_BLOCK4_SELECTOR 0x0004
675#define DMAC_BLOCK5_SELECTOR 0x0005
676#define DMAC_BLOCK6_SELECTOR 0x0006
677#define DMAC_BLOCK7_SELECTOR 0x0007
678#define DMAC_BLOCK8_SELECTOR 0x0008
679#define DMAC_BLOCK9_SELECTOR 0x0009
680#define DMAC_BLOCKA_SELECTOR 0x000A
681#define DMAC_BLOCKB_SELECTOR 0x000B
682#define DMAC_BLOCKC_SELECTOR 0x000C
683#define DMAC_BLOCKD_SELECTOR 0x000D
684#define DMAC_BLOCKE_SELECTOR 0x000E
685#define DMAC_BLOCKF_SELECTOR 0x000F
686#define DMACONTROL_PAGE_MASK 0x00F0
687#define DMAC_PAGE0_SELECTOR 0x0030
688#define DMAC_PAGE1_SELECTOR 0x0020
689#define DMAC_PAGE2_SELECTOR 0x0010
690#define DMAC_PAGE3_SELECTOR 0x0000
691#define DMACONTROL_AUTOREPEAT 0x1000
692#define DMACONTROL_STOPPED 0x2000
693#define DMACONTROL_DIRECTION 0x0100
694
695/*
696 * an arbitrary volume we set the internal
697 * volume settings to so that the ac97 volume
698 * range is a little less insane. 0x7fff is
699 * max.
700 */
701#define ARB_VOLUME ( 0x6800 )
702
703/*
704 */
705
Linus Torvalds1da177e2005-04-16 15:20:36 -0700706struct m3_list {
707 int curlen;
708 int mem_addr;
709 int max;
710};
711
Takashi Iwai3470c292005-11-17 15:05:09 +0100712struct m3_dma {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700713
714 int number;
Takashi Iwai3470c292005-11-17 15:05:09 +0100715 struct snd_pcm_substream *substream;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700716
717 struct assp_instance {
718 unsigned short code, data;
719 } inst;
720
721 int running;
722 int opened;
723
724 unsigned long buffer_addr;
725 int dma_size;
726 int period_size;
727 unsigned int hwptr;
728 int count;
729
730 int index[3];
731 struct m3_list *index_list[3];
732
733 int in_lists;
734
735 struct list_head list;
736
737};
738
739struct snd_m3 {
740
Takashi Iwai3470c292005-11-17 15:05:09 +0100741 struct snd_card *card;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700742
743 unsigned long iobase;
744
745 int irq;
746 unsigned int allegro_flag : 1;
747
Takashi Iwai3470c292005-11-17 15:05:09 +0100748 struct snd_ac97 *ac97;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700749
Takashi Iwai3470c292005-11-17 15:05:09 +0100750 struct snd_pcm *pcm;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700751
752 struct pci_dev *pci;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700753
754 int dacs_active;
755 int timer_users;
756
757 struct m3_list msrc_list;
758 struct m3_list mixer_list;
759 struct m3_list adc1_list;
760 struct m3_list dma_list;
761
762 /* for storing reset state..*/
763 u8 reset_state;
764
765 int external_amp;
Takashi Iwai1061eeb2006-11-24 15:36:46 +0100766 int amp_gpio; /* gpio pin # for external amp, -1 = default */
767 unsigned int hv_config; /* hardware-volume config bits */
768 unsigned irda_workaround :1; /* avoid to touch 0x10 on GPIO_DIRECTION
769 (e.g. for IrDA on Dell Inspirons) */
770 unsigned is_omnibook :1; /* Do HP OmniBook GPIO magic? */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700771
772 /* midi */
Takashi Iwai3470c292005-11-17 15:05:09 +0100773 struct snd_rawmidi *rmidi;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700774
775 /* pcm streams */
776 int num_substreams;
Takashi Iwai3470c292005-11-17 15:05:09 +0100777 struct m3_dma *substreams;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700778
779 spinlock_t reg_lock;
780
Hans de Goedeeb581ad2010-04-23 05:26:42 -0400781#ifdef CONFIG_SND_MAESTRO3_INPUT
782 struct input_dev *input_dev;
783 char phys[64]; /* physical device path */
784#else
Takashi Iwai3470c292005-11-17 15:05:09 +0100785 struct snd_kcontrol *master_switch;
786 struct snd_kcontrol *master_volume;
Hans de Goedeeb581ad2010-04-23 05:26:42 -0400787#endif
Takashi Iwai30bdee02011-06-14 13:57:02 +0200788 struct work_struct hwvol_work;
Hans de Goedeeb581ad2010-04-23 05:26:42 -0400789
Hans de Goede715aa672010-04-21 11:04:08 -0400790 unsigned int in_suspend;
Ville Syrjala82f008c2005-05-20 18:40:38 +0200791
Linus Torvalds1da177e2005-04-16 15:20:36 -0700792#ifdef CONFIG_PM
793 u16 *suspend_mem;
794#endif
Clemens Ladisch81d77242006-11-06 09:26:41 +0100795
796 const struct firmware *assp_kernel_image;
797 const struct firmware *assp_minisrc_image;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798};
799
800/*
801 * pci ids
802 */
Alexey Dobriyancebe41d2010-02-06 00:21:03 +0200803static DEFINE_PCI_DEVICE_TABLE(snd_m3_ids) = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700804 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
805 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
806 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
807 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
808 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
809 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
810 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
811 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
812 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
813 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
814 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
815 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
816 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
817 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
818 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
819 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
820 {0,},
821};
822
823MODULE_DEVICE_TABLE(pci, snd_m3_ids);
824
Takashi Iwai1061eeb2006-11-24 15:36:46 +0100825static struct snd_pci_quirk m3_amp_quirk_list[] __devinitdata = {
Hans de Goede7efbfd12010-04-21 11:04:06 -0400826 SND_PCI_QUIRK(0x0E11, 0x0094, "Compaq Evo N600c", 0x0c),
Takashi Iwai1061eeb2006-11-24 15:36:46 +0100827 SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d),
828 SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d),
829 SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03),
830 SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03),
831 { } /* END */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700832};
833
Takashi Iwai1061eeb2006-11-24 15:36:46 +0100834static struct snd_pci_quirk m3_irda_quirk_list[] __devinitdata = {
835 SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1),
836 SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1),
837 SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1),
838 { } /* END */
839};
840
841/* hardware volume quirks */
842static struct snd_pci_quirk m3_hv_quirk_list[] __devinitdata = {
Ville Syrjala82f008c2005-05-20 18:40:38 +0200843 /* Allegro chips */
Takashi Iwai1061eeb2006-11-24 15:36:46 +0100844 SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
845 SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
846 SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
847 SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
848 SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
849 SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
850 SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
851 SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
852 SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
853 SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
854 SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
855 SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
856 SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
857 SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
858 SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
859 SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
860 SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
861 SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
862 SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
863 SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
864 SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
865 SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
866 SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
867 SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
868 SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
869 SND_PCI_QUIRK(0x1033, 0x80F1, NULL,
870 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
871 SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */
872 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
873 SND_PCI_QUIRK(0x107B, 0x340A, NULL,
874 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
875 SND_PCI_QUIRK(0x107B, 0x3450, NULL,
876 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
877 SND_PCI_QUIRK(0x109F, 0x3134, NULL,
878 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
879 SND_PCI_QUIRK(0x109F, 0x3161, NULL,
880 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
881 SND_PCI_QUIRK(0x144D, 0x3280, NULL,
882 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
883 SND_PCI_QUIRK(0x144D, 0x3281, NULL,
884 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
885 SND_PCI_QUIRK(0x144D, 0xC002, NULL,
886 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
887 SND_PCI_QUIRK(0x144D, 0xC003, NULL,
888 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
889 SND_PCI_QUIRK(0x1509, 0x1740, NULL,
890 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
891 SND_PCI_QUIRK(0x1610, 0x0010, NULL,
892 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
893 SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE),
894 SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE),
895 SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE),
896 SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE),
897 SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE),
Ville Syrjala82f008c2005-05-20 18:40:38 +0200898 /* Maestro3 chips */
Takashi Iwai1061eeb2006-11-24 15:36:46 +0100899 SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE),
900 SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE),
901 SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE),
902 SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE),
903 SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE),
904 SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE),
905 SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE),
906 SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE),
907 SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE),
908 SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE),
909 SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE),
910 SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE),
911 SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE),
912 SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
913 SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
914 SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
915 SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
916 { } /* END */
917};
918
919/* HP Omnibook quirks */
920static struct snd_pci_quirk m3_omnibook_quirk_list[] __devinitdata = {
921 SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */
922 SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */
923 { } /* END */
Ville Syrjala82f008c2005-05-20 18:40:38 +0200924};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700925
926/*
927 * lowlevel functions
928 */
929
Takashi Iwai3470c292005-11-17 15:05:09 +0100930static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700931{
932 outw(value, chip->iobase + reg);
933}
934
Takashi Iwai3470c292005-11-17 15:05:09 +0100935static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700936{
937 return inw(chip->iobase + reg);
938}
939
Takashi Iwai3470c292005-11-17 15:05:09 +0100940static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700941{
942 outb(value, chip->iobase + reg);
943}
944
Takashi Iwai3470c292005-11-17 15:05:09 +0100945static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700946{
947 return inb(chip->iobase + reg);
948}
949
950/*
951 * access 16bit words to the code or data regions of the dsp's memory.
952 * index addresses 16bit words.
953 */
Takashi Iwai3470c292005-11-17 15:05:09 +0100954static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700955{
956 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
957 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
958 return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
959}
960
Takashi Iwai3470c292005-11-17 15:05:09 +0100961static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700962{
963 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
964 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
965 snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
966}
967
Takashi Iwai3470c292005-11-17 15:05:09 +0100968static void snd_m3_assp_halt(struct snd_m3 *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700969{
970 chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
Takashi Iwai5ba1e7b2005-06-30 13:47:58 +0200971 msleep(10);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700972 snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
973}
974
Takashi Iwai3470c292005-11-17 15:05:09 +0100975static void snd_m3_assp_continue(struct snd_m3 *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700976{
977 snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
978}
979
980
981/*
982 * This makes me sad. the maestro3 has lists
983 * internally that must be packed.. 0 terminates,
984 * apparently, or maybe all unused entries have
985 * to be 0, the lists have static lengths set
986 * by the binary code images.
987 */
988
Takashi Iwai3470c292005-11-17 15:05:09 +0100989static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700990{
991 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
992 list->mem_addr + list->curlen,
993 val);
994 return list->curlen++;
995}
996
Takashi Iwai3470c292005-11-17 15:05:09 +0100997static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700998{
999 u16 val;
1000 int lastindex = list->curlen - 1;
1001
1002 if (index != lastindex) {
1003 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1004 list->mem_addr + lastindex);
1005 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1006 list->mem_addr + index,
1007 val);
1008 }
1009
1010 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1011 list->mem_addr + lastindex,
1012 0);
1013
1014 list->curlen--;
1015}
1016
Takashi Iwai3470c292005-11-17 15:05:09 +01001017static void snd_m3_inc_timer_users(struct snd_m3 *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001018{
1019 chip->timer_users++;
1020 if (chip->timer_users != 1)
1021 return;
1022
1023 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1024 KDATA_TIMER_COUNT_RELOAD,
1025 240);
1026
1027 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1028 KDATA_TIMER_COUNT_CURRENT,
1029 240);
1030
1031 snd_m3_outw(chip,
1032 snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1033 HOST_INT_CTRL);
1034}
1035
Takashi Iwai3470c292005-11-17 15:05:09 +01001036static void snd_m3_dec_timer_users(struct snd_m3 *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001037{
1038 chip->timer_users--;
1039 if (chip->timer_users > 0)
1040 return;
1041
1042 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1043 KDATA_TIMER_COUNT_RELOAD,
1044 0);
1045
1046 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1047 KDATA_TIMER_COUNT_CURRENT,
1048 0);
1049
1050 snd_m3_outw(chip,
1051 snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1052 HOST_INT_CTRL);
1053}
1054
1055/*
1056 * start/stop
1057 */
1058
1059/* spinlock held! */
Takashi Iwai3470c292005-11-17 15:05:09 +01001060static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s,
1061 struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001062{
1063 if (! s || ! subs)
1064 return -EINVAL;
1065
1066 snd_m3_inc_timer_users(chip);
1067 switch (subs->stream) {
1068 case SNDRV_PCM_STREAM_PLAYBACK:
1069 chip->dacs_active++;
1070 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1071 s->inst.data + CDATA_INSTANCE_READY, 1);
1072 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1073 KDATA_MIXER_TASK_NUMBER,
1074 chip->dacs_active);
1075 break;
1076 case SNDRV_PCM_STREAM_CAPTURE:
Takashi Iwai3470c292005-11-17 15:05:09 +01001077 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001078 KDATA_ADC1_REQUEST, 1);
1079 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1080 s->inst.data + CDATA_INSTANCE_READY, 1);
1081 break;
1082 }
1083 return 0;
1084}
1085
1086/* spinlock held! */
Takashi Iwai3470c292005-11-17 15:05:09 +01001087static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s,
1088 struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001089{
1090 if (! s || ! subs)
1091 return -EINVAL;
1092
1093 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1094 s->inst.data + CDATA_INSTANCE_READY, 0);
1095 snd_m3_dec_timer_users(chip);
1096 switch (subs->stream) {
1097 case SNDRV_PCM_STREAM_PLAYBACK:
1098 chip->dacs_active--;
1099 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1100 KDATA_MIXER_TASK_NUMBER,
1101 chip->dacs_active);
1102 break;
1103 case SNDRV_PCM_STREAM_CAPTURE:
1104 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1105 KDATA_ADC1_REQUEST, 0);
1106 break;
1107 }
1108 return 0;
1109}
1110
1111static int
Takashi Iwai3470c292005-11-17 15:05:09 +01001112snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001113{
Takashi Iwai3470c292005-11-17 15:05:09 +01001114 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1115 struct m3_dma *s = subs->runtime->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001116 int err = -EINVAL;
1117
Takashi Iwaida3cec32008-08-08 17:12:14 +02001118 if (snd_BUG_ON(!s))
1119 return -ENXIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001120
1121 spin_lock(&chip->reg_lock);
1122 switch (cmd) {
1123 case SNDRV_PCM_TRIGGER_START:
1124 case SNDRV_PCM_TRIGGER_RESUME:
1125 if (s->running)
1126 err = -EBUSY;
1127 else {
1128 s->running = 1;
1129 err = snd_m3_pcm_start(chip, s, subs);
1130 }
1131 break;
1132 case SNDRV_PCM_TRIGGER_STOP:
1133 case SNDRV_PCM_TRIGGER_SUSPEND:
1134 if (! s->running)
1135 err = 0; /* should return error? */
1136 else {
1137 s->running = 0;
1138 err = snd_m3_pcm_stop(chip, s, subs);
1139 }
1140 break;
1141 }
1142 spin_unlock(&chip->reg_lock);
1143 return err;
1144}
1145
1146/*
1147 * setup
1148 */
1149static void
Takashi Iwai3470c292005-11-17 15:05:09 +01001150snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001151{
1152 int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
Takashi Iwai3470c292005-11-17 15:05:09 +01001153 struct snd_pcm_runtime *runtime = subs->runtime;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001154
1155 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1156 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1157 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1158 } else {
1159 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1160 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1161 }
1162 dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1163 dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1164
1165 s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1166 s->period_size = frames_to_bytes(runtime, runtime->period_size);
1167 s->hwptr = 0;
1168 s->count = 0;
1169
1170#define LO(x) ((x) & 0xffff)
1171#define HI(x) LO((x) >> 16)
1172
1173 /* host dma buffer pointers */
1174 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1175 s->inst.data + CDATA_HOST_SRC_ADDRL,
1176 LO(s->buffer_addr));
1177
1178 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1179 s->inst.data + CDATA_HOST_SRC_ADDRH,
1180 HI(s->buffer_addr));
1181
1182 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1183 s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1184 LO(s->buffer_addr + s->dma_size));
1185
1186 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1187 s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1188 HI(s->buffer_addr + s->dma_size));
1189
1190 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1191 s->inst.data + CDATA_HOST_SRC_CURRENTL,
1192 LO(s->buffer_addr));
1193
1194 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1195 s->inst.data + CDATA_HOST_SRC_CURRENTH,
1196 HI(s->buffer_addr));
1197#undef LO
1198#undef HI
1199
1200 /* dsp buffers */
1201
1202 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1203 s->inst.data + CDATA_IN_BUF_BEGIN,
1204 dsp_in_buffer);
1205
1206 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1207 s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1208 dsp_in_buffer + (dsp_in_size / 2));
1209
1210 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1211 s->inst.data + CDATA_IN_BUF_HEAD,
1212 dsp_in_buffer);
1213
1214 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1215 s->inst.data + CDATA_IN_BUF_TAIL,
1216 dsp_in_buffer);
1217
1218 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1219 s->inst.data + CDATA_OUT_BUF_BEGIN,
1220 dsp_out_buffer);
1221
1222 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1223 s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1224 dsp_out_buffer + (dsp_out_size / 2));
1225
1226 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1227 s->inst.data + CDATA_OUT_BUF_HEAD,
1228 dsp_out_buffer);
1229
1230 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1231 s->inst.data + CDATA_OUT_BUF_TAIL,
1232 dsp_out_buffer);
1233}
1234
Takashi Iwai3470c292005-11-17 15:05:09 +01001235static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s,
1236 struct snd_pcm_runtime *runtime)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001237{
1238 u32 freq;
1239
1240 /*
1241 * put us in the lists if we're not already there
1242 */
1243 if (! s->in_lists) {
1244 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1245 s->inst.data >> DP_SHIFT_COUNT);
1246 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1247 s->inst.data >> DP_SHIFT_COUNT);
1248 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1249 s->inst.data >> DP_SHIFT_COUNT);
1250 s->in_lists = 1;
1251 }
1252
1253 /* write to 'mono' word */
1254 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1255 s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1256 runtime->channels == 2 ? 0 : 1);
1257 /* write to '8bit' word */
1258 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1259 s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1260 snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1261
1262 /* set up dac/adc rate */
1263 freq = ((runtime->rate << 15) + 24000 ) / 48000;
1264 if (freq)
1265 freq--;
1266
1267 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1268 s->inst.data + CDATA_FREQUENCY,
1269 freq);
1270}
1271
1272
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02001273static const struct play_vals {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001274 u16 addr, val;
1275} pv[] = {
1276 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1277 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1278 {SRC3_DIRECTION_OFFSET, 0} ,
1279 /* +1, +2 are stereo/16 bit */
1280 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1281 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1282 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1283 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1284 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1285 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1286 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1287 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1288 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1289 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1290 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1291 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1292 {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1293 {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1294 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1295 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1296 {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1297};
1298
1299
1300/* the mode passed should be already shifted and masked */
1301static void
Takashi Iwai3470c292005-11-17 15:05:09 +01001302snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s,
1303 struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001304{
1305 unsigned int i;
1306
1307 /*
1308 * some per client initializers
1309 */
1310
1311 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1312 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1313 s->inst.data + 40 + 8);
1314
1315 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1316 s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1317 s->inst.code + MINISRC_COEF_LOC);
1318
1319 /* enable or disable low pass filter? */
1320 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1321 s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1322 subs->runtime->rate > 45000 ? 0xff : 0);
1323
1324 /* tell it which way dma is going? */
1325 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1326 s->inst.data + CDATA_DMA_CONTROL,
1327 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1328
1329 /*
1330 * set an armload of static initializers
1331 */
1332 for (i = 0; i < ARRAY_SIZE(pv); i++)
1333 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1334 s->inst.data + pv[i].addr, pv[i].val);
1335}
1336
1337/*
1338 * Native record driver
1339 */
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02001340static const struct rec_vals {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001341 u16 addr, val;
1342} rv[] = {
1343 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1344 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1345 {SRC3_DIRECTION_OFFSET, 1} ,
1346 /* +1, +2 are stereo/16 bit */
1347 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1348 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1349 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1350 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1351 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1352 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1353 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1354 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1355 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1356 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1357 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1358 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1359 {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1360 {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1361 {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1362 {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1363 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1364 {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1365 {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1366};
1367
1368static void
Takashi Iwai3470c292005-11-17 15:05:09 +01001369snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001370{
1371 unsigned int i;
1372
1373 /*
1374 * some per client initializers
1375 */
1376
1377 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1378 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1379 s->inst.data + 40 + 8);
1380
1381 /* tell it which way dma is going? */
1382 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1383 s->inst.data + CDATA_DMA_CONTROL,
1384 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1385 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1386
1387 /*
1388 * set an armload of static initializers
1389 */
1390 for (i = 0; i < ARRAY_SIZE(rv); i++)
1391 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1392 s->inst.data + rv[i].addr, rv[i].val);
1393}
1394
Takashi Iwai3470c292005-11-17 15:05:09 +01001395static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream,
1396 struct snd_pcm_hw_params *hw_params)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001397{
Takashi Iwai3470c292005-11-17 15:05:09 +01001398 struct m3_dma *s = substream->runtime->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001399 int err;
1400
1401 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1402 return err;
1403 /* set buffer address */
1404 s->buffer_addr = substream->runtime->dma_addr;
1405 if (s->buffer_addr & 0x3) {
Takashi Iwai99b359b2005-10-20 18:26:44 +02001406 snd_printk(KERN_ERR "oh my, not aligned\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001407 s->buffer_addr = s->buffer_addr & ~0x3;
1408 }
1409 return 0;
1410}
1411
Takashi Iwai3470c292005-11-17 15:05:09 +01001412static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001413{
Takashi Iwai3470c292005-11-17 15:05:09 +01001414 struct m3_dma *s;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001415
1416 if (substream->runtime->private_data == NULL)
1417 return 0;
Takashi Iwai3470c292005-11-17 15:05:09 +01001418 s = substream->runtime->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001419 snd_pcm_lib_free_pages(substream);
1420 s->buffer_addr = 0;
1421 return 0;
1422}
1423
1424static int
Takashi Iwai3470c292005-11-17 15:05:09 +01001425snd_m3_pcm_prepare(struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001426{
Takashi Iwai3470c292005-11-17 15:05:09 +01001427 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1428 struct snd_pcm_runtime *runtime = subs->runtime;
1429 struct m3_dma *s = runtime->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001430
Takashi Iwaida3cec32008-08-08 17:12:14 +02001431 if (snd_BUG_ON(!s))
1432 return -ENXIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001433
1434 if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1435 runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1436 return -EINVAL;
1437 if (runtime->rate > 48000 ||
1438 runtime->rate < 8000)
1439 return -EINVAL;
1440
1441 spin_lock_irq(&chip->reg_lock);
1442
1443 snd_m3_pcm_setup1(chip, s, subs);
1444
1445 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1446 snd_m3_playback_setup(chip, s, subs);
1447 else
1448 snd_m3_capture_setup(chip, s, subs);
1449
1450 snd_m3_pcm_setup2(chip, s, runtime);
1451
1452 spin_unlock_irq(&chip->reg_lock);
1453
1454 return 0;
1455}
1456
1457/*
1458 * get current pointer
1459 */
1460static unsigned int
Takashi Iwai3470c292005-11-17 15:05:09 +01001461snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001462{
1463 u16 hi = 0, lo = 0;
1464 int retry = 10;
1465 u32 addr;
1466
1467 /*
1468 * try and get a valid answer
1469 */
1470 while (retry--) {
1471 hi = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1472 s->inst.data + CDATA_HOST_SRC_CURRENTH);
1473
1474 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1475 s->inst.data + CDATA_HOST_SRC_CURRENTL);
1476
1477 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1478 s->inst.data + CDATA_HOST_SRC_CURRENTH))
1479 break;
1480 }
1481 addr = lo | ((u32)hi<<16);
1482 return (unsigned int)(addr - s->buffer_addr);
1483}
1484
1485static snd_pcm_uframes_t
Takashi Iwai3470c292005-11-17 15:05:09 +01001486snd_m3_pcm_pointer(struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001487{
Takashi Iwai3470c292005-11-17 15:05:09 +01001488 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001489 unsigned int ptr;
Takashi Iwai3470c292005-11-17 15:05:09 +01001490 struct m3_dma *s = subs->runtime->private_data;
Takashi Iwaida3cec32008-08-08 17:12:14 +02001491
1492 if (snd_BUG_ON(!s))
1493 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001494
1495 spin_lock(&chip->reg_lock);
1496 ptr = snd_m3_get_pointer(chip, s, subs);
1497 spin_unlock(&chip->reg_lock);
1498 return bytes_to_frames(subs->runtime, ptr);
1499}
1500
1501
1502/* update pointer */
1503/* spinlock held! */
Takashi Iwai3470c292005-11-17 15:05:09 +01001504static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001505{
Takashi Iwai3470c292005-11-17 15:05:09 +01001506 struct snd_pcm_substream *subs = s->substream;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001507 unsigned int hwptr;
1508 int diff;
1509
1510 if (! s->running)
1511 return;
1512
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02001513 hwptr = snd_m3_get_pointer(chip, s, subs);
1514
1515 /* try to avoid expensive modulo divisions */
1516 if (hwptr >= s->dma_size)
1517 hwptr %= s->dma_size;
1518
1519 diff = s->dma_size + hwptr - s->hwptr;
1520 if (diff >= s->dma_size)
1521 diff %= s->dma_size;
1522
Linus Torvalds1da177e2005-04-16 15:20:36 -07001523 s->hwptr = hwptr;
1524 s->count += diff;
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02001525
Linus Torvalds1da177e2005-04-16 15:20:36 -07001526 if (s->count >= (signed)s->period_size) {
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02001527
1528 if (s->count < 2 * (signed)s->period_size)
1529 s->count -= (signed)s->period_size;
1530 else
1531 s->count %= s->period_size;
1532
Linus Torvalds1da177e2005-04-16 15:20:36 -07001533 spin_unlock(&chip->reg_lock);
1534 snd_pcm_period_elapsed(subs);
1535 spin_lock(&chip->reg_lock);
1536 }
1537}
1538
Hans de Goede20133d42010-04-21 11:04:07 -04001539/* The m3's hardware volume works by incrementing / decrementing 2 counters
1540 (without wrap around) in response to volume button presses and then
1541 generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7
1542 of a byte wide register. The meaning of bits 0 and 4 is unknown. */
Takashi Iwai30bdee02011-06-14 13:57:02 +02001543static void snd_m3_update_hw_volume(struct work_struct *work)
Ville Syrjaladb68d152005-05-12 14:19:32 +02001544{
Takashi Iwai30bdee02011-06-14 13:57:02 +02001545 struct snd_m3 *chip = container_of(work, struct snd_m3, hwvol_work);
Ville Syrjaladb68d152005-05-12 14:19:32 +02001546 int x, val;
Ville Syrjaladb68d152005-05-12 14:19:32 +02001547
1548 /* Figure out which volume control button was pushed,
1549 based on differences from the default register
1550 values. */
1551 x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1552
Hans de Goede20133d42010-04-21 11:04:07 -04001553 /* Reset the volume counters to 4. Tests on the allegro integrated
1554 into a Compaq N600C laptop, have revealed that:
1555 1) Writing any value will result in the 2 counters being reset to
1556 4 so writing 0x88 is not strictly necessary
1557 2) Writing to any of the 4 involved registers will reset all 4
1558 of them (and reading them always returns the same value for all
1559 of them)
1560 It could be that a maestro deviates from this, so leave the code
1561 as is. */
Ville Syrjaladb68d152005-05-12 14:19:32 +02001562 outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1563 outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1564 outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1565 outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1566
Hans de Goede715aa672010-04-21 11:04:08 -04001567 /* Ignore spurious HV interrupts during suspend / resume, this avoids
1568 mistaking them for a mute button press. */
1569 if (chip->in_suspend)
1570 return;
1571
Hans de Goedeeb581ad2010-04-23 05:26:42 -04001572#ifndef CONFIG_SND_MAESTRO3_INPUT
Ville Syrjaladb68d152005-05-12 14:19:32 +02001573 if (!chip->master_switch || !chip->master_volume)
1574 return;
1575
Takashi Iwai30bdee02011-06-14 13:57:02 +02001576 val = snd_ac97_read(chip->ac97, AC97_MASTER);
Ville Syrjaladb68d152005-05-12 14:19:32 +02001577 switch (x) {
1578 case 0x88:
Hans de Goede20133d42010-04-21 11:04:07 -04001579 /* The counters have not changed, yet we've received a HV
1580 interrupt. According to tests run by various people this
1581 happens when pressing the mute button. */
Ville Syrjaladb68d152005-05-12 14:19:32 +02001582 val ^= 0x8000;
Ville Syrjaladb68d152005-05-12 14:19:32 +02001583 break;
1584 case 0xaa:
Hans de Goede20133d42010-04-21 11:04:07 -04001585 /* counters increased by 1 -> volume up */
Ville Syrjaladb68d152005-05-12 14:19:32 +02001586 if ((val & 0x7f) > 0)
1587 val--;
1588 if ((val & 0x7f00) > 0)
1589 val -= 0x0100;
Ville Syrjaladb68d152005-05-12 14:19:32 +02001590 break;
1591 case 0x66:
Hans de Goede20133d42010-04-21 11:04:07 -04001592 /* counters decreased by 1 -> volume down */
Ville Syrjaladb68d152005-05-12 14:19:32 +02001593 if ((val & 0x7f) < 0x1f)
1594 val++;
1595 if ((val & 0x7f00) < 0x1f00)
1596 val += 0x0100;
Ville Syrjaladb68d152005-05-12 14:19:32 +02001597 break;
1598 }
Takashi Iwai30bdee02011-06-14 13:57:02 +02001599 if (snd_ac97_update(chip->ac97, AC97_MASTER, val))
1600 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1601 &chip->master_switch->id);
Hans de Goedeeb581ad2010-04-23 05:26:42 -04001602#else
1603 if (!chip->input_dev)
1604 return;
1605
1606 val = 0;
1607 switch (x) {
1608 case 0x88:
1609 /* The counters have not changed, yet we've received a HV
1610 interrupt. According to tests run by various people this
1611 happens when pressing the mute button. */
1612 val = KEY_MUTE;
1613 break;
1614 case 0xaa:
1615 /* counters increased by 1 -> volume up */
1616 val = KEY_VOLUMEUP;
1617 break;
1618 case 0x66:
1619 /* counters decreased by 1 -> volume down */
1620 val = KEY_VOLUMEDOWN;
1621 break;
1622 }
1623
1624 if (val) {
1625 input_report_key(chip->input_dev, val, 1);
1626 input_sync(chip->input_dev);
1627 input_report_key(chip->input_dev, val, 0);
1628 input_sync(chip->input_dev);
1629 }
1630#endif
Ville Syrjaladb68d152005-05-12 14:19:32 +02001631}
1632
David Howells7d12e782006-10-05 14:55:46 +01001633static irqreturn_t snd_m3_interrupt(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001634{
Takashi Iwai3470c292005-11-17 15:05:09 +01001635 struct snd_m3 *chip = dev_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001636 u8 status;
1637 int i;
1638
1639 status = inb(chip->iobase + HOST_INT_STATUS);
1640
1641 if (status == 0xff)
1642 return IRQ_NONE;
Ville Syrjaladb68d152005-05-12 14:19:32 +02001643
1644 if (status & HV_INT_PENDING)
Takashi Iwai30bdee02011-06-14 13:57:02 +02001645 schedule_work(&chip->hwvol_work);
Ville Syrjaladb68d152005-05-12 14:19:32 +02001646
Linus Torvalds1da177e2005-04-16 15:20:36 -07001647 /*
1648 * ack an assp int if its running
1649 * and has an int pending
1650 */
1651 if (status & ASSP_INT_PENDING) {
1652 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1653 if (!(ctl & STOP_ASSP_CLOCK)) {
1654 ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1655 if (ctl & DSP2HOST_REQ_TIMER) {
1656 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1657 /* update adc/dac info if it was a timer int */
1658 spin_lock(&chip->reg_lock);
1659 for (i = 0; i < chip->num_substreams; i++) {
Takashi Iwai3470c292005-11-17 15:05:09 +01001660 struct m3_dma *s = &chip->substreams[i];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001661 if (s->running)
1662 snd_m3_update_ptr(chip, s);
1663 }
1664 spin_unlock(&chip->reg_lock);
1665 }
1666 }
1667 }
1668
1669#if 0 /* TODO: not supported yet */
1670 if ((status & MPU401_INT_PENDING) && chip->rmidi)
1671 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1672#endif
1673
1674 /* ack ints */
Ville Syrjala88491382005-05-12 14:14:28 +02001675 outb(status, chip->iobase + HOST_INT_STATUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001676
1677 return IRQ_HANDLED;
1678}
1679
1680
1681/*
1682 */
1683
Takashi Iwai3470c292005-11-17 15:05:09 +01001684static struct snd_pcm_hardware snd_m3_playback =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001685{
1686 .info = (SNDRV_PCM_INFO_MMAP |
1687 SNDRV_PCM_INFO_INTERLEAVED |
1688 SNDRV_PCM_INFO_MMAP_VALID |
1689 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1690 /*SNDRV_PCM_INFO_PAUSE |*/
1691 SNDRV_PCM_INFO_RESUME),
1692 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1693 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1694 .rate_min = 8000,
1695 .rate_max = 48000,
1696 .channels_min = 1,
1697 .channels_max = 2,
1698 .buffer_bytes_max = (512*1024),
1699 .period_bytes_min = 64,
1700 .period_bytes_max = (512*1024),
1701 .periods_min = 1,
1702 .periods_max = 1024,
1703};
1704
Takashi Iwai3470c292005-11-17 15:05:09 +01001705static struct snd_pcm_hardware snd_m3_capture =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001706{
1707 .info = (SNDRV_PCM_INFO_MMAP |
1708 SNDRV_PCM_INFO_INTERLEAVED |
1709 SNDRV_PCM_INFO_MMAP_VALID |
1710 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1711 /*SNDRV_PCM_INFO_PAUSE |*/
1712 SNDRV_PCM_INFO_RESUME),
1713 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1714 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1715 .rate_min = 8000,
1716 .rate_max = 48000,
1717 .channels_min = 1,
1718 .channels_max = 2,
1719 .buffer_bytes_max = (512*1024),
1720 .period_bytes_min = 64,
1721 .period_bytes_max = (512*1024),
1722 .periods_min = 1,
1723 .periods_max = 1024,
1724};
1725
1726
1727/*
1728 */
1729
1730static int
Takashi Iwai3470c292005-11-17 15:05:09 +01001731snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001732{
1733 int i;
Takashi Iwai3470c292005-11-17 15:05:09 +01001734 struct m3_dma *s;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001735
1736 spin_lock_irq(&chip->reg_lock);
1737 for (i = 0; i < chip->num_substreams; i++) {
1738 s = &chip->substreams[i];
1739 if (! s->opened)
1740 goto __found;
1741 }
1742 spin_unlock_irq(&chip->reg_lock);
1743 return -ENOMEM;
1744__found:
1745 s->opened = 1;
1746 s->running = 0;
1747 spin_unlock_irq(&chip->reg_lock);
1748
1749 subs->runtime->private_data = s;
1750 s->substream = subs;
1751
1752 /* set list owners */
1753 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1754 s->index_list[0] = &chip->mixer_list;
1755 } else
1756 s->index_list[0] = &chip->adc1_list;
1757 s->index_list[1] = &chip->msrc_list;
1758 s->index_list[2] = &chip->dma_list;
1759
1760 return 0;
1761}
1762
1763static void
Takashi Iwai3470c292005-11-17 15:05:09 +01001764snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001765{
Takashi Iwai3470c292005-11-17 15:05:09 +01001766 struct m3_dma *s = subs->runtime->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001767
1768 if (s == NULL)
1769 return; /* not opened properly */
1770
1771 spin_lock_irq(&chip->reg_lock);
1772 if (s->substream && s->running)
1773 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1774 if (s->in_lists) {
1775 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1776 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1777 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1778 s->in_lists = 0;
1779 }
1780 s->running = 0;
1781 s->opened = 0;
1782 spin_unlock_irq(&chip->reg_lock);
1783}
1784
1785static int
Takashi Iwai3470c292005-11-17 15:05:09 +01001786snd_m3_playback_open(struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001787{
Takashi Iwai3470c292005-11-17 15:05:09 +01001788 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1789 struct snd_pcm_runtime *runtime = subs->runtime;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001790 int err;
1791
1792 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1793 return err;
1794
1795 runtime->hw = snd_m3_playback;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001796
1797 return 0;
1798}
1799
1800static int
Takashi Iwai3470c292005-11-17 15:05:09 +01001801snd_m3_playback_close(struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001802{
Takashi Iwai3470c292005-11-17 15:05:09 +01001803 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001804
1805 snd_m3_substream_close(chip, subs);
1806 return 0;
1807}
1808
1809static int
Takashi Iwai3470c292005-11-17 15:05:09 +01001810snd_m3_capture_open(struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001811{
Takashi Iwai3470c292005-11-17 15:05:09 +01001812 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1813 struct snd_pcm_runtime *runtime = subs->runtime;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001814 int err;
1815
1816 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1817 return err;
1818
1819 runtime->hw = snd_m3_capture;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001820
1821 return 0;
1822}
1823
1824static int
Takashi Iwai3470c292005-11-17 15:05:09 +01001825snd_m3_capture_close(struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001826{
Takashi Iwai3470c292005-11-17 15:05:09 +01001827 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001828
1829 snd_m3_substream_close(chip, subs);
1830 return 0;
1831}
1832
1833/*
1834 * create pcm instance
1835 */
1836
Takashi Iwai3470c292005-11-17 15:05:09 +01001837static struct snd_pcm_ops snd_m3_playback_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001838 .open = snd_m3_playback_open,
1839 .close = snd_m3_playback_close,
1840 .ioctl = snd_pcm_lib_ioctl,
1841 .hw_params = snd_m3_pcm_hw_params,
1842 .hw_free = snd_m3_pcm_hw_free,
1843 .prepare = snd_m3_pcm_prepare,
1844 .trigger = snd_m3_pcm_trigger,
1845 .pointer = snd_m3_pcm_pointer,
1846};
1847
Takashi Iwai3470c292005-11-17 15:05:09 +01001848static struct snd_pcm_ops snd_m3_capture_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001849 .open = snd_m3_capture_open,
1850 .close = snd_m3_capture_close,
1851 .ioctl = snd_pcm_lib_ioctl,
1852 .hw_params = snd_m3_pcm_hw_params,
1853 .hw_free = snd_m3_pcm_hw_free,
1854 .prepare = snd_m3_pcm_prepare,
1855 .trigger = snd_m3_pcm_trigger,
1856 .pointer = snd_m3_pcm_pointer,
1857};
1858
1859static int __devinit
Takashi Iwai3470c292005-11-17 15:05:09 +01001860snd_m3_pcm(struct snd_m3 * chip, int device)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001861{
Takashi Iwai3470c292005-11-17 15:05:09 +01001862 struct snd_pcm *pcm;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001863 int err;
1864
1865 err = snd_pcm_new(chip->card, chip->card->driver, device,
1866 MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1867 if (err < 0)
1868 return err;
1869
1870 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1871 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1872
1873 pcm->private_data = chip;
1874 pcm->info_flags = 0;
1875 strcpy(pcm->name, chip->card->driver);
1876 chip->pcm = pcm;
1877
1878 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1879 snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1880
1881 return 0;
1882}
1883
1884
1885/*
1886 * ac97 interface
1887 */
1888
1889/*
1890 * Wait for the ac97 serial bus to be free.
1891 * return nonzero if the bus is still busy.
1892 */
Takashi Iwai3470c292005-11-17 15:05:09 +01001893static int snd_m3_ac97_wait(struct snd_m3 *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001894{
1895 int i = 10000;
1896
1897 do {
1898 if (! (snd_m3_inb(chip, 0x30) & 1))
1899 return 0;
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02001900 cpu_relax();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001901 } while (i-- > 0);
1902
Takashi Iwai99b359b2005-10-20 18:26:44 +02001903 snd_printk(KERN_ERR "ac97 serial bus busy\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001904 return 1;
1905}
1906
1907static unsigned short
Takashi Iwai3470c292005-11-17 15:05:09 +01001908snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001909{
Takashi Iwai3470c292005-11-17 15:05:09 +01001910 struct snd_m3 *chip = ac97->private_data;
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02001911 unsigned short data = 0xffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001912
1913 if (snd_m3_ac97_wait(chip))
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02001914 goto fail;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001915 snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
1916 if (snd_m3_ac97_wait(chip))
Takashi Iwai30bdee02011-06-14 13:57:02 +02001917 goto fail;
Ville Syrjaladb68d152005-05-12 14:19:32 +02001918 data = snd_m3_inw(chip, CODEC_DATA);
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02001919fail:
Ville Syrjaladb68d152005-05-12 14:19:32 +02001920 return data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001921}
1922
1923static void
Takashi Iwai3470c292005-11-17 15:05:09 +01001924snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001925{
Takashi Iwai3470c292005-11-17 15:05:09 +01001926 struct snd_m3 *chip = ac97->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001927
1928 if (snd_m3_ac97_wait(chip))
1929 return;
1930 snd_m3_outw(chip, val, CODEC_DATA);
1931 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1932}
1933
1934
1935static void snd_m3_remote_codec_config(int io, int isremote)
1936{
1937 isremote = isremote ? 1 : 0;
1938
1939 outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
1940 io + RING_BUS_CTRL_B);
1941 outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
1942 io + SDO_OUT_DEST_CTRL);
1943 outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
1944 io + SDO_IN_DEST_CTRL);
1945}
1946
1947/*
1948 * hack, returns non zero on err
1949 */
Takashi Iwai3470c292005-11-17 15:05:09 +01001950static int snd_m3_try_read_vendor(struct snd_m3 *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001951{
1952 u16 ret;
1953
1954 if (snd_m3_ac97_wait(chip))
1955 return 1;
1956
1957 snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
1958
1959 if (snd_m3_ac97_wait(chip))
1960 return 1;
1961
1962 ret = snd_m3_inw(chip, 0x32);
1963
1964 return (ret == 0) || (ret == 0xffff);
1965}
1966
Takashi Iwai3470c292005-11-17 15:05:09 +01001967static void snd_m3_ac97_reset(struct snd_m3 *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001968{
1969 u16 dir;
1970 int delay1 = 0, delay2 = 0, i;
1971 int io = chip->iobase;
1972
1973 if (chip->allegro_flag) {
1974 /*
1975 * the onboard codec on the allegro seems
1976 * to want to wait a very long time before
1977 * coming back to life
1978 */
1979 delay1 = 50;
1980 delay2 = 800;
1981 } else {
1982 /* maestro3 */
1983 delay1 = 20;
1984 delay2 = 500;
1985 }
1986
1987 for (i = 0; i < 5; i++) {
1988 dir = inw(io + GPIO_DIRECTION);
Takashi Iwai1061eeb2006-11-24 15:36:46 +01001989 if (!chip->irda_workaround)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001990 dir |= 0x10; /* assuming pci bus master? */
1991
1992 snd_m3_remote_codec_config(io, 0);
1993
1994 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
1995 udelay(20);
1996
1997 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
1998 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
1999 outw(0, io + GPIO_DATA);
2000 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2001
Nishanth Aravamudan8433a502005-10-24 15:02:37 +02002002 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002003
2004 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2005 udelay(5);
2006 /* ok, bring back the ac-link */
2007 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2008 outw(~0, io + GPIO_MASK);
2009
Nishanth Aravamudan8433a502005-10-24 15:02:37 +02002010 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002011
2012 if (! snd_m3_try_read_vendor(chip))
2013 break;
2014
2015 delay1 += 10;
2016 delay2 += 100;
2017
2018 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n",
2019 delay1, delay2);
2020 }
2021
2022#if 0
2023 /* more gung-ho reset that doesn't
2024 * seem to work anywhere :)
2025 */
2026 tmp = inw(io + RING_BUS_CTRL_A);
2027 outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
Takashi Iwai5ba1e7b2005-06-30 13:47:58 +02002028 msleep(20);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002029 outw(tmp, io + RING_BUS_CTRL_A);
Takashi Iwai5ba1e7b2005-06-30 13:47:58 +02002030 msleep(50);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002031#endif
2032}
2033
Takashi Iwai3470c292005-11-17 15:05:09 +01002034static int __devinit snd_m3_mixer(struct snd_m3 *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002035{
Takashi Iwai3470c292005-11-17 15:05:09 +01002036 struct snd_ac97_bus *pbus;
2037 struct snd_ac97_template ac97;
Hans de Goedeeb581ad2010-04-23 05:26:42 -04002038#ifndef CONFIG_SND_MAESTRO3_INPUT
Harvey Harrisone37273d2008-02-28 11:56:37 +01002039 struct snd_ctl_elem_id elem_id;
Hans de Goedeeb581ad2010-04-23 05:26:42 -04002040#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002041 int err;
Takashi Iwai3470c292005-11-17 15:05:09 +01002042 static struct snd_ac97_bus_ops ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002043 .write = snd_m3_ac97_write,
2044 .read = snd_m3_ac97_read,
2045 };
2046
2047 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2048 return err;
2049
2050 memset(&ac97, 0, sizeof(ac97));
2051 ac97.private_data = chip;
2052 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2053 return err;
2054
2055 /* seems ac97 PCM needs initialization.. hack hack.. */
2056 snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
Nishanth Aravamudan8433a502005-10-24 15:02:37 +02002057 schedule_timeout_uninterruptible(msecs_to_jiffies(100));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002058 snd_ac97_write(chip->ac97, AC97_PCM, 0);
2059
Hans de Goedeeb581ad2010-04-23 05:26:42 -04002060#ifndef CONFIG_SND_MAESTRO3_INPUT
Harvey Harrisone37273d2008-02-28 11:56:37 +01002061 memset(&elem_id, 0, sizeof(elem_id));
2062 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2063 strcpy(elem_id.name, "Master Playback Switch");
2064 chip->master_switch = snd_ctl_find_id(chip->card, &elem_id);
2065 memset(&elem_id, 0, sizeof(elem_id));
2066 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2067 strcpy(elem_id.name, "Master Playback Volume");
2068 chip->master_volume = snd_ctl_find_id(chip->card, &elem_id);
Hans de Goedeeb581ad2010-04-23 05:26:42 -04002069#endif
Ville Syrjaladb68d152005-05-12 14:19:32 +02002070
Linus Torvalds1da177e2005-04-16 15:20:36 -07002071 return 0;
2072}
2073
2074
Linus Torvalds1da177e2005-04-16 15:20:36 -07002075/*
2076 * initialize ASSP
2077 */
2078
2079#define MINISRC_LPF_LEN 10
Takashi Iwaif40b6892006-07-05 16:51:05 +02002080static const u16 minisrc_lpf[MINISRC_LPF_LEN] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002081 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2082 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2083};
2084
Takashi Iwaif40b6892006-07-05 16:51:05 +02002085static void snd_m3_assp_init(struct snd_m3 *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002086{
2087 unsigned int i;
David Woodhousefa6e1cb2008-05-29 11:58:27 +03002088 const u16 *data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002089
2090 /* zero kernel data */
2091 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2092 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2093 KDATA_BASE_ADDR + i, 0);
2094
2095 /* zero mixer data? */
2096 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2097 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2098 KDATA_BASE_ADDR2 + i, 0);
2099
2100 /* init dma pointer */
2101 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2102 KDATA_CURRENT_DMA,
2103 KDATA_DMA_XFER0);
2104
2105 /* write kernel into code memory.. */
David Woodhousefa6e1cb2008-05-29 11:58:27 +03002106 data = (const u16 *)chip->assp_kernel_image->data;
Clemens Ladisch81d77242006-11-06 09:26:41 +01002107 for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002108 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
David Woodhousefa6e1cb2008-05-29 11:58:27 +03002109 REV_B_CODE_MEMORY_BEGIN + i,
2110 le16_to_cpu(data[i]));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002111 }
2112
2113 /*
2114 * We only have this one client and we know that 0x400
2115 * is free in our kernel's mem map, so lets just
2116 * drop it there. It seems that the minisrc doesn't
2117 * need vectors, so we won't bother with them..
2118 */
David Woodhousefa6e1cb2008-05-29 11:58:27 +03002119 data = (const u16 *)chip->assp_minisrc_image->data;
Clemens Ladisch81d77242006-11-06 09:26:41 +01002120 for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002121 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
David Woodhousefa6e1cb2008-05-29 11:58:27 +03002122 0x400 + i, le16_to_cpu(data[i]));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002123 }
2124
2125 /*
2126 * write the coefficients for the low pass filter?
2127 */
2128 for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2129 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2130 0x400 + MINISRC_COEF_LOC + i,
2131 minisrc_lpf[i]);
2132 }
2133
2134 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2135 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2136 0x8000);
2137
2138 /*
2139 * the minisrc is the only thing on
2140 * our task list..
2141 */
2142 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2143 KDATA_TASK0,
2144 0x400);
2145
2146 /*
2147 * init the mixer number..
2148 */
2149
2150 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2151 KDATA_MIXER_TASK_NUMBER,0);
2152
2153 /*
2154 * EXTREME KERNEL MASTER VOLUME
2155 */
2156 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2157 KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2158 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2159 KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2160
2161 chip->mixer_list.curlen = 0;
2162 chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2163 chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2164 chip->adc1_list.curlen = 0;
2165 chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2166 chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2167 chip->dma_list.curlen = 0;
2168 chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2169 chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2170 chip->msrc_list.curlen = 0;
2171 chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2172 chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2173}
2174
2175
Takashi Iwai3470c292005-11-17 15:05:09 +01002176static int __devinit snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002177{
2178 int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2179 MINISRC_IN_BUFFER_SIZE / 2 +
2180 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2181 int address, i;
2182
2183 /*
2184 * the revb memory map has 0x1100 through 0x1c00
2185 * free.
2186 */
2187
2188 /*
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02002189 * align instance address to 256 bytes so that its
Linus Torvalds1da177e2005-04-16 15:20:36 -07002190 * shifted list address is aligned.
2191 * list address = (mem address >> 1) >> 7;
2192 */
Clemens Ladisch7ab39922006-10-09 08:13:32 +02002193 data_bytes = ALIGN(data_bytes, 256);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002194 address = 0x1100 + ((data_bytes/2) * index);
2195
2196 if ((address + (data_bytes/2)) >= 0x1c00) {
Takashi Iwai99b359b2005-10-20 18:26:44 +02002197 snd_printk(KERN_ERR "no memory for %d bytes at ind %d (addr 0x%x)\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07002198 data_bytes, index, address);
2199 return -ENOMEM;
2200 }
2201
2202 s->number = index;
2203 s->inst.code = 0x400;
2204 s->inst.data = address;
2205
2206 for (i = data_bytes / 2; i > 0; address++, i--) {
2207 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2208 address, 0);
2209 }
2210
2211 return 0;
2212}
2213
2214
2215/*
2216 * this works for the reference board, have to find
2217 * out about others
2218 *
2219 * this needs more magic for 4 speaker, but..
2220 */
2221static void
Takashi Iwai3470c292005-11-17 15:05:09 +01002222snd_m3_amp_enable(struct snd_m3 *chip, int enable)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002223{
2224 int io = chip->iobase;
2225 u16 gpo, polarity;
2226
2227 if (! chip->external_amp)
2228 return;
2229
2230 polarity = enable ? 0 : 1;
2231 polarity = polarity << chip->amp_gpio;
2232 gpo = 1 << chip->amp_gpio;
2233
2234 outw(~gpo, io + GPIO_MASK);
2235
2236 outw(inw(io + GPIO_DIRECTION) | gpo,
2237 io + GPIO_DIRECTION);
2238
2239 outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2240 io + GPIO_DATA);
2241
2242 outw(0xffff, io + GPIO_MASK);
2243}
2244
Ville Syrjälä8b83afe2008-06-03 20:52:10 +03002245static void
2246snd_m3_hv_init(struct snd_m3 *chip)
2247{
2248 unsigned long io = chip->iobase;
2249 u16 val = GPI_VOL_DOWN | GPI_VOL_UP;
2250
2251 if (!chip->is_omnibook)
2252 return;
2253
2254 /*
2255 * Volume buttons on some HP OmniBook laptops
2256 * require some GPIO magic to work correctly.
2257 */
2258 outw(0xffff, io + GPIO_MASK);
2259 outw(0x0000, io + GPIO_DATA);
2260
2261 outw(~val, io + GPIO_MASK);
2262 outw(inw(io + GPIO_DIRECTION) & ~val, io + GPIO_DIRECTION);
2263 outw(val, io + GPIO_MASK);
2264
2265 outw(0xffff, io + GPIO_MASK);
2266}
2267
Linus Torvalds1da177e2005-04-16 15:20:36 -07002268static int
Takashi Iwai3470c292005-11-17 15:05:09 +01002269snd_m3_chip_init(struct snd_m3 *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002270{
2271 struct pci_dev *pcidev = chip->pci;
Ville Syrjaladb68d152005-05-12 14:19:32 +02002272 unsigned long io = chip->iobase;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002273 u32 n;
2274 u16 w;
2275 u8 t; /* makes as much sense as 'n', no? */
2276
2277 pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2278 w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2279 MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2280 DISABLE_LEGACY);
2281 pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2282
2283 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
Ville Syrjala82f008c2005-05-20 18:40:38 +02002284 n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
Takashi Iwai1061eeb2006-11-24 15:36:46 +01002285 n |= chip->hv_config;
Ville Syrjala82f008c2005-05-20 18:40:38 +02002286 /* For some reason we must always use reduced debounce. */
2287 n |= REDUCED_DEBOUNCE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002288 n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2289 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2290
2291 outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2292 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2293 n &= ~INT_CLK_SELECT;
2294 if (!chip->allegro_flag) {
2295 n &= ~INT_CLK_MULT_ENABLE;
2296 n |= INT_CLK_SRC_NOT_PCI;
2297 }
2298 n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2299 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2300
2301 if (chip->allegro_flag) {
2302 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2303 n |= IN_CLK_12MHZ_SELECT;
2304 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2305 }
2306
2307 t = inb(chip->iobase + ASSP_CONTROL_A);
2308 t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
2309 t |= ASSP_CLK_49MHZ_SELECT;
2310 t |= ASSP_0_WS_ENABLE;
2311 outb(t, chip->iobase + ASSP_CONTROL_A);
2312
Charles R. Anderson051b5162005-10-18 18:04:36 +02002313 snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002314 outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2315
Ville Syrjaladb68d152005-05-12 14:19:32 +02002316 outb(0x00, io + HARDWARE_VOL_CTRL);
2317 outb(0x88, io + SHADOW_MIX_REG_VOICE);
2318 outb(0x88, io + HW_VOL_COUNTER_VOICE);
2319 outb(0x88, io + SHADOW_MIX_REG_MASTER);
2320 outb(0x88, io + HW_VOL_COUNTER_MASTER);
2321
Linus Torvalds1da177e2005-04-16 15:20:36 -07002322 return 0;
2323}
2324
2325static void
Takashi Iwai3470c292005-11-17 15:05:09 +01002326snd_m3_enable_ints(struct snd_m3 *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002327{
2328 unsigned long io = chip->iobase;
Takashi Iwai5ba1e7b2005-06-30 13:47:58 +02002329 unsigned short val;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002330
2331 /* TODO: MPU401 not supported yet */
Takashi Iwai5ba1e7b2005-06-30 13:47:58 +02002332 val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
Takashi Iwai1061eeb2006-11-24 15:36:46 +01002333 if (chip->hv_config & HV_CTRL_ENABLE)
Takashi Iwai5ba1e7b2005-06-30 13:47:58 +02002334 val |= HV_INT_ENABLE;
Ville Syrjälä1bde78b2010-05-07 00:12:13 +03002335 outb(val, chip->iobase + HOST_INT_STATUS);
Takashi Iwai5ba1e7b2005-06-30 13:47:58 +02002336 outw(val, io + HOST_INT_CTRL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002337 outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2338 io + ASSP_CONTROL_C);
2339}
2340
2341
2342/*
2343 */
2344
Takashi Iwai3470c292005-11-17 15:05:09 +01002345static int snd_m3_free(struct snd_m3 *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002346{
Takashi Iwai3470c292005-11-17 15:05:09 +01002347 struct m3_dma *s;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002348 int i;
2349
Takashi Iwai30bdee02011-06-14 13:57:02 +02002350 cancel_work_sync(&chip->hwvol_work);
Hans de Goedeeb581ad2010-04-23 05:26:42 -04002351#ifdef CONFIG_SND_MAESTRO3_INPUT
2352 if (chip->input_dev)
2353 input_unregister_device(chip->input_dev);
2354#endif
2355
Linus Torvalds1da177e2005-04-16 15:20:36 -07002356 if (chip->substreams) {
2357 spin_lock_irq(&chip->reg_lock);
2358 for (i = 0; i < chip->num_substreams; i++) {
2359 s = &chip->substreams[i];
2360 /* check surviving pcms; this should not happen though.. */
2361 if (s->substream && s->running)
2362 snd_m3_pcm_stop(chip, s, s->substream);
2363 }
2364 spin_unlock_irq(&chip->reg_lock);
2365 kfree(chip->substreams);
2366 }
2367 if (chip->iobase) {
Ville Syrjala88491382005-05-12 14:14:28 +02002368 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002369 }
2370
2371#ifdef CONFIG_PM
2372 vfree(chip->suspend_mem);
2373#endif
2374
Jeff Garzikf000fd82008-04-22 13:50:34 +02002375 if (chip->irq >= 0)
Takashi Iwai3470c292005-11-17 15:05:09 +01002376 free_irq(chip->irq, chip);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002377
2378 if (chip->iobase)
2379 pci_release_regions(chip->pci);
2380
Takashi Iwaib7dd2b32007-04-26 14:13:44 +02002381 release_firmware(chip->assp_kernel_image);
2382 release_firmware(chip->assp_minisrc_image);
Clemens Ladisch81d77242006-11-06 09:26:41 +01002383
Linus Torvalds1da177e2005-04-16 15:20:36 -07002384 pci_disable_device(chip->pci);
2385 kfree(chip);
2386 return 0;
2387}
2388
2389
2390/*
2391 * APM support
2392 */
2393#ifdef CONFIG_PM
Takashi Iwai68cb2b52012-07-02 15:20:37 +02002394static int m3_suspend(struct device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002395{
Takashi Iwai68cb2b52012-07-02 15:20:37 +02002396 struct pci_dev *pci = to_pci_dev(dev);
2397 struct snd_card *card = dev_get_drvdata(dev);
Takashi Iwai0e2364a2005-11-17 16:10:19 +01002398 struct snd_m3 *chip = card->private_data;
Harvey Harrisone37273d2008-02-28 11:56:37 +01002399 int i, dsp_index;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002400
2401 if (chip->suspend_mem == NULL)
2402 return 0;
2403
Hans de Goede715aa672010-04-21 11:04:08 -04002404 chip->in_suspend = 1;
Takashi Iwai30bdee02011-06-14 13:57:02 +02002405 cancel_work_sync(&chip->hwvol_work);
Takashi Iwai0e2364a2005-11-17 16:10:19 +01002406 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002407 snd_pcm_suspend_all(chip->pcm);
2408 snd_ac97_suspend(chip->ac97);
2409
Takashi Iwai5ba1e7b2005-06-30 13:47:58 +02002410 msleep(10); /* give the assp a chance to idle.. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002411
2412 snd_m3_assp_halt(chip);
2413
2414 /* save dsp image */
Harvey Harrisone37273d2008-02-28 11:56:37 +01002415 dsp_index = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002416 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
Harvey Harrisone37273d2008-02-28 11:56:37 +01002417 chip->suspend_mem[dsp_index++] =
Linus Torvalds1da177e2005-04-16 15:20:36 -07002418 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2419 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
Harvey Harrisone37273d2008-02-28 11:56:37 +01002420 chip->suspend_mem[dsp_index++] =
Linus Torvalds1da177e2005-04-16 15:20:36 -07002421 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2422
Takashi Iwai0e2364a2005-11-17 16:10:19 +01002423 pci_disable_device(pci);
2424 pci_save_state(pci);
Takashi Iwai68cb2b52012-07-02 15:20:37 +02002425 pci_set_power_state(pci, PCI_D3hot);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002426 return 0;
2427}
2428
Takashi Iwai68cb2b52012-07-02 15:20:37 +02002429static int m3_resume(struct device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002430{
Takashi Iwai68cb2b52012-07-02 15:20:37 +02002431 struct pci_dev *pci = to_pci_dev(dev);
2432 struct snd_card *card = dev_get_drvdata(dev);
Takashi Iwai0e2364a2005-11-17 16:10:19 +01002433 struct snd_m3 *chip = card->private_data;
Harvey Harrisone37273d2008-02-28 11:56:37 +01002434 int i, dsp_index;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002435
2436 if (chip->suspend_mem == NULL)
2437 return 0;
2438
Takashi Iwai30b35392006-10-11 18:52:53 +02002439 pci_set_power_state(pci, PCI_D0);
Takashi Iwai0e2364a2005-11-17 16:10:19 +01002440 pci_restore_state(pci);
Takashi Iwai30b35392006-10-11 18:52:53 +02002441 if (pci_enable_device(pci) < 0) {
2442 printk(KERN_ERR "maestor3: pci_enable_device failed, "
2443 "disabling device\n");
2444 snd_card_disconnect(card);
2445 return -EIO;
2446 }
Takashi Iwai0e2364a2005-11-17 16:10:19 +01002447 pci_set_master(pci);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002448
2449 /* first lets just bring everything back. .*/
2450 snd_m3_outw(chip, 0, 0x54);
2451 snd_m3_outw(chip, 0, 0x56);
2452
2453 snd_m3_chip_init(chip);
2454 snd_m3_assp_halt(chip);
2455 snd_m3_ac97_reset(chip);
2456
2457 /* restore dsp image */
Harvey Harrisone37273d2008-02-28 11:56:37 +01002458 dsp_index = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002459 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2460 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
Harvey Harrisone37273d2008-02-28 11:56:37 +01002461 chip->suspend_mem[dsp_index++]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002462 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2463 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
Harvey Harrisone37273d2008-02-28 11:56:37 +01002464 chip->suspend_mem[dsp_index++]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002465
2466 /* tell the dma engine to restart itself */
2467 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2468 KDATA_DMA_ACTIVE, 0);
2469
2470 /* restore ac97 registers */
2471 snd_ac97_resume(chip->ac97);
2472
2473 snd_m3_assp_continue(chip);
2474 snd_m3_enable_ints(chip);
2475 snd_m3_amp_enable(chip, 1);
2476
Ville Syrjälä8b83afe2008-06-03 20:52:10 +03002477 snd_m3_hv_init(chip);
2478
Takashi Iwai0e2364a2005-11-17 16:10:19 +01002479 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
Hans de Goede715aa672010-04-21 11:04:08 -04002480 chip->in_suspend = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002481 return 0;
2482}
Takashi Iwai68cb2b52012-07-02 15:20:37 +02002483
2484static SIMPLE_DEV_PM_OPS(m3_pm, m3_suspend, m3_resume);
2485#define M3_PM_OPS &m3_pm
2486#else
2487#define M3_PM_OPS NULL
Linus Torvalds1da177e2005-04-16 15:20:36 -07002488#endif /* CONFIG_PM */
2489
Hans de Goedeeb581ad2010-04-23 05:26:42 -04002490#ifdef CONFIG_SND_MAESTRO3_INPUT
2491static int __devinit snd_m3_input_register(struct snd_m3 *chip)
2492{
2493 struct input_dev *input_dev;
2494 int err;
2495
2496 input_dev = input_allocate_device();
2497 if (!input_dev)
2498 return -ENOMEM;
2499
2500 snprintf(chip->phys, sizeof(chip->phys), "pci-%s/input0",
2501 pci_name(chip->pci));
2502
2503 input_dev->name = chip->card->driver;
2504 input_dev->phys = chip->phys;
2505 input_dev->id.bustype = BUS_PCI;
2506 input_dev->id.vendor = chip->pci->vendor;
2507 input_dev->id.product = chip->pci->device;
2508 input_dev->dev.parent = &chip->pci->dev;
2509
2510 __set_bit(EV_KEY, input_dev->evbit);
2511 __set_bit(KEY_MUTE, input_dev->keybit);
2512 __set_bit(KEY_VOLUMEDOWN, input_dev->keybit);
2513 __set_bit(KEY_VOLUMEUP, input_dev->keybit);
2514
2515 err = input_register_device(input_dev);
2516 if (err) {
2517 input_free_device(input_dev);
2518 return err;
2519 }
2520
2521 chip->input_dev = input_dev;
2522 return 0;
2523}
2524#endif /* CONFIG_INPUT */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002525
2526/*
2527 */
2528
Takashi Iwai3470c292005-11-17 15:05:09 +01002529static int snd_m3_dev_free(struct snd_device *device)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002530{
Takashi Iwai3470c292005-11-17 15:05:09 +01002531 struct snd_m3 *chip = device->device_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002532 return snd_m3_free(chip);
2533}
2534
2535static int __devinit
Takashi Iwai3470c292005-11-17 15:05:09 +01002536snd_m3_create(struct snd_card *card, struct pci_dev *pci,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002537 int enable_amp,
2538 int amp_gpio,
Takashi Iwai3470c292005-11-17 15:05:09 +01002539 struct snd_m3 **chip_ret)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002540{
Takashi Iwai3470c292005-11-17 15:05:09 +01002541 struct snd_m3 *chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002542 int i, err;
Takashi Iwai1061eeb2006-11-24 15:36:46 +01002543 const struct snd_pci_quirk *quirk;
Takashi Iwai3470c292005-11-17 15:05:09 +01002544 static struct snd_device_ops ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002545 .dev_free = snd_m3_dev_free,
2546 };
2547
2548 *chip_ret = NULL;
2549
2550 if (pci_enable_device(pci))
2551 return -EIO;
2552
2553 /* check, if we can restrict PCI DMA transfers to 28 bits */
Yang Hongyangce0b6202009-04-06 19:01:17 -07002554 if (pci_set_dma_mask(pci, DMA_BIT_MASK(28)) < 0 ||
2555 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(28)) < 0) {
Takashi Iwai99b359b2005-10-20 18:26:44 +02002556 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002557 pci_disable_device(pci);
2558 return -ENXIO;
2559 }
2560
Takashi Iwaie560d8d2005-09-09 14:21:46 +02002561 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002562 if (chip == NULL) {
2563 pci_disable_device(pci);
2564 return -ENOMEM;
2565 }
2566
2567 spin_lock_init(&chip->reg_lock);
Takashi Iwai5ba1e7b2005-06-30 13:47:58 +02002568
Linus Torvalds1da177e2005-04-16 15:20:36 -07002569 switch (pci->device) {
2570 case PCI_DEVICE_ID_ESS_ALLEGRO:
2571 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2572 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2573 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2574 chip->allegro_flag = 1;
2575 break;
2576 }
2577
2578 chip->card = card;
2579 chip->pci = pci;
2580 chip->irq = -1;
Takashi Iwai30bdee02011-06-14 13:57:02 +02002581 INIT_WORK(&chip->hwvol_work, snd_m3_update_hw_volume);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002582
Linus Torvalds1da177e2005-04-16 15:20:36 -07002583 chip->external_amp = enable_amp;
2584 if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2585 chip->amp_gpio = amp_gpio;
Takashi Iwai1061eeb2006-11-24 15:36:46 +01002586 else {
2587 quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list);
2588 if (quirk) {
2589 snd_printdd(KERN_INFO "maestro3: set amp-gpio "
2590 "for '%s'\n", quirk->name);
2591 chip->amp_gpio = quirk->value;
2592 } else if (chip->allegro_flag)
2593 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2594 else /* presumably this is for all 'maestro3's.. */
2595 chip->amp_gpio = GPO_EXT_AMP_M3;
2596 }
2597
2598 quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list);
2599 if (quirk) {
2600 snd_printdd(KERN_INFO "maestro3: enabled irda workaround "
2601 "for '%s'\n", quirk->name);
2602 chip->irda_workaround = 1;
2603 }
2604 quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list);
2605 if (quirk)
2606 chip->hv_config = quirk->value;
2607 if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list))
2608 chip->is_omnibook = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002609
2610 chip->num_substreams = NR_DSPS;
Takashi Iwai3470c292005-11-17 15:05:09 +01002611 chip->substreams = kcalloc(chip->num_substreams, sizeof(struct m3_dma),
2612 GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002613 if (chip->substreams == NULL) {
2614 kfree(chip);
2615 pci_disable_device(pci);
2616 return -ENOMEM;
2617 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002618
Clemens Ladisch81d77242006-11-06 09:26:41 +01002619 err = request_firmware(&chip->assp_kernel_image,
2620 "ess/maestro3_assp_kernel.fw", &pci->dev);
2621 if (err < 0) {
Clemens Ladisch81d77242006-11-06 09:26:41 +01002622 snd_m3_free(chip);
2623 return err;
David Woodhousefa6e1cb2008-05-29 11:58:27 +03002624 }
Clemens Ladisch81d77242006-11-06 09:26:41 +01002625
2626 err = request_firmware(&chip->assp_minisrc_image,
2627 "ess/maestro3_assp_minisrc.fw", &pci->dev);
2628 if (err < 0) {
Clemens Ladisch81d77242006-11-06 09:26:41 +01002629 snd_m3_free(chip);
2630 return err;
David Woodhousefa6e1cb2008-05-29 11:58:27 +03002631 }
Clemens Ladisch81d77242006-11-06 09:26:41 +01002632
Linus Torvalds1da177e2005-04-16 15:20:36 -07002633 if ((err = pci_request_regions(pci, card->driver)) < 0) {
2634 snd_m3_free(chip);
2635 return err;
2636 }
2637 chip->iobase = pci_resource_start(pci, 0);
2638
2639 /* just to be sure */
2640 pci_set_master(pci);
2641
2642 snd_m3_chip_init(chip);
2643 snd_m3_assp_halt(chip);
2644
2645 snd_m3_ac97_reset(chip);
2646
Linus Torvalds1da177e2005-04-16 15:20:36 -07002647 snd_m3_amp_enable(chip, 1);
2648
Ville Syrjälä8b83afe2008-06-03 20:52:10 +03002649 snd_m3_hv_init(chip);
2650
Takashi Iwai437a5a42006-11-21 12:14:23 +01002651 if (request_irq(pci->irq, snd_m3_interrupt, IRQF_SHARED,
Takashi Iwai934c2b62011-06-10 16:36:37 +02002652 KBUILD_MODNAME, chip)) {
Takashi Iwai99b359b2005-10-20 18:26:44 +02002653 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002654 snd_m3_free(chip);
2655 return -ENOMEM;
2656 }
2657 chip->irq = pci->irq;
2658
2659#ifdef CONFIG_PM
2660 chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2661 if (chip->suspend_mem == NULL)
2662 snd_printk(KERN_WARNING "can't allocate apm buffer\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002663#endif
2664
2665 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2666 snd_m3_free(chip);
2667 return err;
2668 }
2669
2670 if ((err = snd_m3_mixer(chip)) < 0)
2671 return err;
2672
2673 for (i = 0; i < chip->num_substreams; i++) {
Takashi Iwai3470c292005-11-17 15:05:09 +01002674 struct m3_dma *s = &chip->substreams[i];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002675 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2676 return err;
2677 }
2678
2679 if ((err = snd_m3_pcm(chip, 0)) < 0)
2680 return err;
Hans de Goedeeb581ad2010-04-23 05:26:42 -04002681
2682#ifdef CONFIG_SND_MAESTRO3_INPUT
2683 if (chip->hv_config & HV_CTRL_ENABLE) {
2684 err = snd_m3_input_register(chip);
2685 if (err)
2686 snd_printk(KERN_WARNING "Input device registration "
2687 "failed with error %i", err);
2688 }
2689#endif
2690
Linus Torvalds1da177e2005-04-16 15:20:36 -07002691 snd_m3_enable_ints(chip);
2692 snd_m3_assp_continue(chip);
2693
2694 snd_card_set_dev(card, &pci->dev);
2695
2696 *chip_ret = chip;
2697
2698 return 0;
2699}
2700
2701/*
2702 */
2703static int __devinit
2704snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2705{
2706 static int dev;
Takashi Iwai3470c292005-11-17 15:05:09 +01002707 struct snd_card *card;
2708 struct snd_m3 *chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002709 int err;
2710
2711 /* don't pick up modems */
2712 if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2713 return -ENODEV;
2714
2715 if (dev >= SNDRV_CARDS)
2716 return -ENODEV;
2717 if (!enable[dev]) {
2718 dev++;
2719 return -ENOENT;
2720 }
2721
Takashi Iwaie58de7b2008-12-28 16:44:30 +01002722 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2723 if (err < 0)
2724 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002725
2726 switch (pci->device) {
2727 case PCI_DEVICE_ID_ESS_ALLEGRO:
2728 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2729 strcpy(card->driver, "Allegro");
2730 break;
2731 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2732 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2733 strcpy(card->driver, "Canyon3D-2");
2734 break;
2735 default:
2736 strcpy(card->driver, "Maestro3");
2737 break;
2738 }
2739
2740 if ((err = snd_m3_create(card, pci,
2741 external_amp[dev],
2742 amp_gpio[dev],
2743 &chip)) < 0) {
2744 snd_card_free(card);
2745 return err;
2746 }
Takashi Iwai0e2364a2005-11-17 16:10:19 +01002747 card->private_data = chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002748
2749 sprintf(card->shortname, "ESS %s PCI", card->driver);
2750 sprintf(card->longname, "%s at 0x%lx, irq %d",
2751 card->shortname, chip->iobase, chip->irq);
2752
2753 if ((err = snd_card_register(card)) < 0) {
2754 snd_card_free(card);
2755 return err;
2756 }
2757
2758#if 0 /* TODO: not supported yet */
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02002759 /* TODO enable MIDI IRQ and I/O */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002760 err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
Takashi Iwai302e4c22006-05-23 13:24:30 +02002761 chip->iobase + MPU401_DATA_PORT,
Clemens Ladischdba8b462011-09-13 11:24:41 +02002762 MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
2763 -1, &chip->rmidi);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002764 if (err < 0)
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02002765 printk(KERN_WARNING "maestro3: no MIDI support.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002766#endif
2767
2768 pci_set_drvdata(pci, card);
2769 dev++;
2770 return 0;
2771}
2772
2773static void __devexit snd_m3_remove(struct pci_dev *pci)
2774{
2775 snd_card_free(pci_get_drvdata(pci));
2776 pci_set_drvdata(pci, NULL);
2777}
2778
Takashi Iwaie9f66d92012-04-24 12:25:00 +02002779static struct pci_driver m3_driver = {
Takashi Iwai3733e422011-06-10 16:20:20 +02002780 .name = KBUILD_MODNAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002781 .id_table = snd_m3_ids,
2782 .probe = snd_m3_probe,
2783 .remove = __devexit_p(snd_m3_remove),
Takashi Iwai68cb2b52012-07-02 15:20:37 +02002784 .driver = {
2785 .pm = M3_PM_OPS,
2786 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002787};
2788
Takashi Iwaie9f66d92012-04-24 12:25:00 +02002789module_pci_driver(m3_driver);