blob: d09ad2254b577f19089608d308a3e1bb3ab94d8d [file] [log] [blame]
Vladimir Barinov7d831bf2007-06-12 18:09:50 +04001/*
2 * drivers/char/watchdog/davinci_wdt.c
3 *
4 * Watchdog driver for DaVinci DM644x/DM646x processors
5 *
Ivan Khoronzhukf48f3ce2013-12-05 13:26:24 +02006 * Copyright (C) 2006-2013 Texas Instruments.
Vladimir Barinov7d831bf2007-06-12 18:09:50 +04007 *
8 * 2007 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/types.h>
17#include <linux/kernel.h>
Vladimir Barinov7d831bf2007-06-12 18:09:50 +040018#include <linux/watchdog.h>
Vladimir Barinov7d831bf2007-06-12 18:09:50 +040019#include <linux/platform_device.h>
Alan Coxf78b0a82008-05-19 14:05:30 +010020#include <linux/io.h>
Kevin Hilman371d3522009-01-29 14:14:30 -080021#include <linux/device.h>
Kevin Hilman9fd868f2009-02-10 20:30:37 -080022#include <linux/clk.h>
Sachin Kamat6330c702013-03-04 10:36:41 +053023#include <linux/err.h>
Vladimir Barinov7d831bf2007-06-12 18:09:50 +040024
25#define MODULE_NAME "DAVINCI-WDT: "
26
27#define DEFAULT_HEARTBEAT 60
28#define MAX_HEARTBEAT 600 /* really the max margin is 264/27MHz*/
29
30/* Timer register set definition */
31#define PID12 (0x0)
32#define EMUMGT (0x4)
33#define TIM12 (0x10)
34#define TIM34 (0x14)
35#define PRD12 (0x18)
36#define PRD34 (0x1C)
37#define TCR (0x20)
38#define TGCR (0x24)
39#define WDTCR (0x28)
40
41/* TCR bit definitions */
42#define ENAMODE12_DISABLED (0 << 6)
43#define ENAMODE12_ONESHOT (1 << 6)
44#define ENAMODE12_PERIODIC (2 << 6)
45
46/* TGCR bit definitions */
47#define TIM12RS_UNRESET (1 << 0)
48#define TIM34RS_UNRESET (1 << 1)
49#define TIMMODE_64BIT_WDOG (2 << 2)
50
51/* WDTCR bit definitions */
52#define WDEN (1 << 14)
53#define WDFLAG (1 << 15)
54#define WDKEY_SEQ0 (0xa5c6 << 16)
55#define WDKEY_SEQ1 (0xda7e << 16)
56
Ivan Khoronzhukf48f3ce2013-12-05 13:26:24 +020057static int heartbeat;
Ivan Khoronzhuk6d9a6cf2013-12-04 21:39:27 +020058
59/*
60 * struct to hold data for each WDT device
61 * @base - base io address of WD device
62 * @clk - source clock of WDT
63 * @wdd - hold watchdog device as is in WDT core
64 */
65struct davinci_wdt_device {
66 void __iomem *base;
67 struct clk *clk;
68 struct watchdog_device wdd;
69};
Vladimir Barinov7d831bf2007-06-12 18:09:50 +040070
Ivan Khoronzhukf48f3ce2013-12-05 13:26:24 +020071static int davinci_wdt_start(struct watchdog_device *wdd)
Vladimir Barinov7d831bf2007-06-12 18:09:50 +040072{
73 u32 tgcr;
74 u32 timer_margin;
Kevin Hilman9fd868f2009-02-10 20:30:37 -080075 unsigned long wdt_freq;
Ivan Khoronzhuk6d9a6cf2013-12-04 21:39:27 +020076 struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
Kevin Hilman9fd868f2009-02-10 20:30:37 -080077
Ivan Khoronzhuk6d9a6cf2013-12-04 21:39:27 +020078 wdt_freq = clk_get_rate(davinci_wdt->clk);
Vladimir Barinov7d831bf2007-06-12 18:09:50 +040079
Vladimir Barinov7d831bf2007-06-12 18:09:50 +040080 /* disable, internal clock source */
Ivan Khoronzhuk6d9a6cf2013-12-04 21:39:27 +020081 iowrite32(0, davinci_wdt->base + TCR);
Vladimir Barinov7d831bf2007-06-12 18:09:50 +040082 /* reset timer, set mode to 64-bit watchdog, and unreset */
Ivan Khoronzhuk6d9a6cf2013-12-04 21:39:27 +020083 iowrite32(0, davinci_wdt->base + TGCR);
Vladimir Barinov7d831bf2007-06-12 18:09:50 +040084 tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
Ivan Khoronzhuk6d9a6cf2013-12-04 21:39:27 +020085 iowrite32(tgcr, davinci_wdt->base + TGCR);
Vladimir Barinov7d831bf2007-06-12 18:09:50 +040086 /* clear counter regs */
Ivan Khoronzhuk6d9a6cf2013-12-04 21:39:27 +020087 iowrite32(0, davinci_wdt->base + TIM12);
88 iowrite32(0, davinci_wdt->base + TIM34);
Vladimir Barinov7d831bf2007-06-12 18:09:50 +040089 /* set timeout period */
Ivan Khoronzhukf48f3ce2013-12-05 13:26:24 +020090 timer_margin = (((u64)wdd->timeout * wdt_freq) & 0xffffffff);
Ivan Khoronzhuk6d9a6cf2013-12-04 21:39:27 +020091 iowrite32(timer_margin, davinci_wdt->base + PRD12);
Ivan Khoronzhukf48f3ce2013-12-05 13:26:24 +020092 timer_margin = (((u64)wdd->timeout * wdt_freq) >> 32);
Ivan Khoronzhuk6d9a6cf2013-12-04 21:39:27 +020093 iowrite32(timer_margin, davinci_wdt->base + PRD34);
Vladimir Barinov7d831bf2007-06-12 18:09:50 +040094 /* enable run continuously */
Ivan Khoronzhuk6d9a6cf2013-12-04 21:39:27 +020095 iowrite32(ENAMODE12_PERIODIC, davinci_wdt->base + TCR);
Vladimir Barinov7d831bf2007-06-12 18:09:50 +040096 /* Once the WDT is in pre-active state write to
97 * TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are
98 * write protected (except for the WDKEY field)
99 */
100 /* put watchdog in pre-active state */
Ivan Khoronzhuk6d9a6cf2013-12-04 21:39:27 +0200101 iowrite32(WDKEY_SEQ0 | WDEN, davinci_wdt->base + WDTCR);
Vladimir Barinov7d831bf2007-06-12 18:09:50 +0400102 /* put watchdog in active state */
Ivan Khoronzhuk6d9a6cf2013-12-04 21:39:27 +0200103 iowrite32(WDKEY_SEQ1 | WDEN, davinci_wdt->base + WDTCR);
Ivan Khoronzhukf48f3ce2013-12-05 13:26:24 +0200104 return 0;
Vladimir Barinov7d831bf2007-06-12 18:09:50 +0400105}
106
Ivan Khoronzhukf48f3ce2013-12-05 13:26:24 +0200107static int davinci_wdt_ping(struct watchdog_device *wdd)
Vladimir Barinov7d831bf2007-06-12 18:09:50 +0400108{
Ivan Khoronzhuk6d9a6cf2013-12-04 21:39:27 +0200109 struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
110
Ivan Khoronzhukf48f3ce2013-12-05 13:26:24 +0200111 /* put watchdog in service state */
Ivan Khoronzhuk6d9a6cf2013-12-04 21:39:27 +0200112 iowrite32(WDKEY_SEQ0, davinci_wdt->base + WDTCR);
Ivan Khoronzhukf48f3ce2013-12-05 13:26:24 +0200113 /* put watchdog in active state */
Ivan Khoronzhuk6d9a6cf2013-12-04 21:39:27 +0200114 iowrite32(WDKEY_SEQ1, davinci_wdt->base + WDTCR);
Ivan Khoronzhukf48f3ce2013-12-05 13:26:24 +0200115 return 0;
Vladimir Barinov7d831bf2007-06-12 18:09:50 +0400116}
117
Ivan Khoronzhuka7719942013-12-04 21:39:28 +0200118static unsigned int davinci_wdt_get_timeleft(struct watchdog_device *wdd)
119{
120 u64 timer_counter;
121 unsigned long freq;
122 u32 val;
123 struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
124
125 /* if timeout has occured then return 0 */
126 val = ioread32(davinci_wdt->base + WDTCR);
127 if (val & WDFLAG)
128 return 0;
129
130 freq = clk_get_rate(davinci_wdt->clk);
131
132 if (!freq)
133 return 0;
134
135 timer_counter = ioread32(davinci_wdt->base + TIM12);
136 timer_counter |= ((u64)ioread32(davinci_wdt->base + TIM34) << 32);
137
138 do_div(timer_counter, freq);
139
140 return wdd->timeout - timer_counter;
141}
142
Ivan Khoronzhukf48f3ce2013-12-05 13:26:24 +0200143static const struct watchdog_info davinci_wdt_info = {
Wim Van Sebroeckf1a08cc2007-07-20 21:47:55 +0000144 .options = WDIOF_KEEPALIVEPING,
Ivan Khoronzhuk8832b202013-12-04 21:39:30 +0200145 .identity = "DaVinci/Keystone Watchdog",
Vladimir Barinov7d831bf2007-06-12 18:09:50 +0400146};
147
Ivan Khoronzhukf48f3ce2013-12-05 13:26:24 +0200148static const struct watchdog_ops davinci_wdt_ops = {
149 .owner = THIS_MODULE,
150 .start = davinci_wdt_start,
151 .stop = davinci_wdt_ping,
152 .ping = davinci_wdt_ping,
Ivan Khoronzhuka7719942013-12-04 21:39:28 +0200153 .get_timeleft = davinci_wdt_get_timeleft,
Vladimir Barinov7d831bf2007-06-12 18:09:50 +0400154};
155
Bill Pemberton2d991a12012-11-19 13:21:41 -0500156static int davinci_wdt_probe(struct platform_device *pdev)
Vladimir Barinov7d831bf2007-06-12 18:09:50 +0400157{
Kumar, Anile20880e2013-02-08 13:09:30 +0530158 int ret = 0;
Kevin Hilman371d3522009-01-29 14:14:30 -0800159 struct device *dev = &pdev->dev;
Kumar, Anile20880e2013-02-08 13:09:30 +0530160 struct resource *wdt_mem;
Ivan Khoronzhukf48f3ce2013-12-05 13:26:24 +0200161 struct watchdog_device *wdd;
Ivan Khoronzhuk6d9a6cf2013-12-04 21:39:27 +0200162 struct davinci_wdt_device *davinci_wdt;
Vladimir Barinov7d831bf2007-06-12 18:09:50 +0400163
Ivan Khoronzhuk6d9a6cf2013-12-04 21:39:27 +0200164 davinci_wdt = devm_kzalloc(dev, sizeof(*davinci_wdt), GFP_KERNEL);
165 if (!davinci_wdt)
166 return -ENOMEM;
Kevin Hilman9fd868f2009-02-10 20:30:37 -0800167
Ivan Khoronzhuk6d9a6cf2013-12-04 21:39:27 +0200168 davinci_wdt->clk = devm_clk_get(dev, NULL);
169 if (WARN_ON(IS_ERR(davinci_wdt->clk)))
170 return PTR_ERR(davinci_wdt->clk);
Kevin Hilman9fd868f2009-02-10 20:30:37 -0800171
Ivan Khoronzhuk6d9a6cf2013-12-04 21:39:27 +0200172 clk_prepare_enable(davinci_wdt->clk);
173
174 platform_set_drvdata(pdev, davinci_wdt);
175
176 wdd = &davinci_wdt->wdd;
Ivan Khoronzhukf48f3ce2013-12-05 13:26:24 +0200177 wdd->info = &davinci_wdt_info;
178 wdd->ops = &davinci_wdt_ops;
179 wdd->min_timeout = 1;
180 wdd->max_timeout = MAX_HEARTBEAT;
181 wdd->timeout = DEFAULT_HEARTBEAT;
Vladimir Barinov7d831bf2007-06-12 18:09:50 +0400182
Ivan Khoronzhukf48f3ce2013-12-05 13:26:24 +0200183 watchdog_init_timeout(wdd, heartbeat, dev);
184
185 dev_info(dev, "heartbeat %d sec\n", wdd->timeout);
186
Ivan Khoronzhuk6d9a6cf2013-12-04 21:39:27 +0200187 watchdog_set_drvdata(wdd, davinci_wdt);
Ivan Khoronzhukf48f3ce2013-12-05 13:26:24 +0200188 watchdog_set_nowayout(wdd, 1);
Vladimir Barinov7d831bf2007-06-12 18:09:50 +0400189
Julia Lawallf712eac2011-02-26 17:34:39 +0100190 wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Ivan Khoronzhuk6d9a6cf2013-12-04 21:39:27 +0200191 davinci_wdt->base = devm_ioremap_resource(dev, wdt_mem);
192 if (IS_ERR(davinci_wdt->base))
193 return PTR_ERR(davinci_wdt->base);
Vladimir Barinov7d831bf2007-06-12 18:09:50 +0400194
Ivan Khoronzhukf48f3ce2013-12-05 13:26:24 +0200195 ret = watchdog_register_device(wdd);
196 if (ret < 0)
197 dev_err(dev, "cannot register watchdog device\n");
Vladimir Barinov7d831bf2007-06-12 18:09:50 +0400198
199 return ret;
200}
201
Bill Pemberton4b12b892012-11-19 13:26:24 -0500202static int davinci_wdt_remove(struct platform_device *pdev)
Vladimir Barinov7d831bf2007-06-12 18:09:50 +0400203{
Ivan Khoronzhuk6d9a6cf2013-12-04 21:39:27 +0200204 struct davinci_wdt_device *davinci_wdt = platform_get_drvdata(pdev);
205
206 watchdog_unregister_device(&davinci_wdt->wdd);
207 clk_disable_unprepare(davinci_wdt->clk);
Kevin Hilman9fd868f2009-02-10 20:30:37 -0800208
Vladimir Barinov7d831bf2007-06-12 18:09:50 +0400209 return 0;
210}
211
Murali Karicheri902e2e72012-11-26 16:41:35 -0500212static const struct of_device_id davinci_wdt_of_match[] = {
213 { .compatible = "ti,davinci-wdt", },
214 {},
215};
216MODULE_DEVICE_TABLE(of, davinci_wdt_of_match);
217
Vladimir Barinov7d831bf2007-06-12 18:09:50 +0400218static struct platform_driver platform_wdt_driver = {
219 .driver = {
Ivan Khoronzhuk84374812013-11-27 15:31:53 +0200220 .name = "davinci-wdt",
Kay Sieversf37d1932008-04-10 21:29:23 -0700221 .owner = THIS_MODULE,
Murali Karicheri902e2e72012-11-26 16:41:35 -0500222 .of_match_table = davinci_wdt_of_match,
Vladimir Barinov7d831bf2007-06-12 18:09:50 +0400223 },
224 .probe = davinci_wdt_probe,
Bill Pemberton82268712012-11-19 13:21:12 -0500225 .remove = davinci_wdt_remove,
Vladimir Barinov7d831bf2007-06-12 18:09:50 +0400226};
227
Axel Linb8ec6112011-11-29 13:56:27 +0800228module_platform_driver(platform_wdt_driver);
Vladimir Barinov7d831bf2007-06-12 18:09:50 +0400229
230MODULE_AUTHOR("Texas Instruments");
231MODULE_DESCRIPTION("DaVinci Watchdog Driver");
232
233module_param(heartbeat, int, 0);
234MODULE_PARM_DESC(heartbeat,
235 "Watchdog heartbeat period in seconds from 1 to "
236 __MODULE_STRING(MAX_HEARTBEAT) ", default "
237 __MODULE_STRING(DEFAULT_HEARTBEAT));
238
239MODULE_LICENSE("GPL");
Ivan Khoronzhuk84374812013-11-27 15:31:53 +0200240MODULE_ALIAS("platform:davinci-wdt");