blob: 8d8473278d91c37e1bf5b742bbe20f8938a9ed9a [file] [log] [blame]
Benjamin Herrenschmidt57e2a992009-07-28 11:59:34 +10001#ifndef _ASM_POWERPC_PTE_BOOK3E_H
2#define _ASM_POWERPC_PTE_BOOK3E_H
3#ifdef __KERNEL__
4
5/* PTE bit definitions for processors compliant to the Book3E
6 * architecture 2.06 or later. The position of the PTE bits
7 * matches the HW definition of the optional Embedded Page Table
8 * category.
9 */
10
11/* Architected bits */
12#define _PAGE_PRESENT 0x000001 /* software: pte contains a translation */
Benjamin Herrenschmidt57e2a992009-07-28 11:59:34 +100013#define _PAGE_SW1 0x000002
Aneesh Kumar K.Ve1483152015-06-17 08:13:41 +053014#define _PAGE_BIT_SWAP_TYPE 2
Benjamin Herrenschmidt57e2a992009-07-28 11:59:34 +100015#define _PAGE_BAP_SR 0x000004
16#define _PAGE_BAP_UR 0x000008
17#define _PAGE_BAP_SW 0x000010
18#define _PAGE_BAP_UW 0x000020
19#define _PAGE_BAP_SX 0x000040
20#define _PAGE_BAP_UX 0x000080
21#define _PAGE_PSIZE_MSK 0x000f00
22#define _PAGE_PSIZE_4K 0x000200
Kumar Gala1d5d9522009-09-01 15:43:54 +000023#define _PAGE_PSIZE_8K 0x000300
24#define _PAGE_PSIZE_16K 0x000400
25#define _PAGE_PSIZE_32K 0x000500
Benjamin Herrenschmidt57e2a992009-07-28 11:59:34 +100026#define _PAGE_PSIZE_64K 0x000600
Kumar Gala1d5d9522009-09-01 15:43:54 +000027#define _PAGE_PSIZE_128K 0x000700
28#define _PAGE_PSIZE_256K 0x000800
29#define _PAGE_PSIZE_512K 0x000900
Benjamin Herrenschmidt57e2a992009-07-28 11:59:34 +100030#define _PAGE_PSIZE_1M 0x000a00
Kumar Gala1d5d9522009-09-01 15:43:54 +000031#define _PAGE_PSIZE_2M 0x000b00
32#define _PAGE_PSIZE_4M 0x000c00
33#define _PAGE_PSIZE_8M 0x000d00
Benjamin Herrenschmidt57e2a992009-07-28 11:59:34 +100034#define _PAGE_PSIZE_16M 0x000e00
Kumar Gala1d5d9522009-09-01 15:43:54 +000035#define _PAGE_PSIZE_32M 0x000f00
Benjamin Herrenschmidt57e2a992009-07-28 11:59:34 +100036#define _PAGE_DIRTY 0x001000 /* C: page changed */
37#define _PAGE_SW0 0x002000
38#define _PAGE_U3 0x004000
39#define _PAGE_U2 0x008000
40#define _PAGE_U1 0x010000
41#define _PAGE_U0 0x020000
42#define _PAGE_ACCESSED 0x040000
Bharat Bhushanc199efa2013-09-19 11:32:41 +053043#define _PAGE_ENDIAN 0x080000
Benjamin Herrenschmidt57e2a992009-07-28 11:59:34 +100044#define _PAGE_GUARDED 0x100000
45#define _PAGE_COHERENT 0x200000 /* M: enforce memory coherence */
46#define _PAGE_NO_CACHE 0x400000 /* I: cache inhibit */
47#define _PAGE_WRITETHRU 0x800000 /* W: cache write-through */
48
49/* "Higher level" linux bit combinations */
Benjamin Herrenschmidtea3cc332009-08-18 19:00:34 +000050#define _PAGE_EXEC _PAGE_BAP_UX /* .. and was cache cleaned */
51#define _PAGE_RW (_PAGE_BAP_SW | _PAGE_BAP_UW) /* User write permission */
52#define _PAGE_KERNEL_RW (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY)
53#define _PAGE_KERNEL_RO (_PAGE_BAP_SR)
54#define _PAGE_KERNEL_RWX (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY | _PAGE_BAP_SX)
55#define _PAGE_KERNEL_ROX (_PAGE_BAP_SR | _PAGE_BAP_SX)
56#define _PAGE_USER (_PAGE_BAP_UR | _PAGE_BAP_SR) /* Can be read */
Benjamin Herrenschmidt57e2a992009-07-28 11:59:34 +100057
58#define _PAGE_HASHPTE 0
59#define _PAGE_BUSY 0
60
61#define _PAGE_SPECIAL _PAGE_SW0
62
63/* Flags to be preserved on PTE modifications */
64#define _PAGE_HPTEFLAGS _PAGE_BUSY
65
66/* Base page size */
67#ifdef CONFIG_PPC_64K_PAGES
68#define _PAGE_PSIZE _PAGE_PSIZE_64K
69#define PTE_RPN_SHIFT (28)
70#else
71#define _PAGE_PSIZE _PAGE_PSIZE_4K
72#define PTE_RPN_SHIFT (24)
73#endif
74
Becky Bruce41151e72011-06-28 09:54:48 +000075#define PTE_WIMGE_SHIFT (19)
76#define PTE_BAP_SHIFT (2)
77
Benjamin Herrenschmidt57e2a992009-07-28 11:59:34 +100078/* On 32-bit, we never clear the top part of the PTE */
79#ifdef CONFIG_PPC32
80#define _PTE_NONE_MASK 0xffffffff00000000ULL
Kumar Gala76acc2c2009-09-01 15:48:42 +000081#define _PMD_PRESENT 0
82#define _PMD_PRESENT_MASK (PAGE_MASK)
83#define _PMD_BAD (~PAGE_MASK)
Benjamin Herrenschmidt57e2a992009-07-28 11:59:34 +100084#endif
85
86#endif /* __KERNEL__ */
87#endif /* _ASM_POWERPC_PTE_FSL_BOOKE_H */