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Mike Turquetteb24764902012-03-15 23:11:19 -07001/*
2 * linux/include/linux/clk-provider.h
3 *
4 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
5 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef __LINUX_CLK_PROVIDER_H
12#define __LINUX_CLK_PROVIDER_H
13
14#include <linux/clk.h>
Gerhard Sittigaa514ce2013-07-22 14:14:40 +020015#include <linux/io.h>
Mike Turquetteb24764902012-03-15 23:11:19 -070016
17#ifdef CONFIG_COMMON_CLK
18
Mike Turquetteb24764902012-03-15 23:11:19 -070019/*
20 * flags used across common struct clk. these flags should only affect the
21 * top-level framework. custom flags for dealing with hardware specifics
22 * belong in struct clk_foo
23 */
24#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
25#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
26#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
27#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
28#define CLK_IS_ROOT BIT(4) /* root clk, has no parent */
Rajendra Nayakf7d8caa2012-06-01 14:02:47 +053029#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
Ulf Hanssona093bde2012-08-31 14:21:28 +020030#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
James Hogan819c1de2013-07-29 12:25:01 +010031#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
Mike Turquetteb24764902012-03-15 23:11:19 -070032
Saravana Kannan0197b3e2012-04-25 22:58:56 -070033struct clk_hw;
34
Mike Turquetteb24764902012-03-15 23:11:19 -070035/**
36 * struct clk_ops - Callback operations for hardware clocks; these are to
37 * be provided by the clock implementation, and will be called by drivers
38 * through the clk_* api.
39 *
40 * @prepare: Prepare the clock for enabling. This must not return until
41 * the clock is fully prepared, and it's safe to call clk_enable.
42 * This callback is intended to allow clock implementations to
43 * do any initialisation that may sleep. Called with
44 * prepare_lock held.
45 *
46 * @unprepare: Release the clock from its prepared state. This will typically
47 * undo any work done in the @prepare callback. Called with
48 * prepare_lock held.
49 *
Ulf Hansson3d6ee282013-03-12 20:26:02 +010050 * @is_prepared: Queries the hardware to determine if the clock is prepared.
51 * This function is allowed to sleep. Optional, if this op is not
52 * set then the prepare count will be used.
53 *
Ulf Hansson3cc82472013-03-12 20:26:04 +010054 * @unprepare_unused: Unprepare the clock atomically. Only called from
55 * clk_disable_unused for prepare clocks with special needs.
56 * Called with prepare mutex held. This function may sleep.
57 *
Mike Turquetteb24764902012-03-15 23:11:19 -070058 * @enable: Enable the clock atomically. This must not return until the
59 * clock is generating a valid clock signal, usable by consumer
60 * devices. Called with enable_lock held. This function must not
61 * sleep.
62 *
63 * @disable: Disable the clock atomically. Called with enable_lock held.
64 * This function must not sleep.
65 *
Stephen Boyd119c7122012-10-03 23:38:53 -070066 * @is_enabled: Queries the hardware to determine if the clock is enabled.
67 * This function must not sleep. Optional, if this op is not
68 * set then the enable count will be used.
69 *
Mike Turquette7c045a52012-12-04 11:00:35 -080070 * @disable_unused: Disable the clock atomically. Only called from
71 * clk_disable_unused for gate clocks with special needs.
72 * Called with enable_lock held. This function must not
73 * sleep.
74 *
Stephen Boyd7ce3e8c2012-10-03 23:38:54 -070075 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
Mike Turquetteb24764902012-03-15 23:11:19 -070076 * parent rate is an input parameter. It is up to the caller to
Stephen Boyd7ce3e8c2012-10-03 23:38:54 -070077 * ensure that the prepare_mutex is held across this call.
Mike Turquetteb24764902012-03-15 23:11:19 -070078 * Returns the calculated rate. Optional, but recommended - if
79 * this op is not set then clock rate will be initialized to 0.
80 *
81 * @round_rate: Given a target rate as input, returns the closest rate actually
82 * supported by the clock.
83 *
James Hogan71472c02013-07-29 12:25:00 +010084 * @determine_rate: Given a target rate as input, returns the closest rate
85 * actually supported by the clock, and optionally the parent clock
86 * that should be used to provide the clock rate.
87 *
Mike Turquetteb24764902012-03-15 23:11:19 -070088 * @get_parent: Queries the hardware to determine the parent of a clock. The
89 * return value is a u8 which specifies the index corresponding to
90 * the parent clock. This index can be applied to either the
91 * .parent_names or .parents arrays. In short, this function
92 * translates the parent value read from hardware into an array
93 * index. Currently only called when the clock is initialized by
94 * __clk_init. This callback is mandatory for clocks with
95 * multiple parents. It is optional (and unnecessary) for clocks
96 * with 0 or 1 parents.
97 *
98 * @set_parent: Change the input source of this clock; for clocks with multiple
99 * possible parents specify a new parent by passing in the index
100 * as a u8 corresponding to the parent in either the .parent_names
101 * or .parents arrays. This function in affect translates an
102 * array index into the value programmed into the hardware.
103 * Returns 0 on success, -EERROR otherwise.
104 *
Shawn Guo1c0035d2012-04-12 20:50:18 +0800105 * @set_rate: Change the rate of this clock. The requested rate is specified
106 * by the second argument, which should typically be the return
107 * of .round_rate call. The third argument gives the parent rate
108 * which is likely helpful for most .set_rate implementation.
109 * Returns 0 on success, -EERROR otherwise.
Mike Turquetteb24764902012-03-15 23:11:19 -0700110 *
111 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
112 * implementations to split any work between atomic (enable) and sleepable
113 * (prepare) contexts. If enabling a clock requires code that might sleep,
114 * this must be done in clk_prepare. Clock enable code that will never be
Stephen Boyd7ce3e8c2012-10-03 23:38:54 -0700115 * called in a sleepable context may be implemented in clk_enable.
Mike Turquetteb24764902012-03-15 23:11:19 -0700116 *
117 * Typically, drivers will call clk_prepare when a clock may be needed later
118 * (eg. when a device is opened), and clk_enable when the clock is actually
119 * required (eg. from an interrupt). Note that clk_prepare MUST have been
120 * called before clk_enable.
121 */
122struct clk_ops {
123 int (*prepare)(struct clk_hw *hw);
124 void (*unprepare)(struct clk_hw *hw);
Ulf Hansson3d6ee282013-03-12 20:26:02 +0100125 int (*is_prepared)(struct clk_hw *hw);
Ulf Hansson3cc82472013-03-12 20:26:04 +0100126 void (*unprepare_unused)(struct clk_hw *hw);
Mike Turquetteb24764902012-03-15 23:11:19 -0700127 int (*enable)(struct clk_hw *hw);
128 void (*disable)(struct clk_hw *hw);
129 int (*is_enabled)(struct clk_hw *hw);
Mike Turquette7c045a52012-12-04 11:00:35 -0800130 void (*disable_unused)(struct clk_hw *hw);
Mike Turquetteb24764902012-03-15 23:11:19 -0700131 unsigned long (*recalc_rate)(struct clk_hw *hw,
132 unsigned long parent_rate);
133 long (*round_rate)(struct clk_hw *hw, unsigned long,
134 unsigned long *);
James Hogan71472c02013-07-29 12:25:00 +0100135 long (*determine_rate)(struct clk_hw *hw, unsigned long rate,
136 unsigned long *best_parent_rate,
137 struct clk **best_parent_clk);
Mike Turquetteb24764902012-03-15 23:11:19 -0700138 int (*set_parent)(struct clk_hw *hw, u8 index);
139 u8 (*get_parent)(struct clk_hw *hw);
Shawn Guo1c0035d2012-04-12 20:50:18 +0800140 int (*set_rate)(struct clk_hw *hw, unsigned long,
141 unsigned long);
Mike Turquetteb24764902012-03-15 23:11:19 -0700142 void (*init)(struct clk_hw *hw);
143};
144
Saravana Kannan0197b3e2012-04-25 22:58:56 -0700145/**
146 * struct clk_init_data - holds init data that's common to all clocks and is
147 * shared between the clock provider and the common clock framework.
148 *
149 * @name: clock name
150 * @ops: operations this clock supports
151 * @parent_names: array of string names for all possible parents
152 * @num_parents: number of possible parents
153 * @flags: framework-level hints and quirks
154 */
155struct clk_init_data {
156 const char *name;
157 const struct clk_ops *ops;
158 const char **parent_names;
159 u8 num_parents;
160 unsigned long flags;
161};
162
163/**
164 * struct clk_hw - handle for traversing from a struct clk to its corresponding
165 * hardware-specific structure. struct clk_hw should be declared within struct
166 * clk_foo and then referenced by the struct clk instance that uses struct
167 * clk_foo's clk_ops
168 *
169 * @clk: pointer to the struct clk instance that points back to this struct
170 * clk_hw instance
171 *
172 * @init: pointer to struct clk_init_data that contains the init data shared
173 * with the common clock framework.
174 */
175struct clk_hw {
176 struct clk *clk;
Mark Browndc4cd942012-05-14 15:12:42 +0100177 const struct clk_init_data *init;
Saravana Kannan0197b3e2012-04-25 22:58:56 -0700178};
179
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700180/*
181 * DOC: Basic clock implementations common to many platforms
182 *
183 * Each basic clock hardware type is comprised of a structure describing the
184 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
185 * unique flags for that hardware type, a registration function and an
186 * alternative macro for static initialization
187 */
188
189/**
190 * struct clk_fixed_rate - fixed-rate clock
191 * @hw: handle between common and hardware-specific interfaces
192 * @fixed_rate: constant frequency of clock
193 */
194struct clk_fixed_rate {
195 struct clk_hw hw;
196 unsigned long fixed_rate;
197 u8 flags;
198};
199
Shawn Guobffad662012-03-27 15:23:23 +0800200extern const struct clk_ops clk_fixed_rate_ops;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700201struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
202 const char *parent_name, unsigned long flags,
203 unsigned long fixed_rate);
204
Grant Likely015ba402012-04-07 21:39:39 -0500205void of_fixed_clk_setup(struct device_node *np);
206
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700207/**
208 * struct clk_gate - gating clock
209 *
210 * @hw: handle between common and hardware-specific interfaces
211 * @reg: register controlling gate
212 * @bit_idx: single bit controlling gate
213 * @flags: hardware-specific flags
214 * @lock: register lock
215 *
216 * Clock which can gate its output. Implements .enable & .disable
217 *
218 * Flags:
Viresh Kumar1f73f312012-04-17 16:45:35 +0530219 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700220 * enable the clock. Setting this flag does the opposite: setting the bit
221 * disable the clock and clearing it enables the clock
Haojian Zhuang04577992013-06-08 22:47:19 +0800222 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
223 * of this register, and mask of gate bits are in higher 16-bit of this
224 * register. While setting the gate bits, higher 16-bit should also be
225 * updated to indicate changing gate bits.
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700226 */
227struct clk_gate {
228 struct clk_hw hw;
229 void __iomem *reg;
230 u8 bit_idx;
231 u8 flags;
232 spinlock_t *lock;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700233};
234
235#define CLK_GATE_SET_TO_DISABLE BIT(0)
Haojian Zhuang04577992013-06-08 22:47:19 +0800236#define CLK_GATE_HIWORD_MASK BIT(1)
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700237
Shawn Guobffad662012-03-27 15:23:23 +0800238extern const struct clk_ops clk_gate_ops;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700239struct clk *clk_register_gate(struct device *dev, const char *name,
240 const char *parent_name, unsigned long flags,
241 void __iomem *reg, u8 bit_idx,
242 u8 clk_gate_flags, spinlock_t *lock);
243
Rajendra Nayak357c3f02012-06-29 19:06:32 +0530244struct clk_div_table {
245 unsigned int val;
246 unsigned int div;
247};
248
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700249/**
250 * struct clk_divider - adjustable divider clock
251 *
252 * @hw: handle between common and hardware-specific interfaces
253 * @reg: register containing the divider
254 * @shift: shift to the divider bit field
255 * @width: width of the divider bit field
Rajendra Nayak357c3f02012-06-29 19:06:32 +0530256 * @table: array of value/divider pairs, last entry should have div = 0
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700257 * @lock: register lock
258 *
259 * Clock with an adjustable divider affecting its output frequency. Implements
260 * .recalc_rate, .set_rate and .round_rate
261 *
262 * Flags:
263 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
264 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
265 * the raw value read from the register, with the value of zero considered
Soren Brinkmann056b20532013-04-02 15:36:56 -0700266 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700267 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
268 * the hardware register
Soren Brinkmann056b20532013-04-02 15:36:56 -0700269 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
270 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
271 * Some hardware implementations gracefully handle this case and allow a
272 * zero divisor by not modifying their input clock
273 * (divide by one / bypass).
Haojian Zhuangd57dfe72013-06-08 22:47:18 +0800274 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
275 * of this register, and mask of divider bits are in higher 16-bit of this
276 * register. While setting the divider bits, higher 16-bit should also be
277 * updated to indicate changing divider bits.
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700278 */
279struct clk_divider {
280 struct clk_hw hw;
281 void __iomem *reg;
282 u8 shift;
283 u8 width;
284 u8 flags;
Rajendra Nayak357c3f02012-06-29 19:06:32 +0530285 const struct clk_div_table *table;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700286 spinlock_t *lock;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700287};
288
289#define CLK_DIVIDER_ONE_BASED BIT(0)
290#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
Soren Brinkmann056b20532013-04-02 15:36:56 -0700291#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
Haojian Zhuangd57dfe72013-06-08 22:47:18 +0800292#define CLK_DIVIDER_HIWORD_MASK BIT(3)
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700293
Shawn Guobffad662012-03-27 15:23:23 +0800294extern const struct clk_ops clk_divider_ops;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700295struct clk *clk_register_divider(struct device *dev, const char *name,
296 const char *parent_name, unsigned long flags,
297 void __iomem *reg, u8 shift, u8 width,
298 u8 clk_divider_flags, spinlock_t *lock);
Rajendra Nayak357c3f02012-06-29 19:06:32 +0530299struct clk *clk_register_divider_table(struct device *dev, const char *name,
300 const char *parent_name, unsigned long flags,
301 void __iomem *reg, u8 shift, u8 width,
302 u8 clk_divider_flags, const struct clk_div_table *table,
303 spinlock_t *lock);
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700304
305/**
306 * struct clk_mux - multiplexer clock
307 *
308 * @hw: handle between common and hardware-specific interfaces
309 * @reg: register controlling multiplexer
310 * @shift: shift to multiplexer bit field
311 * @width: width of mutliplexer bit field
James Hogan3566d402013-03-25 14:35:07 +0000312 * @flags: hardware-specific flags
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700313 * @lock: register lock
314 *
315 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
316 * and .recalc_rate
317 *
318 * Flags:
319 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
Viresh Kumar1f73f312012-04-17 16:45:35 +0530320 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
Haojian Zhuangba492e92013-06-08 22:47:17 +0800321 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
322 * register, and mask of mux bits are in higher 16-bit of this register.
323 * While setting the mux bits, higher 16-bit should also be updated to
324 * indicate changing mux bits.
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700325 */
326struct clk_mux {
327 struct clk_hw hw;
328 void __iomem *reg;
Peter De Schrijverce4f3312013-03-22 14:07:53 +0200329 u32 *table;
330 u32 mask;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700331 u8 shift;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700332 u8 flags;
333 spinlock_t *lock;
334};
335
336#define CLK_MUX_INDEX_ONE BIT(0)
337#define CLK_MUX_INDEX_BIT BIT(1)
Haojian Zhuangba492e92013-06-08 22:47:17 +0800338#define CLK_MUX_HIWORD_MASK BIT(2)
Tomasz Figac57acd12013-07-23 01:49:18 +0200339#define CLK_MUX_READ_ONLY BIT(3) /* mux setting cannot be changed */
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700340
Shawn Guobffad662012-03-27 15:23:23 +0800341extern const struct clk_ops clk_mux_ops;
Tomasz Figac57acd12013-07-23 01:49:18 +0200342extern const struct clk_ops clk_mux_ro_ops;
Peter De Schrijverce4f3312013-03-22 14:07:53 +0200343
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700344struct clk *clk_register_mux(struct device *dev, const char *name,
Mark Brownd305fb72012-03-21 20:01:20 +0000345 const char **parent_names, u8 num_parents, unsigned long flags,
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700346 void __iomem *reg, u8 shift, u8 width,
347 u8 clk_mux_flags, spinlock_t *lock);
Mike Turquetteb24764902012-03-15 23:11:19 -0700348
Peter De Schrijverce4f3312013-03-22 14:07:53 +0200349struct clk *clk_register_mux_table(struct device *dev, const char *name,
350 const char **parent_names, u8 num_parents, unsigned long flags,
351 void __iomem *reg, u8 shift, u32 mask,
352 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
353
Gregory CLEMENT79b16642013-04-12 13:57:44 +0200354void of_fixed_factor_clk_setup(struct device_node *node);
355
Mike Turquetteb24764902012-03-15 23:11:19 -0700356/**
Sascha Hauerf0948f52012-05-03 15:36:14 +0530357 * struct clk_fixed_factor - fixed multiplier and divider clock
358 *
359 * @hw: handle between common and hardware-specific interfaces
360 * @mult: multiplier
361 * @div: divider
362 *
363 * Clock with a fixed multiplier and divider. The output frequency is the
364 * parent clock rate divided by div and multiplied by mult.
365 * Implements .recalc_rate, .set_rate and .round_rate
366 */
367
368struct clk_fixed_factor {
369 struct clk_hw hw;
370 unsigned int mult;
371 unsigned int div;
372};
373
374extern struct clk_ops clk_fixed_factor_ops;
375struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
376 const char *parent_name, unsigned long flags,
377 unsigned int mult, unsigned int div);
378
Prashant Gaikwadece70092013-03-20 17:30:34 +0530379/***
380 * struct clk_composite - aggregate clock of mux, divider and gate clocks
381 *
382 * @hw: handle between common and hardware-specific interfaces
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700383 * @mux_hw: handle between composite and hardware-specific mux clock
384 * @rate_hw: handle between composite and hardware-specific rate clock
385 * @gate_hw: handle between composite and hardware-specific gate clock
Prashant Gaikwadece70092013-03-20 17:30:34 +0530386 * @mux_ops: clock ops for mux
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700387 * @rate_ops: clock ops for rate
Prashant Gaikwadece70092013-03-20 17:30:34 +0530388 * @gate_ops: clock ops for gate
389 */
390struct clk_composite {
391 struct clk_hw hw;
392 struct clk_ops ops;
393
394 struct clk_hw *mux_hw;
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700395 struct clk_hw *rate_hw;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530396 struct clk_hw *gate_hw;
397
398 const struct clk_ops *mux_ops;
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700399 const struct clk_ops *rate_ops;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530400 const struct clk_ops *gate_ops;
401};
402
403struct clk *clk_register_composite(struct device *dev, const char *name,
404 const char **parent_names, int num_parents,
405 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700406 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
Prashant Gaikwadece70092013-03-20 17:30:34 +0530407 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
408 unsigned long flags);
409
Sascha Hauerf0948f52012-05-03 15:36:14 +0530410/**
Mike Turquetteb24764902012-03-15 23:11:19 -0700411 * clk_register - allocate a new clock, register it and return an opaque cookie
412 * @dev: device that is registering this clock
Mike Turquetteb24764902012-03-15 23:11:19 -0700413 * @hw: link to hardware-specific clock data
Mike Turquetteb24764902012-03-15 23:11:19 -0700414 *
415 * clk_register is the primary interface for populating the clock tree with new
416 * clock nodes. It returns a pointer to the newly allocated struct clk which
417 * cannot be dereferenced by driver code but may be used in conjuction with the
Mike Turquetted1302a32012-03-29 14:30:40 -0700418 * rest of the clock API. In the event of an error clk_register will return an
419 * error code; drivers must test for an error code after calling clk_register.
Mike Turquetteb24764902012-03-15 23:11:19 -0700420 */
Saravana Kannan0197b3e2012-04-25 22:58:56 -0700421struct clk *clk_register(struct device *dev, struct clk_hw *hw);
Stephen Boyd46c87732012-09-24 13:38:04 -0700422struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
Mike Turquetteb24764902012-03-15 23:11:19 -0700423
Mark Brown1df5c932012-04-18 09:07:12 +0100424void clk_unregister(struct clk *clk);
Stephen Boyd46c87732012-09-24 13:38:04 -0700425void devm_clk_unregister(struct device *dev, struct clk *clk);
Mark Brown1df5c932012-04-18 09:07:12 +0100426
Mike Turquetteb24764902012-03-15 23:11:19 -0700427/* helper functions */
428const char *__clk_get_name(struct clk *clk);
429struct clk_hw *__clk_get_hw(struct clk *clk);
430u8 __clk_get_num_parents(struct clk *clk);
431struct clk *__clk_get_parent(struct clk *clk);
James Hogan7ef3dcc2013-07-29 12:24:58 +0100432struct clk *clk_get_parent_by_index(struct clk *clk, u8 index);
Linus Torvalds93874682012-12-11 11:25:08 -0800433unsigned int __clk_get_enable_count(struct clk *clk);
434unsigned int __clk_get_prepare_count(struct clk *clk);
Mike Turquetteb24764902012-03-15 23:11:19 -0700435unsigned long __clk_get_rate(struct clk *clk);
436unsigned long __clk_get_flags(struct clk *clk);
Ulf Hansson3d6ee282013-03-12 20:26:02 +0100437bool __clk_is_prepared(struct clk *clk);
Stephen Boyd2ac6b1f2012-10-03 23:38:55 -0700438bool __clk_is_enabled(struct clk *clk);
Mike Turquetteb24764902012-03-15 23:11:19 -0700439struct clk *__clk_lookup(const char *name);
James Hogane366fdd2013-07-29 12:25:02 +0100440long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
441 unsigned long *best_parent_rate,
442 struct clk **best_parent_p);
Mike Turquetteb24764902012-03-15 23:11:19 -0700443
444/*
445 * FIXME clock api without lock protection
446 */
447int __clk_prepare(struct clk *clk);
448void __clk_unprepare(struct clk *clk);
449void __clk_reparent(struct clk *clk, struct clk *new_parent);
450unsigned long __clk_round_rate(struct clk *clk, unsigned long rate);
451
Grant Likely766e6a42012-04-09 14:50:06 -0500452struct of_device_id;
453
454typedef void (*of_clk_init_cb_t)(struct device_node *);
455
Sebastian Hesselbarth0b151de2013-05-01 02:58:28 +0200456struct clk_onecell_data {
457 struct clk **clks;
458 unsigned int clk_num;
459};
460
461#define CLK_OF_DECLARE(name, compat, fn) \
462 static const struct of_device_id __clk_of_table_##name \
463 __used __section(__clk_of_table) \
464 = { .compatible = compat, .data = fn };
465
466#ifdef CONFIG_OF
Grant Likely766e6a42012-04-09 14:50:06 -0500467int of_clk_add_provider(struct device_node *np,
468 struct clk *(*clk_src_get)(struct of_phandle_args *args,
469 void *data),
470 void *data);
471void of_clk_del_provider(struct device_node *np);
472struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
473 void *data);
Shawn Guo494bfec2012-08-22 21:36:27 +0800474struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
Mike Turquettef6102742013-10-07 23:12:13 -0700475int of_clk_get_parent_count(struct device_node *np);
Grant Likely766e6a42012-04-09 14:50:06 -0500476const char *of_clk_get_parent_name(struct device_node *np, int index);
Prashant Gaikwadf2f6c252013-01-04 12:30:52 +0530477
Grant Likely766e6a42012-04-09 14:50:06 -0500478void of_clk_init(const struct of_device_id *matches);
479
Sebastian Hesselbarth0b151de2013-05-01 02:58:28 +0200480#else /* !CONFIG_OF */
Prashant Gaikwadf2f6c252013-01-04 12:30:52 +0530481
Sebastian Hesselbarth0b151de2013-05-01 02:58:28 +0200482static inline int of_clk_add_provider(struct device_node *np,
483 struct clk *(*clk_src_get)(struct of_phandle_args *args,
484 void *data),
485 void *data)
486{
487 return 0;
488}
489#define of_clk_del_provider(np) \
490 { while (0); }
491static inline struct clk *of_clk_src_simple_get(
492 struct of_phandle_args *clkspec, void *data)
493{
494 return ERR_PTR(-ENOENT);
495}
496static inline struct clk *of_clk_src_onecell_get(
497 struct of_phandle_args *clkspec, void *data)
498{
499 return ERR_PTR(-ENOENT);
500}
501static inline const char *of_clk_get_parent_name(struct device_node *np,
502 int index)
503{
504 return NULL;
505}
506#define of_clk_init(matches) \
507 { while (0); }
508#endif /* CONFIG_OF */
Gerhard Sittigaa514ce2013-07-22 14:14:40 +0200509
510/*
511 * wrap access to peripherals in accessor routines
512 * for improved portability across platforms
513 */
514
515static inline u32 clk_readl(u32 __iomem *reg)
516{
517 return readl(reg);
518}
519
520static inline void clk_writel(u32 val, u32 __iomem *reg)
521{
522 writel(val, reg);
523}
524
Mike Turquetteb24764902012-03-15 23:11:19 -0700525#endif /* CONFIG_COMMON_CLK */
526#endif /* CLK_PROVIDER_H */