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Ingo Molnar06fcb0c2006-06-29 02:24:40 -07001#ifndef _LINUX_IRQ_H
2#define _LINUX_IRQ_H
Linus Torvalds1da177e2005-04-16 15:20:36 -07003
4/*
5 * Please do not include this file in generic code. There is currently
6 * no requirement for any architecture to implement anything held
7 * within this file.
8 *
9 * Thanks. --rmk
10 */
11
Adrian Bunk23f9b312005-12-21 02:27:50 +010012#include <linux/smp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070013#include <linux/linkage.h>
14#include <linux/cache.h>
15#include <linux/spinlock.h>
16#include <linux/cpumask.h>
Ralf Baechle503e5762009-03-29 12:59:50 +020017#include <linux/gfp.h>
Jan Beulich908dcec2006-06-23 02:06:00 -070018#include <linux/irqreturn.h>
Thomas Gleixnerdd3a1db2008-10-16 18:20:58 +020019#include <linux/irqnr.h>
David Howells77904fd2007-02-28 20:13:26 -080020#include <linux/errno.h>
Ralf Baechle503e5762009-03-29 12:59:50 +020021#include <linux/topology.h>
Thomas Gleixner3aa551c2009-03-23 18:28:15 +010022#include <linux/wait.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070023
24#include <asm/irq.h>
25#include <asm/ptrace.h>
David Howells7d12e782006-10-05 14:55:46 +010026#include <asm/irq_regs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070027
Thomas Gleixnerab7798f2011-03-25 16:48:50 +010028struct seq_file;
Paul Gortmakerec53cf22011-09-19 20:33:19 -040029struct module;
David Howells57a58a92006-10-05 13:06:34 +010030struct irq_desc;
Thomas Gleixner78129572011-02-10 15:14:20 +010031struct irq_data;
Harvey Harrisonec701582008-02-08 04:19:55 -080032typedef void (*irq_flow_handler_t)(unsigned int irq,
David Howells7d12e782006-10-05 14:55:46 +010033 struct irq_desc *desc);
Thomas Gleixner78129572011-02-10 15:14:20 +010034typedef void (*irq_preflow_handler_t)(struct irq_data *data);
David Howells57a58a92006-10-05 13:06:34 +010035
Linus Torvalds1da177e2005-04-16 15:20:36 -070036/*
37 * IRQ line status.
Thomas Gleixner6e213612006-07-01 19:29:03 -070038 *
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010039 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
Thomas Gleixner6e213612006-07-01 19:29:03 -070040 *
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010041 * IRQ_TYPE_NONE - default, unspecified type
42 * IRQ_TYPE_EDGE_RISING - rising edge triggered
43 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
44 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
45 * IRQ_TYPE_LEVEL_HIGH - high level triggered
46 * IRQ_TYPE_LEVEL_LOW - low level triggered
47 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
48 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
Benjamin Herrenschmidt3fca40c2012-04-19 17:29:42 +000049 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
50 * to setup the HW to a sane default (used
51 * by irqdomain map() callbacks to synchronize
52 * the HW state and SW flags for a newly
53 * allocated descriptor).
54 *
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010055 * IRQ_TYPE_PROBE - Special flag for probing in progress
56 *
57 * Bits which can be modified via irq_set/clear/modify_status_flags()
58 * IRQ_LEVEL - Interrupt is level type. Will be also
59 * updated in the code when the above trigger
Geert Uytterhoeven0911f122011-04-10 11:01:51 +020060 * bits are modified via irq_set_irq_type()
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010061 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
62 * it from affinity setting
63 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
64 * IRQ_NOREQUEST - Interrupt cannot be requested via
65 * request_irq()
Paul Mundt7f1b1242011-04-07 06:01:44 +090066 * IRQ_NOTHREAD - Interrupt cannot be threaded
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010067 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
68 * request/setup_irq()
69 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
70 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
71 * IRQ_NESTED_TRHEAD - Interrupt nests into another thread
Marc Zyngier31d9d9b2011-09-23 17:03:06 +010072 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
Thomas Gleixnerb39898c2013-11-06 12:30:07 +010073 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
74 * it from the spurious interrupt detection
75 * mechanism and from core side polling.
Linus Torvalds1da177e2005-04-16 15:20:36 -070076 */
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010077enum {
78 IRQ_TYPE_NONE = 0x00000000,
79 IRQ_TYPE_EDGE_RISING = 0x00000001,
80 IRQ_TYPE_EDGE_FALLING = 0x00000002,
81 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
82 IRQ_TYPE_LEVEL_HIGH = 0x00000004,
83 IRQ_TYPE_LEVEL_LOW = 0x00000008,
84 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
85 IRQ_TYPE_SENSE_MASK = 0x0000000f,
Benjamin Herrenschmidt3fca40c2012-04-19 17:29:42 +000086 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
Thomas Gleixner876dbd42011-02-08 17:28:12 +010087
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010088 IRQ_TYPE_PROBE = 0x00000010,
Thomas Gleixner6e213612006-07-01 19:29:03 -070089
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010090 IRQ_LEVEL = (1 << 8),
91 IRQ_PER_CPU = (1 << 9),
92 IRQ_NOPROBE = (1 << 10),
93 IRQ_NOREQUEST = (1 << 11),
94 IRQ_NOAUTOEN = (1 << 12),
95 IRQ_NO_BALANCING = (1 << 13),
96 IRQ_MOVE_PCNTXT = (1 << 14),
97 IRQ_NESTED_THREAD = (1 << 15),
Paul Mundt7f1b1242011-04-07 06:01:44 +090098 IRQ_NOTHREAD = (1 << 16),
Marc Zyngier31d9d9b2011-09-23 17:03:06 +010099 IRQ_PER_CPU_DEVID = (1 << 17),
Thomas Gleixnerb39898c2013-11-06 12:30:07 +0100100 IRQ_IS_POLLED = (1 << 18),
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +0100101};
Thomas Gleixner950f4422007-02-16 01:27:24 -0800102
Thomas Gleixner44247182010-09-28 10:40:18 +0200103#define IRQF_MODIFY_MASK \
104 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
Thomas Gleixner872434d2011-02-05 16:25:25 +0100105 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
Thomas Gleixnerb39898c2013-11-06 12:30:07 +0100106 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
107 IRQ_IS_POLLED)
Thomas Gleixner44247182010-09-28 10:40:18 +0200108
Thomas Gleixner8f53f922011-02-08 16:50:00 +0100109#define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
110
Thomas Gleixner3b8249e2011-02-07 16:02:20 +0100111/*
112 * Return value for chip->irq_set_affinity()
113 *
114 * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity
115 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity
116 */
117enum {
118 IRQ_SET_MASK_OK = 0,
119 IRQ_SET_MASK_OK_NOCOPY,
120};
121
Eric W. Biederman5b912c12007-01-28 12:52:03 -0700122struct msi_desc;
Grant Likely08a543a2011-07-26 03:19:06 -0600123struct irq_domain;
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700124
Ingo Molnar8fee5c32006-06-29 02:24:45 -0700125/**
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000126 * struct irq_data - per irq and irq chip data passed down to chip functions
Thomas Gleixner966dc732013-05-06 14:30:22 +0000127 * @mask: precomputed bitmask for accessing the chip registers
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000128 * @irq: interrupt number
Grant Likely08a543a2011-07-26 03:19:06 -0600129 * @hwirq: hardware interrupt number, local to the interrupt domain
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000130 * @node: node index useful for balancing
Randy Dunlap30398bf2011-03-18 09:33:56 -0700131 * @state_use_accessors: status information for irq chip functions.
Thomas Gleixner91c49912011-02-03 20:48:29 +0100132 * Use accessor functions to deal with it
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000133 * @chip: low level interrupt hardware access
Grant Likely08a543a2011-07-26 03:19:06 -0600134 * @domain: Interrupt translation domain; responsible for mapping
135 * between hwirq number and linux irq number.
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000136 * @handler_data: per-IRQ data for the irq_chip methods
137 * @chip_data: platform-specific per-chip private data for the chip
138 * methods, to allow shared chip implementations
139 * @msi_desc: MSI descriptor
140 * @affinity: IRQ affinity on SMP
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000141 *
142 * The fields here need to overlay the ones in irq_desc until we
143 * cleaned up the direct references and switched everything over to
144 * irq_data.
145 */
146struct irq_data {
Thomas Gleixner966dc732013-05-06 14:30:22 +0000147 u32 mask;
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000148 unsigned int irq;
Grant Likely08a543a2011-07-26 03:19:06 -0600149 unsigned long hwirq;
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000150 unsigned int node;
Thomas Gleixner91c49912011-02-03 20:48:29 +0100151 unsigned int state_use_accessors;
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000152 struct irq_chip *chip;
Grant Likely08a543a2011-07-26 03:19:06 -0600153 struct irq_domain *domain;
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000154 void *handler_data;
155 void *chip_data;
156 struct msi_desc *msi_desc;
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000157 cpumask_var_t affinity;
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000158};
159
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +0100160/*
161 * Bit masks for irq_data.state
162 *
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100163 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +0100164 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
Thomas Gleixnera0056772011-02-08 17:11:03 +0100165 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
166 * IRQD_PER_CPU - Interrupt is per cpu
Thomas Gleixner2bdd1052011-02-08 17:22:00 +0100167 * IRQD_AFFINITY_SET - Interrupt affinity was set
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100168 * IRQD_LEVEL - Interrupt is level triggered
Thomas Gleixner7f942262011-02-10 19:46:26 +0100169 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
170 * from suspend
Thomas Gleixnere1ef8242011-02-10 22:25:31 +0100171 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process
172 * context
Thomas Gleixner32f41252011-03-28 14:10:52 +0200173 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
174 * IRQD_IRQ_MASKED - Masked state of the interrupt
175 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +0100176 */
177enum {
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100178 IRQD_TRIGGER_MASK = 0xf,
Thomas Gleixnera0056772011-02-08 17:11:03 +0100179 IRQD_SETAFFINITY_PENDING = (1 << 8),
180 IRQD_NO_BALANCING = (1 << 10),
181 IRQD_PER_CPU = (1 << 11),
Thomas Gleixner2bdd1052011-02-08 17:22:00 +0100182 IRQD_AFFINITY_SET = (1 << 12),
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100183 IRQD_LEVEL = (1 << 13),
Thomas Gleixner7f942262011-02-10 19:46:26 +0100184 IRQD_WAKEUP_STATE = (1 << 14),
Thomas Gleixnere1ef8242011-02-10 22:25:31 +0100185 IRQD_MOVE_PCNTXT = (1 << 15),
Thomas Gleixner801a0e92011-03-27 11:02:49 +0200186 IRQD_IRQ_DISABLED = (1 << 16),
Thomas Gleixner32f41252011-03-28 14:10:52 +0200187 IRQD_IRQ_MASKED = (1 << 17),
188 IRQD_IRQ_INPROGRESS = (1 << 18),
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +0100189};
190
191static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
192{
193 return d->state_use_accessors & IRQD_SETAFFINITY_PENDING;
194}
195
Thomas Gleixnera0056772011-02-08 17:11:03 +0100196static inline bool irqd_is_per_cpu(struct irq_data *d)
197{
198 return d->state_use_accessors & IRQD_PER_CPU;
199}
200
201static inline bool irqd_can_balance(struct irq_data *d)
202{
203 return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING));
204}
205
Thomas Gleixner2bdd1052011-02-08 17:22:00 +0100206static inline bool irqd_affinity_was_set(struct irq_data *d)
207{
208 return d->state_use_accessors & IRQD_AFFINITY_SET;
209}
210
Thomas Gleixneree38c042011-03-28 17:11:13 +0200211static inline void irqd_mark_affinity_was_set(struct irq_data *d)
212{
213 d->state_use_accessors |= IRQD_AFFINITY_SET;
214}
215
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100216static inline u32 irqd_get_trigger_type(struct irq_data *d)
217{
218 return d->state_use_accessors & IRQD_TRIGGER_MASK;
219}
220
221/*
222 * Must only be called inside irq_chip.irq_set_type() functions.
223 */
224static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
225{
226 d->state_use_accessors &= ~IRQD_TRIGGER_MASK;
227 d->state_use_accessors |= type & IRQD_TRIGGER_MASK;
228}
229
230static inline bool irqd_is_level_type(struct irq_data *d)
231{
232 return d->state_use_accessors & IRQD_LEVEL;
233}
234
Thomas Gleixner7f942262011-02-10 19:46:26 +0100235static inline bool irqd_is_wakeup_set(struct irq_data *d)
236{
237 return d->state_use_accessors & IRQD_WAKEUP_STATE;
238}
239
Thomas Gleixnere1ef8242011-02-10 22:25:31 +0100240static inline bool irqd_can_move_in_process_context(struct irq_data *d)
241{
242 return d->state_use_accessors & IRQD_MOVE_PCNTXT;
243}
244
Thomas Gleixner801a0e92011-03-27 11:02:49 +0200245static inline bool irqd_irq_disabled(struct irq_data *d)
246{
247 return d->state_use_accessors & IRQD_IRQ_DISABLED;
248}
249
Thomas Gleixner32f41252011-03-28 14:10:52 +0200250static inline bool irqd_irq_masked(struct irq_data *d)
251{
252 return d->state_use_accessors & IRQD_IRQ_MASKED;
253}
254
255static inline bool irqd_irq_inprogress(struct irq_data *d)
256{
257 return d->state_use_accessors & IRQD_IRQ_INPROGRESS;
258}
259
Thomas Gleixner9cff60d2011-03-28 16:41:14 +0200260/*
261 * Functions for chained handlers which can be enabled/disabled by the
262 * standard disable_irq/enable_irq calls. Must be called with
263 * irq_desc->lock held.
264 */
265static inline void irqd_set_chained_irq_inprogress(struct irq_data *d)
266{
267 d->state_use_accessors |= IRQD_IRQ_INPROGRESS;
268}
269
270static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d)
271{
272 d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS;
273}
274
Grant Likelya699e4e2012-04-03 07:11:04 -0600275static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
276{
277 return d->hwirq;
278}
279
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000280/**
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700281 * struct irq_chip - hardware interrupt chip descriptor
Ingo Molnar8fee5c32006-06-29 02:24:45 -0700282 *
283 * @name: name for /proc/interrupts
Thomas Gleixnerf8822652010-09-27 12:44:32 +0000284 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
285 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
286 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
287 * @irq_disable: disable the interrupt
288 * @irq_ack: start of a new interrupt
289 * @irq_mask: mask an interrupt source
290 * @irq_mask_ack: ack and mask an interrupt source
291 * @irq_unmask: unmask an interrupt source
292 * @irq_eoi: end of interrupt
293 * @irq_set_affinity: set the CPU affinity on SMP machines
294 * @irq_retrigger: resend an IRQ to the CPU
295 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
296 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
297 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
298 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
David Daney0fdb4b22011-03-25 12:38:49 -0700299 * @irq_cpu_online: configure an interrupt source for a secondary CPU
300 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
Thomas Gleixnercfefd212011-04-15 22:36:08 +0200301 * @irq_suspend: function called from core code on suspend once per chip
302 * @irq_resume: function called from core code on resume once per chip
303 * @irq_pm_shutdown: function called from core code on shutdown once per chip
Thomas Gleixnerd0051812013-05-06 14:30:24 +0000304 * @irq_calc_mask: Optional function to set irq_data.mask for special cases
Thomas Gleixnerab7798f2011-03-25 16:48:50 +0100305 * @irq_print_chip: optional to print special chip info in show_interrupts
Thomas Gleixner2bff17a2011-02-10 13:08:38 +0100306 * @flags: chip specific flags
Linus Torvalds1da177e2005-04-16 15:20:36 -0700307 */
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700308struct irq_chip {
309 const char *name;
Thomas Gleixnerf8822652010-09-27 12:44:32 +0000310 unsigned int (*irq_startup)(struct irq_data *data);
311 void (*irq_shutdown)(struct irq_data *data);
312 void (*irq_enable)(struct irq_data *data);
313 void (*irq_disable)(struct irq_data *data);
314
315 void (*irq_ack)(struct irq_data *data);
316 void (*irq_mask)(struct irq_data *data);
317 void (*irq_mask_ack)(struct irq_data *data);
318 void (*irq_unmask)(struct irq_data *data);
319 void (*irq_eoi)(struct irq_data *data);
320
321 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
322 int (*irq_retrigger)(struct irq_data *data);
323 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
324 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
325
326 void (*irq_bus_lock)(struct irq_data *data);
327 void (*irq_bus_sync_unlock)(struct irq_data *data);
328
David Daney0fdb4b22011-03-25 12:38:49 -0700329 void (*irq_cpu_online)(struct irq_data *data);
330 void (*irq_cpu_offline)(struct irq_data *data);
331
Thomas Gleixnercfefd212011-04-15 22:36:08 +0200332 void (*irq_suspend)(struct irq_data *data);
333 void (*irq_resume)(struct irq_data *data);
334 void (*irq_pm_shutdown)(struct irq_data *data);
335
Thomas Gleixnerd0051812013-05-06 14:30:24 +0000336 void (*irq_calc_mask)(struct irq_data *data);
337
Thomas Gleixnerab7798f2011-03-25 16:48:50 +0100338 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
339
Thomas Gleixner2bff17a2011-02-10 13:08:38 +0100340 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700341};
342
Thomas Gleixnerd4d5e082011-02-10 13:16:14 +0100343/*
344 * irq_chip specific flags
345 *
Thomas Gleixner77694b42011-02-15 10:33:57 +0100346 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
347 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
Thomas Gleixnerd209a692011-03-11 21:22:14 +0100348 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
Thomas Gleixnerb3d42232011-03-27 16:05:36 +0200349 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
350 * when irq enabled
Santosh Shilimkar60f96b42011-09-09 13:59:35 +0530351 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
Thomas Gleixnerd4d5e082011-02-10 13:16:14 +0100352 */
353enum {
354 IRQCHIP_SET_TYPE_MASKED = (1 << 0),
Thomas Gleixner77694b42011-02-15 10:33:57 +0100355 IRQCHIP_EOI_IF_HANDLED = (1 << 1),
Thomas Gleixnerd209a692011-03-11 21:22:14 +0100356 IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
Thomas Gleixnerb3d42232011-03-27 16:05:36 +0200357 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
Santosh Shilimkar60f96b42011-09-09 13:59:35 +0530358 IRQCHIP_SKIP_SET_WAKE = (1 << 4),
Thomas Gleixnerdc9b2292012-07-13 19:29:45 +0200359 IRQCHIP_ONESHOT_SAFE = (1 << 5),
Thomas Gleixnerd4d5e082011-02-10 13:16:14 +0100360};
361
Thomas Gleixnere1447102010-10-01 16:03:45 +0200362/* This include will go away once we isolated irq_desc usage to core code */
363#include <linux/irqdesc.h>
Thomas Gleixnerc6b76742008-10-15 14:31:29 +0200364
Ingo Molnar34ffdb72006-06-29 02:24:40 -0700365/*
Ingo Molnar34ffdb72006-06-29 02:24:40 -0700366 * Pick up the arch-dependent methods:
367 */
368#include <asm/hw_irq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700369
Thomas Gleixnerb683de22010-09-27 20:55:03 +0200370#ifndef NR_IRQS_LEGACY
371# define NR_IRQS_LEGACY 0
372#endif
373
Thomas Gleixner1318a482010-09-27 21:01:37 +0200374#ifndef ARCH_IRQ_INIT_FLAGS
375# define ARCH_IRQ_INIT_FLAGS 0
376#endif
377
Thomas Gleixnerc1594b72011-02-07 22:11:30 +0100378#define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
Thomas Gleixner1318a482010-09-27 21:01:37 +0200379
Thomas Gleixnere1447102010-10-01 16:03:45 +0200380struct irqaction;
Ingo Molnar06fcb0c2006-06-29 02:24:40 -0700381extern int setup_irq(unsigned int irq, struct irqaction *new);
Magnus Dammcbf94f02009-03-12 21:05:51 +0900382extern void remove_irq(unsigned int irq, struct irqaction *act);
Marc Zyngier31d9d9b2011-09-23 17:03:06 +0100383extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
384extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700385
David Daney0fdb4b22011-03-25 12:38:49 -0700386extern void irq_cpu_online(void);
387extern void irq_cpu_offline(void);
David Daneyc2d0c552011-03-25 12:38:50 -0700388extern int __irq_set_affinity_locked(struct irq_data *data, const struct cpumask *cpumask);
David Daney0fdb4b22011-03-25 12:38:49 -0700389
Thomas Gleixner3a3856d02010-10-04 13:47:12 +0200390#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
Thomas Gleixnera4395202011-02-04 18:46:16 +0100391void irq_move_irq(struct irq_data *data);
392void irq_move_masked_irq(struct irq_data *data);
Thomas Gleixnere1447102010-10-01 16:03:45 +0200393#else
Thomas Gleixnera4395202011-02-04 18:46:16 +0100394static inline void irq_move_irq(struct irq_data *data) { }
395static inline void irq_move_masked_irq(struct irq_data *data) { }
Thomas Gleixnere1447102010-10-01 16:03:45 +0200396#endif
Ashok Raj54d5d422005-09-06 15:16:15 -0700397
Linus Torvalds1da177e2005-04-16 15:20:36 -0700398extern int no_irq_affinity;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700399
Thomas Gleixner293a7a02012-10-16 15:07:49 -0700400#ifdef CONFIG_HARDIRQS_SW_RESEND
401int irq_set_parent(int irq, int parent_irq);
402#else
403static inline int irq_set_parent(int irq, int parent_irq)
404{
405 return 0;
406}
407#endif
408
Ingo Molnar2e60bbb2006-06-29 02:24:39 -0700409/*
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700410 * Built-in IRQ handlers for various IRQ types,
Krzysztof Halasabebd04c2009-11-15 18:57:24 +0100411 * callable via desc->handle_irq()
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700412 */
Harvey Harrisonec701582008-02-08 04:19:55 -0800413extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
414extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
415extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
Thomas Gleixner0521c8f2011-03-28 16:13:24 +0200416extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc);
Harvey Harrisonec701582008-02-08 04:19:55 -0800417extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
418extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
Marc Zyngier31d9d9b2011-09-23 17:03:06 +0100419extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc);
Harvey Harrisonec701582008-02-08 04:19:55 -0800420extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);
Mark Brown31b47cf2009-08-24 20:28:04 +0100421extern void handle_nested_irq(unsigned int irq);
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700422
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700423/* Handling of unhandled and spurious interrupts: */
Ingo Molnar34ffdb72006-06-29 02:24:40 -0700424extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
Thomas Gleixnerbedd30d2008-09-30 23:14:27 +0200425 irqreturn_t action_ret);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700426
Thomas Gleixnera4633adc2006-06-29 02:24:48 -0700427
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700428/* Enable/disable irq debugging output: */
429extern int noirqdebug_setup(char *str);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700430
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700431/* Checks whether the interrupt can be requested by request_irq(): */
432extern int can_request_irq(unsigned int irq, unsigned long irqflags);
433
Thomas Gleixnerf8b54732006-07-01 22:30:08 +0100434/* Dummy irq-chip implementations: */
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700435extern struct irq_chip no_irq_chip;
Thomas Gleixnerf8b54732006-07-01 22:30:08 +0100436extern struct irq_chip dummy_irq_chip;
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700437
438extern void
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100439irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
Ingo Molnara460e742006-10-17 00:10:03 -0700440 irq_flow_handler_t handle, const char *name);
441
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100442static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
443 irq_flow_handler_t handle)
444{
445 irq_set_chip_and_handler_name(irq, chip, handle, NULL);
446}
447
Marc Zyngier31d9d9b2011-09-23 17:03:06 +0100448extern int irq_set_percpu_devid(unsigned int irq);
449
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700450extern void
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100451__irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
Ingo Molnara460e742006-10-17 00:10:03 -0700452 const char *name);
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700453
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700454static inline void
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100455irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700456{
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100457 __irq_set_handler(irq, handle, 0, NULL);
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700458}
459
460/*
461 * Set a highlevel chained flow handler for a given IRQ.
462 * (a chained handler is automatically enabled and set to
Paul Mundt7f1b1242011-04-07 06:01:44 +0900463 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700464 */
465static inline void
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100466irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700467{
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100468 __irq_set_handler(irq, handle, 1, NULL);
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700469}
470
Thomas Gleixner44247182010-09-28 10:40:18 +0200471void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
472
473static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
474{
475 irq_modify_status(irq, 0, set);
476}
477
478static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
479{
480 irq_modify_status(irq, clr, 0);
481}
482
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100483static inline void irq_set_noprobe(unsigned int irq)
Thomas Gleixner44247182010-09-28 10:40:18 +0200484{
485 irq_modify_status(irq, 0, IRQ_NOPROBE);
486}
487
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100488static inline void irq_set_probe(unsigned int irq)
Thomas Gleixner44247182010-09-28 10:40:18 +0200489{
490 irq_modify_status(irq, IRQ_NOPROBE, 0);
491}
Ralf Baechle46f4f8f2008-02-08 04:22:01 -0800492
Paul Mundt7f1b1242011-04-07 06:01:44 +0900493static inline void irq_set_nothread(unsigned int irq)
494{
495 irq_modify_status(irq, 0, IRQ_NOTHREAD);
496}
497
498static inline void irq_set_thread(unsigned int irq)
499{
500 irq_modify_status(irq, IRQ_NOTHREAD, 0);
501}
502
Thomas Gleixner6f91a522011-02-14 13:33:16 +0100503static inline void irq_set_nested_thread(unsigned int irq, bool nest)
504{
505 if (nest)
506 irq_set_status_flags(irq, IRQ_NESTED_THREAD);
507 else
508 irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
509}
510
Marc Zyngier31d9d9b2011-09-23 17:03:06 +0100511static inline void irq_set_percpu_devid_flags(unsigned int irq)
512{
513 irq_set_status_flags(irq,
514 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
515 IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
516}
517
Eric W. Biederman3a16d712006-10-04 02:16:37 -0700518/* Handle dynamic irq creation and destruction */
Yinghai Lud047f53a2009-04-27 18:02:23 -0700519extern unsigned int create_irq_nr(unsigned int irq_want, int node);
Joerg Roedel5afba622012-09-26 12:44:38 +0200520extern unsigned int __create_irqs(unsigned int from, unsigned int count,
521 int node);
Eric W. Biederman3a16d712006-10-04 02:16:37 -0700522extern int create_irq(void);
523extern void destroy_irq(unsigned int irq);
Joerg Roedel5afba622012-09-26 12:44:38 +0200524extern void destroy_irqs(unsigned int irq, unsigned int count);
Thomas Gleixnerdd87eb32006-06-29 02:24:53 -0700525
Thomas Gleixnerb7b29332010-09-29 18:46:55 +0200526/*
527 * Dynamic irq helper functions. Obsolete. Use irq_alloc_desc* and
528 * irq_free_desc instead.
529 */
Eric W. Biederman3a16d712006-10-04 02:16:37 -0700530extern void dynamic_irq_cleanup(unsigned int irq);
Thomas Gleixnerb7b29332010-09-29 18:46:55 +0200531static inline void dynamic_irq_init(unsigned int irq)
532{
533 dynamic_irq_cleanup(irq);
534}
Eric W. Biederman3a16d712006-10-04 02:16:37 -0700535
536/* Set/get chip/data for an IRQ: */
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100537extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
538extern int irq_set_handler_data(unsigned int irq, void *data);
539extern int irq_set_chip_data(unsigned int irq, void *data);
540extern int irq_set_irq_type(unsigned int irq, unsigned int type);
541extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
Alexander Gordeev51906e72012-11-19 16:01:29 +0100542extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
543 struct msi_desc *entry);
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200544extern struct irq_data *irq_get_irq_data(unsigned int irq);
Thomas Gleixnerdd87eb32006-06-29 02:24:53 -0700545
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100546static inline struct irq_chip *irq_get_chip(unsigned int irq)
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200547{
548 struct irq_data *d = irq_get_irq_data(irq);
549 return d ? d->chip : NULL;
550}
551
552static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
553{
554 return d->chip;
555}
556
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100557static inline void *irq_get_chip_data(unsigned int irq)
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200558{
559 struct irq_data *d = irq_get_irq_data(irq);
560 return d ? d->chip_data : NULL;
561}
562
563static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
564{
565 return d->chip_data;
566}
567
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100568static inline void *irq_get_handler_data(unsigned int irq)
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200569{
570 struct irq_data *d = irq_get_irq_data(irq);
571 return d ? d->handler_data : NULL;
572}
573
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100574static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200575{
576 return d->handler_data;
577}
578
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100579static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200580{
581 struct irq_data *d = irq_get_irq_data(irq);
582 return d ? d->msi_desc : NULL;
583}
584
585static inline struct msi_desc *irq_data_get_msi(struct irq_data *d)
586{
587 return d->msi_desc;
588}
589
Javier Martinez Canillas1f6236b2013-06-14 18:40:43 +0200590static inline u32 irq_get_trigger_type(unsigned int irq)
591{
592 struct irq_data *d = irq_get_irq_data(irq);
593 return d ? irqd_get_trigger_type(d) : 0;
594}
595
Sebastian Andrzej Siewiorb6873802011-07-11 12:17:31 +0200596int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
597 struct module *owner);
598
Paul Gortmakerec53cf22011-09-19 20:33:19 -0400599/* use macros to avoid needing export.h for THIS_MODULE */
600#define irq_alloc_descs(irq, from, cnt, node) \
601 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE)
602
603#define irq_alloc_desc(node) \
604 irq_alloc_descs(-1, 0, 1, node)
605
606#define irq_alloc_desc_at(at, node) \
607 irq_alloc_descs(at, at, 1, node)
608
609#define irq_alloc_desc_from(from, node) \
610 irq_alloc_descs(-1, from, 1, node)
Sebastian Andrzej Siewiorb6873802011-07-11 12:17:31 +0200611
Alexander Gordeev51906e72012-11-19 16:01:29 +0100612#define irq_alloc_descs_from(from, cnt, node) \
613 irq_alloc_descs(-1, from, cnt, node)
614
Thomas Gleixner1f5a5b82010-09-27 17:48:26 +0200615void irq_free_descs(unsigned int irq, unsigned int cnt);
Thomas Gleixner06f6c332010-10-12 12:31:46 +0200616int irq_reserve_irqs(unsigned int from, unsigned int cnt);
Thomas Gleixner1f5a5b82010-09-27 17:48:26 +0200617
Thomas Gleixner1f5a5b82010-09-27 17:48:26 +0200618static inline void irq_free_desc(unsigned int irq)
619{
620 irq_free_descs(irq, 1);
621}
622
Paul Mundt639bd122010-10-26 16:19:13 +0900623static inline int irq_reserve_irq(unsigned int irq)
624{
625 return irq_reserve_irqs(irq, 1);
626}
627
Thomas Gleixner7d828062011-04-03 11:42:53 +0200628#ifndef irq_reg_writel
629# define irq_reg_writel(val, addr) writel(val, addr)
630#endif
631#ifndef irq_reg_readl
632# define irq_reg_readl(addr) readl(addr)
633#endif
634
635/**
636 * struct irq_chip_regs - register offsets for struct irq_gci
637 * @enable: Enable register offset to reg_base
638 * @disable: Disable register offset to reg_base
639 * @mask: Mask register offset to reg_base
640 * @ack: Ack register offset to reg_base
641 * @eoi: Eoi register offset to reg_base
642 * @type: Type configuration register offset to reg_base
643 * @polarity: Polarity configuration register offset to reg_base
644 */
645struct irq_chip_regs {
646 unsigned long enable;
647 unsigned long disable;
648 unsigned long mask;
649 unsigned long ack;
650 unsigned long eoi;
651 unsigned long type;
652 unsigned long polarity;
653};
654
655/**
656 * struct irq_chip_type - Generic interrupt chip instance for a flow type
657 * @chip: The real interrupt chip which provides the callbacks
658 * @regs: Register offsets for this chip
659 * @handler: Flow handler associated with this chip
660 * @type: Chip can handle these flow types
Gerlando Falauto899f0e62013-05-06 14:30:19 +0000661 * @mask_cache_priv: Cached mask register private to the chip type
662 * @mask_cache: Pointer to cached mask register
Thomas Gleixner7d828062011-04-03 11:42:53 +0200663 *
664 * A irq_generic_chip can have several instances of irq_chip_type when
665 * it requires different functions and register offsets for different
666 * flow types.
667 */
668struct irq_chip_type {
669 struct irq_chip chip;
670 struct irq_chip_regs regs;
671 irq_flow_handler_t handler;
672 u32 type;
Gerlando Falauto899f0e62013-05-06 14:30:19 +0000673 u32 mask_cache_priv;
674 u32 *mask_cache;
Thomas Gleixner7d828062011-04-03 11:42:53 +0200675};
676
677/**
678 * struct irq_chip_generic - Generic irq chip data structure
679 * @lock: Lock to protect register and cache data access
680 * @reg_base: Register base address (virtual)
681 * @irq_base: Interrupt base nr for this chip
682 * @irq_cnt: Number of interrupts handled by this chip
Gerlando Falauto899f0e62013-05-06 14:30:19 +0000683 * @mask_cache: Cached mask register shared between all chip types
Thomas Gleixner7d828062011-04-03 11:42:53 +0200684 * @type_cache: Cached type register
685 * @polarity_cache: Cached polarity register
686 * @wake_enabled: Interrupt can wakeup from suspend
687 * @wake_active: Interrupt is marked as an wakeup from suspend source
688 * @num_ct: Number of available irq_chip_type instances (usually 1)
689 * @private: Private data for non generic chip callbacks
Thomas Gleixner088f40b2013-05-06 14:30:27 +0000690 * @installed: bitfield to denote installed interrupts
Grant Likelye8bd8342013-05-29 03:10:52 +0100691 * @unused: bitfield to denote unused interrupts
Thomas Gleixner088f40b2013-05-06 14:30:27 +0000692 * @domain: irq domain pointer
Thomas Gleixnercfefd212011-04-15 22:36:08 +0200693 * @list: List head for keeping track of instances
Thomas Gleixner7d828062011-04-03 11:42:53 +0200694 * @chip_types: Array of interrupt irq_chip_types
695 *
696 * Note, that irq_chip_generic can have multiple irq_chip_type
697 * implementations which can be associated to a particular irq line of
698 * an irq_chip_generic instance. That allows to share and protect
699 * state in an irq_chip_generic instance when we need to implement
700 * different flow mechanisms (level/edge) for it.
701 */
702struct irq_chip_generic {
703 raw_spinlock_t lock;
704 void __iomem *reg_base;
705 unsigned int irq_base;
706 unsigned int irq_cnt;
707 u32 mask_cache;
708 u32 type_cache;
709 u32 polarity_cache;
710 u32 wake_enabled;
711 u32 wake_active;
712 unsigned int num_ct;
713 void *private;
Thomas Gleixner088f40b2013-05-06 14:30:27 +0000714 unsigned long installed;
Grant Likelye8bd8342013-05-29 03:10:52 +0100715 unsigned long unused;
Thomas Gleixner088f40b2013-05-06 14:30:27 +0000716 struct irq_domain *domain;
Thomas Gleixnercfefd212011-04-15 22:36:08 +0200717 struct list_head list;
Thomas Gleixner7d828062011-04-03 11:42:53 +0200718 struct irq_chip_type chip_types[0];
719};
720
721/**
722 * enum irq_gc_flags - Initialization flags for generic irq chips
723 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
724 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
725 * irq chips which need to call irq_set_wake() on
726 * the parent irq. Usually GPIO implementations
Gerlando Falautoaf80b0f2013-05-06 14:30:21 +0000727 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
Thomas Gleixner966dc732013-05-06 14:30:22 +0000728 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
Thomas Gleixner7d828062011-04-03 11:42:53 +0200729 */
730enum irq_gc_flags {
731 IRQ_GC_INIT_MASK_CACHE = 1 << 0,
732 IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
Gerlando Falautoaf80b0f2013-05-06 14:30:21 +0000733 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
Thomas Gleixner966dc732013-05-06 14:30:22 +0000734 IRQ_GC_NO_MASK = 1 << 3,
Thomas Gleixner7d828062011-04-03 11:42:53 +0200735};
736
Thomas Gleixner088f40b2013-05-06 14:30:27 +0000737/*
738 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
739 * @irqs_per_chip: Number of interrupts per chip
740 * @num_chips: Number of chips
741 * @irq_flags_to_set: IRQ* flags to set on irq setup
742 * @irq_flags_to_clear: IRQ* flags to clear on irq setup
743 * @gc_flags: Generic chip specific setup flags
744 * @gc: Array of pointers to generic interrupt chips
745 */
746struct irq_domain_chip_generic {
747 unsigned int irqs_per_chip;
748 unsigned int num_chips;
749 unsigned int irq_flags_to_clear;
750 unsigned int irq_flags_to_set;
751 enum irq_gc_flags gc_flags;
752 struct irq_chip_generic *gc[0];
753};
754
Thomas Gleixner7d828062011-04-03 11:42:53 +0200755/* Generic chip callback functions */
756void irq_gc_noop(struct irq_data *d);
757void irq_gc_mask_disable_reg(struct irq_data *d);
758void irq_gc_mask_set_bit(struct irq_data *d);
759void irq_gc_mask_clr_bit(struct irq_data *d);
760void irq_gc_unmask_enable_reg(struct irq_data *d);
Simon Guinot659fb322011-07-06 12:41:31 -0400761void irq_gc_ack_set_bit(struct irq_data *d);
762void irq_gc_ack_clr_bit(struct irq_data *d);
Thomas Gleixner7d828062011-04-03 11:42:53 +0200763void irq_gc_mask_disable_reg_and_ack(struct irq_data *d);
764void irq_gc_eoi(struct irq_data *d);
765int irq_gc_set_wake(struct irq_data *d, unsigned int on);
766
767/* Setup functions for irq_chip_generic */
768struct irq_chip_generic *
769irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
770 void __iomem *reg_base, irq_flow_handler_t handler);
771void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
772 enum irq_gc_flags flags, unsigned int clr,
773 unsigned int set);
774int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
Thomas Gleixnercfefd212011-04-15 22:36:08 +0200775void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
776 unsigned int clr, unsigned int set);
Thomas Gleixner7d828062011-04-03 11:42:53 +0200777
Thomas Gleixner088f40b2013-05-06 14:30:27 +0000778struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
779int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
780 int num_ct, const char *name,
781 irq_flow_handler_t handler,
782 unsigned int clr, unsigned int set,
783 enum irq_gc_flags flags);
784
785
Thomas Gleixner7d828062011-04-03 11:42:53 +0200786static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
787{
788 return container_of(d->chip, struct irq_chip_type, chip);
789}
790
791#define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
792
793#ifdef CONFIG_SMP
794static inline void irq_gc_lock(struct irq_chip_generic *gc)
795{
796 raw_spin_lock(&gc->lock);
797}
798
799static inline void irq_gc_unlock(struct irq_chip_generic *gc)
800{
801 raw_spin_unlock(&gc->lock);
802}
803#else
804static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
805static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
806#endif
807
Ingo Molnar06fcb0c2006-06-29 02:24:40 -0700808#endif /* _LINUX_IRQ_H */