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gerrit-public.fairphone.software / kernel / msm-4.9 / b67b0efa47ffd2f97a25386fd184491097174bc9 / . / arch / arm64 / boot / dts / qcom / sdm670.dtsi
blob: 4d4e91862fe2ebfc5b8474d09172052dc194b9c6 [file] [log] [blame]
Zhen Kong0ebe1bc32018-01-02 14:53:51 -0800[diff] [blame]1/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include "skeleton64.dtsi"
14#include <dt-bindings/interrupt-controller/arm-gic.h>
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]15#include <dt-bindings/clock/qcom,gcc-sdm845.h>
16#include <dt-bindings/clock/qcom,camcc-sdm845.h>
17#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
18#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
19#include <dt-bindings/clock/qcom,videocc-sdm845.h>
20#include <dt-bindings/clock/qcom,cpucc-sdm845.h>
21#include <dt-bindings/clock/qcom,rpmh.h>
Maulik Shahc77d1d22017-06-15 14:04:50 +0530[diff] [blame]22#include <dt-bindings/soc/qcom,tcs-mbox.h>
Tirupathi Reddy0cfe2082017-06-08 14:24:13 +0530[diff] [blame]23#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
Odelu Kukatla6f3ffa12017-08-10 12:31:06 +0530[diff] [blame]24#include <dt-bindings/clock/qcom,aop-qmp.h>
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]25
Santosh Mardi903c95d2017-09-25 10:36:29 +0530[diff] [blame]26#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
27
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]28/ {
29 model = "Qualcomm Technologies, Inc. SDM670";
30 compatible = "qcom,sdm670";
31 qcom,msm-id = <336 0x0>;
Maulik Shah30ebbde2017-06-15 10:02:54 +0530[diff] [blame]32 interrupt-parent = <&pdc>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]33
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]34 aliases {
35 ufshc1 = &ufshc_mem; /* Embedded UFS slot */
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]36 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
Vijay Viswanathee4340d2017-08-28 09:50:18 +0530[diff] [blame]37 sdhc2 = &sdhc_2; /* SDC2 SD Card slot */
Mukesh Kumar Savaliya7b272542017-07-10 19:35:29 +0530[diff] [blame]38 serial0 = &qupv3_se12_2uart;
39 spi0 = &qupv3_se8_spi;
40 i2c0 = &qupv3_se10_i2c;
41 i2c1 = &qupv3_se3_i2c;
42 hsuart0 = &qupv3_se6_4uart;
43 };
44
Lingutla Chandrasekhard9eb37a2017-10-03 19:53:36 +0530[diff] [blame]45 chosen {
Pavankumar Kondeti2c218d72017-10-03 19:31:31 +0530[diff] [blame]46 bootargs = "rcupdate.rcu_expedited=1 core_ctl_disable_cpumask=6-7";
Lingutla Chandrasekhard9eb37a2017-10-03 19:53:36 +0530[diff] [blame]47 };
48
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]49 cpus {
50 #address-cells = <2>;
51 #size-cells = <0>;
52
53 CPU0: cpu@0 {
54 device_type = "cpu";
55 compatible = "arm,armv8";
56 reg = <0x0 0x0>;
57 enable-method = "psci";
58 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]59 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]60 cpu-release-addr = <0x0 0x90000000>;
61 next-level-cache = <&L2_0>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]62 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]63 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]64 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]65 L2_0: l2-cache {
66 compatible = "arm,arch-cache";
67 cache-size = <0x20000>;
68 cache-level = <2>;
69 next-level-cache = <&L3_0>;
70 L3_0: l3-cache {
71 compatible = "arm,arch-cache";
72 cache-size = <0x100000>;
73 cache-level = <3>;
74 };
75 };
76 L1_I_0: l1-icache {
77 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]78 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]79 };
80 L1_D_0: l1-dcache {
81 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]82 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]83 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]84 L1_TLB_0: l1-tlb {
85 qcom,dump-size = <0x3000>;
86 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]87 };
88
89 CPU1: cpu@100 {
90 device_type = "cpu";
91 compatible = "arm,armv8";
92 reg = <0x0 0x100>;
93 enable-method = "psci";
94 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]95 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]96 cpu-release-addr = <0x0 0x90000000>;
97 next-level-cache = <&L2_100>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]98 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]99 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]100 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]101 L2_100: l2-cache {
102 compatible = "arm,arch-cache";
103 cache-size = <0x20000>;
104 cache-level = <2>;
105 next-level-cache = <&L3_0>;
106 };
107 L1_I_100: l1-icache {
108 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]109 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]110 };
111 L1_D_100: l1-dcache {
112 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]113 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]114 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]115 L1_TLB_100: l1-tlb {
116 qcom,dump-size = <0x3000>;
117 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]118 };
119
120 CPU2: cpu@200 {
121 device_type = "cpu";
122 compatible = "arm,armv8";
123 reg = <0x0 0x200>;
124 enable-method = "psci";
125 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]126 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]127 cpu-release-addr = <0x0 0x90000000>;
128 next-level-cache = <&L2_200>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]129 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]130 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]131 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]132 L2_200: l2-cache {
133 compatible = "arm,arch-cache";
134 cache-size = <0x20000>;
135 cache-level = <2>;
136 next-level-cache = <&L3_0>;
137 };
138 L1_I_200: l1-icache {
139 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]140 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]141 };
142 L1_D_200: l1-dcache {
143 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]144 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]145 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]146 L1_TLB_200: l1-tlb {
147 qcom,dump-size = <0x3000>;
148 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]149 };
150
151 CPU3: cpu@300 {
152 device_type = "cpu";
153 compatible = "arm,armv8";
154 reg = <0x0 0x300>;
155 enable-method = "psci";
156 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]157 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]158 cpu-release-addr = <0x0 0x90000000>;
159 next-level-cache = <&L2_300>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]160 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]161 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]162 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]163 L2_300: l2-cache {
164 compatible = "arm,arch-cache";
165 cache-size = <0x20000>;
166 cache-level = <2>;
167 next-level-cache = <&L3_0>;
168 };
169 L1_I_300: l1-icache {
170 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]171 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]172 };
173 L1_D_300: l1-dcache {
174 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]175 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]176 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]177 L1_TLB_300: l1-tlb {
178 qcom,dump-size = <0x3000>;
179 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]180 };
181
182 CPU4: cpu@400 {
183 device_type = "cpu";
184 compatible = "arm,armv8";
185 reg = <0x0 0x400>;
186 enable-method = "psci";
187 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]188 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]189 cpu-release-addr = <0x0 0x90000000>;
190 next-level-cache = <&L2_400>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]191 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]192 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]193 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]194 L2_400: l2-cache {
195 compatible = "arm,arch-cache";
196 cache-size = <0x20000>;
197 cache-level = <2>;
198 next-level-cache = <&L3_0>;
199 };
200 L1_I_400: l1-icache {
201 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]202 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]203 };
204 L1_D_400: l1-dcache {
205 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]206 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]207 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]208 L1_TLB_400: l1-tlb {
209 qcom,dump-size = <0x3000>;
210 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]211 };
212
213 CPU5: cpu@500 {
214 device_type = "cpu";
215 compatible = "arm,armv8";
216 reg = <0x0 0x500>;
217 enable-method = "psci";
218 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]219 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]220 cpu-release-addr = <0x0 0x90000000>;
221 next-level-cache = <&L2_500>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]222 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]223 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]224 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]225 L2_500: l2-cache {
226 compatible = "arm,arch-cache";
227 cache-size = <0x20000>;
228 cache-level = <2>;
229 next-level-cache = <&L3_0>;
230 };
231 L1_I_500: l1-icache {
232 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]233 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]234 };
235 L1_D_500: l1-dcache {
236 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]237 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]238 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]239 L1_TLB_500: l1-tlb {
240 qcom,dump-size = <0x3000>;
241 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]242 };
243
244 CPU6: cpu@600 {
245 device_type = "cpu";
246 compatible = "arm,armv8";
247 reg = <0x0 0x600>;
248 enable-method = "psci";
249 efficiency = <1740>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]250 cache-size = <0x20000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]251 cpu-release-addr = <0x0 0x90000000>;
252 next-level-cache = <&L2_600>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]253 sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]254 qcom,lmh-dcvs = <&lmh_dcvs1>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]255 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]256 L2_600: l2-cache {
257 compatible = "arm,arch-cache";
258 cache-size = <0x40000>;
259 cache-level = <2>;
260 next-level-cache = <&L3_0>;
261 };
262 L1_I_600: l1-icache {
263 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]264 qcom,dump-size = <0x24000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]265 };
266 L1_D_600: l1-dcache {
267 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]268 qcom,dump-size = <0x14000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]269 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]270 L1_TLB_600: l1-tlb {
271 qcom,dump-size = <0x3c000>;
272 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]273 };
274
275 CPU7: cpu@700 {
276 device_type = "cpu";
277 compatible = "arm,armv8";
278 reg = <0x0 0x700>;
279 enable-method = "psci";
280 efficiency = <1740>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]281 cache-size = <0x20000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]282 cpu-release-addr = <0x0 0x90000000>;
283 next-level-cache = <&L2_700>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]284 sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]285 qcom,lmh-dcvs = <&lmh_dcvs1>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]286 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]287 L2_700: l2-cache {
288 compatible = "arm,arch-cache";
289 cache-size = <0x40000>;
290 cache-level = <2>;
291 next-level-cache = <&L3_0>;
292 };
293 L1_I_700: l1-icache {
294 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]295 qcom,dump-size = <0x24000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]296 };
297 L1_D_700: l1-dcache {
298 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]299 qcom,dump-size = <0x14000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]300 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]301 L1_TLB_700: l1-tlb {
302 qcom,dump-size = <0x3c000>;
303 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]304 };
305
306 cpu-map {
307 cluster0 {
308 core0 {
309 cpu = <&CPU0>;
310 };
311
312 core1 {
313 cpu = <&CPU1>;
314 };
315
316 core2 {
317 cpu = <&CPU2>;
318 };
319
320 core3 {
321 cpu = <&CPU3>;
322 };
323
324 core4 {
325 cpu = <&CPU4>;
326 };
327
328 core5 {
329 cpu = <&CPU5>;
330 };
331 };
332 cluster1 {
333 core0 {
334 cpu = <&CPU6>;
335 };
336
337 core1 {
338 cpu = <&CPU7>;
339 };
340 };
341 };
342 };
343
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]344 energy_costs: energy-costs {
345 compatible = "sched-energy";
346
347 CPU_COST_0: core-cost0 {
348 busy-cost-data = <
349 300000 14
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]350 576000 25
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]351 748800 31
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]352 998400 46
353 1209600 57
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]354 1324800 84
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]355 1516800 96
356 1612800 114
Pavankumar Kondeti80872462017-11-06 08:57:45 +0530[diff] [blame]357 1708800 139
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]358 >;
359 idle-cost-data = <
360 12 10 8 6
361 >;
362 };
363 CPU_COST_1: core-cost1 {
364 busy-cost-data = <
365 300000 256
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]366 652800 307
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]367 825600 332
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]368 979200 382
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]369 1132800 408
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]370 1363200 448
Pavankumar Kondeti865e7562017-11-06 08:57:45 +0530[diff] [blame]371 1536000 586
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]372 1747200 641
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]373 1843200 659
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]374 1996800 696
Pavankumar Kondetid019a602017-11-06 08:57:45 +0530[diff] [blame]375 2016000 865
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]376 2054400 876
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]377 2169600 900
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]378 2208000 924
379 2361600 948
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]380 2400000 1170
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]381 2457600 1200
382 2515200 1300
383 2611200 1400
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]384 >;
385 idle-cost-data = <
386 100 80 60 40
387 >;
388 };
389 CLUSTER_COST_0: cluster-cost0 {
390 busy-cost-data = <
391 300000 5
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]392 576000 7
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]393 748800 8
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]394 998400 9
395 1209600 10
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]396 1324800 13
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]397 1516800 15
398 1612800 16
Pavankumar Kondeti80872462017-11-06 08:57:45 +0530[diff] [blame]399 1708800 19
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]400 >;
401 idle-cost-data = <
402 4 3 2 1
403 >;
404 };
405 CLUSTER_COST_1: cluster-cost1 {
406 busy-cost-data = <
407 300000 25
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]408 652800 30
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]409 825600 33
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]410 979200 38
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]411 1132800 40
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]412 1363200 44
Pavankumar Kondeti865e7562017-11-06 08:57:45 +0530[diff] [blame]413 1536000 58
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]414 1747200 64
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]415 1843200 65
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]416 1996800 69
Pavankumar Kondetid019a602017-11-06 08:57:45 +0530[diff] [blame]417 2016000 85
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]418 2054400 87
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]419 2169600 90
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]420 2208000 92
421 2361600 94
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]422 2400000 117
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]423 2457600 120
424 2515200 130
425 2611200 140
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]426 >;
427 idle-cost-data = <
428 4 3 2 1
429 >;
430 };
431 };
432
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]433 psci {
434 compatible = "arm,psci-1.0";
435 method = "smc";
436 };
437
438 soc: soc { };
439
Imran Khanb1066fa2017-08-01 17:20:22 +0530[diff] [blame]440 vendor: vendor {
441 #address-cells = <1>;
442 #size-cells = <1>;
443 ranges = <0 0 0 0xffffffff>;
444 compatible = "simple-bus";
445 };
446
Imran Khan5381c932017-08-02 11:27:07 +0530[diff] [blame]447 firmware: firmware {
448 android {
449 compatible = "android,firmware";
450
monisingfb2cb762017-12-19 14:40:49 +0530[diff] [blame]451 vbmeta {
452 compatible = "android,vbmeta";
453 parts = "vbmeta,boot,system,vendor,dtbo";
454 };
455
Imran Khan5381c932017-08-02 11:27:07 +0530[diff] [blame]456 fstab {
457 compatible = "android,fstab";
458 vendor {
459 compatible = "android,vendor";
460 dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
461 type = "ext4";
462 mnt_flags = "ro,barrier=1,discard";
AnilKumar Chimata0d646ab2017-10-25 22:09:03 +0530[diff] [blame]463 fsmgr_flags = "wait,slotselect,avb";
Imran Khan5381c932017-08-02 11:27:07 +0530[diff] [blame]464 };
465 };
466 };
467 };
468
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]469 reserved-memory {
470 #address-cells = <2>;
471 #size-cells = <2>;
472 ranges;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]473
Vijayanand Jitta0ef73982017-12-11 11:19:29 +0530[diff] [blame]474 hyp_region: hyp_region@85700000 {
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]475 compatible = "removed-dma-pool";
476 no-map;
Vijayanand Jitta0ef73982017-12-11 11:19:29 +0530[diff] [blame]477 reg = <0 0x85700000 0 0x600000>;
478 };
479
480 xbl_region: xbl_region@85e00000 {
481 compatible = "removed-dma-pool";
482 no-map;
483 reg = <0 0x85e00000 0 0x100000>;
484 };
485
486 removed_region: removed_region@85fc0000 {
487 compatible = "removed-dma-pool";
488 no-map;
489 reg = <0 0x85fc0000 0 0x2f40000>;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]490 };
491
492 pil_camera_mem: camera_region@8ab00000 {
493 compatible = "removed-dma-pool";
494 no-map;
495 reg = <0 0x8ab00000 0 0x500000>;
496 };
497
498 pil_modem_mem: modem_region@8b000000 {
499 compatible = "removed-dma-pool";
500 no-map;
501 reg = <0 0x8b000000 0 0x7e00000>;
502 };
503
504 pil_video_mem: pil_video_region@92e00000 {
505 compatible = "removed-dma-pool";
506 no-map;
507 reg = <0 0x92e00000 0 0x500000>;
508 };
509
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]510 wlan_msa_mem: wlan_msa_region@93300000 {
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]511 compatible = "removed-dma-pool";
512 no-map;
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]513 reg = <0 0x93300000 0 0x100000>;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]514 };
515
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]516 pil_cdsp_mem: cdsp_regions@93400000 {
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]517 compatible = "removed-dma-pool";
518 no-map;
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]519 reg = <0 0x93400000 0 0x800000>;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]520 };
521
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]522 pil_mba_mem: pil_mba_region@0x93c00000 {
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]523 compatible = "removed-dma-pool";
524 no-map;
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]525 reg = <0 0x93c00000 0 0x200000>;
526 };
527
528 pil_adsp_mem: pil_adsp_region@93e00000 {
529 compatible = "removed-dma-pool";
530 no-map;
531 reg = <0 0x93e00000 0 0x1e00000>;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]532 };
533
Prakash Gupta7c571ef2018-01-19 17:57:47 +0530[diff] [blame]534 pil_ipa_fw_mem: ips_fw_region@0x95c00000 {
535 compatible = "removed-dma-pool";
536 no-map;
537 reg = <0 0x95c00000 0 0x10000>;
538 };
539
540 pil_ipa_gsi_mem: ipa_gsi_region@0x95c10000 {
541 compatible = "removed-dma-pool";
542 no-map;
543 reg = <0 0x95c10000 0 0x5000>;
544 };
545
546 pil_gpu_mem: gpu_region@0x95c15000 {
547 compatible = "removed-dma-pool";
548 no-map;
549 reg = <0 0x95c15000 0 0x2000>;
550 };
551
552 qseecom_mem: qseecom_region@0x9e400000 {
553 compatible = "shared-dma-pool";
554 no-map;
555 reg = <0 0x9e400000 0 0x1400000>;
556 };
557
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]558 adsp_mem: adsp_region {
559 compatible = "shared-dma-pool";
560 alloc-ranges = <0 0x00000000 0 0xffffffff>;
561 reusable;
562 alignment = <0 0x400000>;
563 size = <0 0xc00000>;
564 };
565
Zhen Kong0ebe1bc32018-01-02 14:53:51 -0800[diff] [blame]566 qseecom_ta_mem: qseecom_ta_region {
567 compatible = "shared-dma-pool";
568 alloc-ranges = <0 0x00000000 0 0xffffffff>;
569 reusable;
570 alignment = <0 0x400000>;
571 size = <0 0x1000000>;
572 };
573
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]574 sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
575 compatible = "shared-dma-pool";
576 alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */
577 reusable;
578 alignment = <0 0x400000>;
579 size = <0 0x800000>;
580 };
581
582 secure_display_memory: secure_display_region {
583 compatible = "shared-dma-pool";
584 alloc-ranges = <0 0x00000000 0 0xffffffff>;
585 reusable;
586 alignment = <0 0x400000>;
587 size = <0 0x5c00000>;
588 };
589
Jayant Shekhare3191272018-01-30 16:49:08 +0530[diff] [blame]590 cont_splash_memory: cont_splash_region@9c000000 {
591 reg = <0x0 0x9c000000 0x0 0x02400000>;
Jayant Shekharb59d1692017-11-10 14:21:40 +0530[diff] [blame]592 label = "cont_splash_region";
593 };
594
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]595 dump_mem: mem_dump_region {
596 compatible = "shared-dma-pool";
597 reusable;
598 size = <0 0x2400000>;
599 };
600
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]601 /* global autoconfigured region for contiguous allocations */
602 linux,cma {
603 compatible = "shared-dma-pool";
604 alloc-ranges = <0 0x00000000 0 0xffffffff>;
605 reusable;
606 alignment = <0 0x400000>;
607 size = <0 0x2000000>;
608 linux,cma-default;
609 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]610 };
611};
612
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]613#include "sdm670-ion.dtsi"
614
Dhoat Harpal92d63dea2017-06-06 21:20:26 +0530[diff] [blame]615#include "sdm670-smp2p.dtsi"
616
c_mtharuce962e42017-12-05 22:41:17 +0530[diff] [blame]617#include "msm-rdbg.dtsi"
618
Mukesh Kumar Savaliya065ca482017-06-06 14:44:45 +0530[diff] [blame]619#include "sdm670-qupv3.dtsi"
620
Saranya Chiduraf49fee12017-06-19 10:52:37 +0530[diff] [blame]621#include "sdm670-coresight.dtsi"
Manikanta Kanamarlapudid4abc602017-08-28 19:23:41 +0530[diff] [blame]622
623#include "sdm670-vidc.dtsi"
624
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]625#include "sdm670-sde-pll.dtsi"
626
627#include "sdm670-sde.dtsi"
628
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]629&soc {
630 #address-cells = <1>;
631 #size-cells = <1>;
632 ranges = <0 0 0 0xffffffff>;
633 compatible = "simple-bus";
634
Saranya Chidura0e8b4262017-10-04 13:06:26 +0530[diff] [blame]635 jtag_mm0: jtagmm@7040000 {
636 compatible = "qcom,jtagv8-mm";
637 reg = <0x7040000 0x1000>;
638 reg-names = "etm-base";
639
640 clocks = <&clock_aop QDSS_CLK>;
641 clock-names = "core_clk";
642
643 qcom,coresight-jtagmm-cpu = <&CPU0>;
644 };
645
646 jtag_mm1: jtagmm@7140000 {
647 compatible = "qcom,jtagv8-mm";
648 reg = <0x7140000 0x1000>;
649 reg-names = "etm-base";
650
651 clocks = <&clock_aop QDSS_CLK>;
652 clock-names = "core_clk";
653
654 qom,coresight-jtagmm-cpu = <&CPU1>;
655 };
656
657 jtag_mm2: jtagmm@7240000 {
658 compatible = "qcom,jtagv8-mm";
659 reg = <0x7240000 0x1000>;
660 reg-names = "etm-base";
661
662 clocks = <&clock_aop QDSS_CLK>;
663 clock-names = "core_clk";
664
665 qcom,coresight-jtagmm-cpu = <&CPU2>;
666 };
667
668 jtag_mm3: jtagmm@7340000 {
669 compatible = "qcom,jtagv8-mm";
670 reg = <0x7340000 0x1000>;
671 reg-names = "etm-base";
672
673 clocks = <&clock_aop QDSS_CLK>;
674 clock-names = "core_clk";
675
676 qcom,coresight-jtagmm-cpu = <&CPU3>;
677 };
678
679 jtag_mm4: jtagmm@7440000 {
680 compatible = "qcom,jtagv8-mm";
681 reg = <0x7440000 0x1000>;
682 reg-names = "etm-base";
683
684 clocks = <&clock_aop QDSS_CLK>;
685 clock-names = "core_clk";
686
687 qcom,coresight-jtagmm-cpu = <&CPU4>;
688 };
689
690 jtag_mm5: jtagmm@7540000 {
691 compatible = "qcom,jtagv8-mm";
692 reg = <0x7540000 0x1000>;
693 reg-names = "etm-base";
694
695 clocks = <&clock_aop QDSS_CLK>;
696 clock-names = "core_clk";
697
698 qcom,coresight-jtagmm-cpu = <&CPU5>;
699 };
700
701 jtag_mm6: jtagmm@7640000 {
702 compatible = "qcom,jtagv8-mm";
703 reg = <0x7640000 0x1000>;
704 reg-names = "etm-base";
705
706 clocks = <&clock_aop QDSS_CLK>;
707 clock-names = "core_clk";
708
709 qcom,coresight-jtagmm-cpu = <&CPU6>;
710 };
711
712 jtag_mm7: jtagmm@7740000 {
713 compatible = "qcom,jtagv8-mm";
714 reg = <0x7740000 0x1000>;
715 reg-names = "etm-base";
716
717 clocks = <&clock_aop QDSS_CLK>;
718 clock-names = "core_clk";
719
720 qcom,coresight-jtagmm-cpu = <&CPU7>;
721 };
722
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]723 intc: interrupt-controller@17a00000 {
724 compatible = "arm,gic-v3";
725 #interrupt-cells = <3>;
726 interrupt-controller;
727 #redistributor-regions = <1>;
728 redistributor-stride = <0x0 0x20000>;
729 reg = <0x17a00000 0x10000>, /* GICD */
730 <0x17a60000 0x100000>; /* GICR * 8 */
731 interrupts = <1 9 4>;
Maulik Shah30ebbde2017-06-15 10:02:54 +0530[diff] [blame]732 interrupt-parent = <&intc>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]733 };
734
Raghavendra Kakarla04f032162017-12-08 19:11:54 +0530[diff] [blame]735 pdc: interrupt-controller@b220000{
736 compatible = "qcom,pdc-sdm670";
737 reg = <0xb220000 0x400>;
738 #interrupt-cells = <3>;
739 interrupt-parent = <&intc>;
740 interrupt-controller;
741 };
742
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]743 timer {
744 compatible = "arm,armv8-timer";
745 interrupts = <1 1 0xf08>,
746 <1 2 0xf08>,
747 <1 3 0xf08>,
748 <1 0 0xf08>;
749 clock-frequency = <19200000>;
750 };
751
Manoj Prabhu B95b1bc72017-11-17 15:09:29 +0530[diff] [blame]752 qcom,memshare {
753 compatible = "qcom,memshare";
754
755 qcom,client_1 {
756 compatible = "qcom,memshare-peripheral";
757 qcom,peripheral-size = <0x0>;
758 qcom,client-id = <0>;
759 qcom,allocate-boot-time;
760 label = "modem";
761 };
762
763 qcom,client_2 {
764 compatible = "qcom,memshare-peripheral";
765 qcom,peripheral-size = <0x0>;
766 qcom,client-id = <2>;
767 label = "modem";
768 };
769
770 mem_client_3_size: qcom,client_3 {
771 compatible = "qcom,memshare-peripheral";
772 qcom,peripheral-size = <0x500000>;
773 qcom,client-id = <1>;
Manoj Prabhu B991f9222018-01-03 19:13:56 +0530[diff] [blame]774 qcom,allocate-boot-time;
Manoj Prabhu B95b1bc72017-11-17 15:09:29 +0530[diff] [blame]775 label = "modem";
776 };
777 };
778
Lakshmi Sunkarabbd69892017-06-09 13:17:10 +0530[diff] [blame]779 qcom,sps {
780 compatible = "qcom,msm_sps_4k";
781 qcom,pipe-attr-ee;
782 };
783
mohamed sunfeer7462bc82017-10-11 22:50:13 +0530[diff] [blame]784 qcom_cedev: qcedev@1de0000 {
785 compatible = "qcom,qcedev";
786 reg = <0x1de0000 0x20000>,
787 <0x1dc4000 0x24000>;
788 reg-names = "crypto-base","crypto-bam-base";
789 interrupts = <0 272 0>;
790 qcom,bam-pipe-pair = <3>;
791 qcom,ce-hw-instance = <0>;
792 qcom,ce-device = <0>;
793 qcom,ce-hw-shared;
794 qcom,bam-ee = <0>;
795 qcom,msm-bus,name = "qcedev-noc";
796 qcom,msm-bus,num-cases = <2>;
797 qcom,msm-bus,num-paths = <1>;
798 qcom,msm-bus,vectors-KBps =
799 <125 512 0 0>,
800 <125 512 393600 393600>;
801 clock-names = "core_clk_src", "core_clk",
802 "iface_clk", "bus_clk";
803 clocks = <&clock_gcc GCC_CE1_CLK>,
804 <&clock_gcc GCC_CE1_CLK>,
805 <&clock_gcc GCC_CE1_AHB_CLK>,
806 <&clock_gcc GCC_CE1_AXI_CLK>;
807 qcom,ce-opp-freq = <171430000>;
808 qcom,request-bw-before-clk;
mohamed sunfeer4b2ca442017-11-07 14:46:45 +0530[diff] [blame]809 qcom,smmu-s1-enable;
mohamed sunfeerdce9b922017-11-11 22:14:58 +0530[diff] [blame]810 iommus = <&apps_smmu 0x706 0x1>,
811 <&apps_smmu 0x716 0x1>;
mohamed sunfeer7462bc82017-10-11 22:50:13 +0530[diff] [blame]812 };
813
Tatenda Chipeperekwa8a77c8a2018-01-30 14:50:11 -0800[diff] [blame]814 qcom_msmhdcp: qcom,msm_hdcp {
815 compatible = "qcom,msm-hdcp";
816 };
817
mohamed sunfeer7462bc82017-10-11 22:50:13 +0530[diff] [blame]818 qcom_crypto: qcrypto@1de0000 {
819 compatible = "qcom,qcrypto";
820 reg = <0x1de0000 0x20000>,
821 <0x1dc4000 0x24000>;
822 reg-names = "crypto-base","crypto-bam-base";
823 interrupts = <0 272 0>;
824 qcom,bam-pipe-pair = <2>;
825 qcom,ce-hw-instance = <0>;
826 qcom,ce-device = <0>;
827 qcom,bam-ee = <0>;
828 qcom,ce-hw-shared;
829 qcom,clk-mgmt-sus-res;
830 qcom,msm-bus,name = "qcrypto-noc";
831 qcom,msm-bus,num-cases = <2>;
832 qcom,msm-bus,num-paths = <1>;
833 qcom,msm-bus,vectors-KBps =
834 <125 512 0 0>,
835 <125 512 393600 393600>;
836 clock-names = "core_clk_src", "core_clk",
837 "iface_clk", "bus_clk";
838 clocks = <&clock_gcc GCC_CE1_CLK>,
839 <&clock_gcc GCC_CE1_CLK>,
840 <&clock_gcc GCC_CE1_AHB_CLK>,
841 <&clock_gcc GCC_CE1_AXI_CLK>;
842 qcom,ce-opp-freq = <171430000>;
843 qcom,request-bw-before-clk;
844 qcom,use-sw-aes-cbc-ecb-ctr-algo;
845 qcom,use-sw-aes-xts-algo;
846 qcom,use-sw-aes-ccm-algo;
847 qcom,use-sw-aead-algo;
848 qcom,use-sw-ahash-algo;
849 qcom,use-sw-hmac-algo;
mohamed sunfeer4b2ca442017-11-07 14:46:45 +0530[diff] [blame]850 qcom,smmu-s1-enable;
mohamed sunfeerdce9b922017-11-11 22:14:58 +0530[diff] [blame]851 iommus = <&apps_smmu 0x704 0x1>,
852 <&apps_smmu 0x714 0x1>;
mohamed sunfeer7462bc82017-10-11 22:50:13 +0530[diff] [blame]853 };
854
Abir Ghoshb849ab22017-09-19 13:03:11 +0530[diff] [blame]855 qcom,qbt1000 {
856 compatible = "qcom,qbt1000";
857 clock-names = "core", "iface";
858 clock-frequency = <25000000>;
859 qcom,ipc-gpio = <&tlmm 121 0>;
860 qcom,finger-detect-gpio = <&tlmm 122 0>;
861 };
862
mohamed sunfeer71b31322017-09-20 00:46:46 +0530[diff] [blame]863 qcom_seecom: qseecom@86d00000 {
864 compatible = "qcom,qseecom";
865 reg = <0x86d00000 0x2200000>;
866 reg-names = "secapp-region";
867 qcom,hlos-num-ce-hw-instances = <1>;
868 qcom,hlos-ce-hw-instance = <0>;
869 qcom,qsee-ce-hw-instance = <0>;
870 qcom,disk-encrypt-pipe-pair = <2>;
871 qcom,support-fde;
872 qcom,no-clock-support;
Neeraj Soni7c4254c2017-11-15 11:13:14 +0530[diff] [blame]873 qcom,fde-key-size;
mohamed sunfeer71b31322017-09-20 00:46:46 +0530[diff] [blame]874 qcom,appsbl-qseecom-support;
875 qcom,msm-bus,name = "qseecom-noc";
876 qcom,msm-bus,num-cases = <4>;
877 qcom,msm-bus,num-paths = <1>;
878 qcom,msm-bus,vectors-KBps =
879 <125 512 0 0>,
880 <125 512 200000 400000>,
881 <125 512 300000 800000>,
882 <125 512 400000 1000000>;
883 clock-names = "core_clk_src", "core_clk",
884 "iface_clk", "bus_clk";
885 clocks = <&clock_gcc GCC_CE1_CLK>,
886 <&clock_gcc GCC_CE1_CLK>,
887 <&clock_gcc GCC_CE1_AHB_CLK>,
888 <&clock_gcc GCC_CE1_AXI_CLK>;
889 qcom,ce-opp-freq = <171430000>;
890 qcom,qsee-reentrancy-support = <2>;
891 };
892
mohamed sunfeer732f7572017-09-19 19:51:11 +0530[diff] [blame]893 qcom_tzlog: tz-log@146bf720 {
894 compatible = "qcom,tz-log";
895 reg = <0x146bf720 0x3000>;
896 qcom,hyplog-enabled;
897 hyplog-address-offset = <0x410>;
898 hyplog-size-offset = <0x414>;
899 };
900
mohamed sunfeer2228b242017-09-19 19:10:08 +0530[diff] [blame]901 qcom_rng: qrng@793000{
902 compatible = "qcom,msm-rng";
903 reg = <0x793000 0x1000>;
904 qcom,msm-rng-iface-clk;
905 qcom,no-qrng-config;
906 qcom,msm-bus,name = "msm-rng-noc";
907 qcom,msm-bus,num-cases = <2>;
908 qcom,msm-bus,num-paths = <1>;
909 qcom,msm-bus,vectors-KBps =
910 <1 618 0 0>, /* No vote */
911 <1 618 0 800>; /* 100 KHz */
912 clocks = <&clock_gcc GCC_PRNG_AHB_CLK>;
913 clock-names = "iface_clk";
914 };
915
Manaf Meethalavalappu Pallikunhi52c7ba12017-09-07 01:41:43 +0530[diff] [blame]916 thermal_zones: thermal-zones {};
Rama Krishna Phani Aa3c0e782017-07-17 20:09:15 +0530[diff] [blame]917
918 tsens0: tsens@c222000 {
919 compatible = "qcom,tsens24xx";
920 reg = <0xc222000 0x4>,
921 <0xc263000 0x1ff>;
922 reg-names = "tsens_srot_physical",
923 "tsens_tm_physical";
924 interrupts = <0 506 0>, <0 508 0>;
925 interrupt-names = "tsens-upper-lower", "tsens-critical";
926 #thermal-sensor-cells = <1>;
927 };
928
929 tsens1: tsens@c223000 {
930 compatible = "qcom,tsens24xx";
931 reg = <0xc223000 0x4>,
932 <0xc265000 0x1ff>;
933 reg-names = "tsens_srot_physical",
934 "tsens_tm_physical";
935 interrupts = <0 507 0>, <0 509 0>;
936 interrupt-names = "tsens-upper-lower", "tsens-critical";
937 #thermal-sensor-cells = <1>;
938 };
939
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]940 timer@0x17c90000{
941 #address-cells = <1>;
942 #size-cells = <1>;
943 ranges;
944 compatible = "arm,armv7-timer-mem";
945 reg = <0x17c90000 0x1000>;
946 clock-frequency = <19200000>;
947
948 frame@0x17ca0000 {
949 frame-number = <0>;
950 interrupts = <0 7 0x4>,
951 <0 6 0x4>;
952 reg = <0x17ca0000 0x1000>,
953 <0x17cb0000 0x1000>;
954 };
955
956 frame@17cc0000 {
957 frame-number = <1>;
958 interrupts = <0 8 0x4>;
959 reg = <0x17cc0000 0x1000>;
960 status = "disabled";
961 };
962
963 frame@17cd0000 {
964 frame-number = <2>;
965 interrupts = <0 9 0x4>;
966 reg = <0x17cd0000 0x1000>;
967 status = "disabled";
968 };
969
970 frame@17ce0000 {
971 frame-number = <3>;
972 interrupts = <0 10 0x4>;
973 reg = <0x17ce0000 0x1000>;
974 status = "disabled";
975 };
976
977 frame@17cf0000 {
978 frame-number = <4>;
979 interrupts = <0 11 0x4>;
980 reg = <0x17cf0000 0x1000>;
981 status = "disabled";
982 };
983
984 frame@17d00000 {
985 frame-number = <5>;
986 interrupts = <0 12 0x4>;
987 reg = <0x17d00000 0x1000>;
988 status = "disabled";
989 };
990
991 frame@17d10000 {
992 frame-number = <6>;
993 interrupts = <0 13 0x4>;
994 reg = <0x17d10000 0x1000>;
995 status = "disabled";
996 };
997 };
998
999 restart@10ac000 {
1000 compatible = "qcom,pshold";
1001 reg = <0xC264000 0x4>,
1002 <0x1fd3000 0x4>;
1003 reg-names = "pshold-base", "tcsr-boot-misc-detect";
1004 };
1005
Maulik Shah6bf7d5d2017-07-27 09:48:42 +0530[diff] [blame]1006 aop-msg-client {
1007 compatible = "qcom,debugfs-qmp-client";
1008 mboxes = <&qmp_aop 0>;
1009 mbox-names = "aop";
1010 };
1011
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1012 clock_rpmh: qcom,rpmhclk {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1013 compatible = "qcom,rpmh-clk-sdm670";
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1014 #clock-cells = <1>;
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1015 mboxes = <&apps_rsc 0>;
1016 mbox-names = "apps";
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1017 };
1018
1019 clock_gcc: qcom,gcc@100000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1020 compatible = "qcom,gcc-sdm670", "syscon";
1021 reg = <0x100000 0x1f0000>;
1022 reg-names = "cc_base";
1023 vdd_cx-supply = <&pm660l_s3_level>;
1024 vdd_cx_ao-supply = <&pm660l_s3_level_ao>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1025 #clock-cells = <1>;
1026 #reset-cells = <1>;
1027 };
1028
1029 clock_videocc: qcom,videocc@ab00000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1030 compatible = "qcom,video_cc-sdm670", "syscon";
1031 reg = <0xab00000 0x10000>;
1032 reg-names = "cc_base";
1033 vdd_cx-supply = <&pm660l_s3_level>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1034 #clock-cells = <1>;
1035 #reset-cells = <1>;
1036 };
1037
1038 clock_camcc: qcom,camcc@ad00000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1039 compatible = "qcom,cam_cc-sdm670", "syscon";
1040 reg = <0xad00000 0x10000>;
1041 reg-names = "cc_base";
1042 vdd_cx-supply = <&pm660l_s3_level>;
1043 vdd_mx-supply = <&pm660l_s1_level>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1044 #clock-cells = <1>;
1045 #reset-cells = <1>;
Alok Pandey499587b2018-02-08 22:14:59 +0530[diff] [blame]1046 qcom,cam_cc_csi0phytimer_clk_src-opp-handle = <&cam_csiphy0>;
1047 qcom,cam_cc_csi1phytimer_clk_src-opp-handle = <&cam_csiphy1>;
1048 qcom,cam_cc_csi2phytimer_clk_src-opp-handle = <&cam_csiphy2>;
1049 qcom,cam_cc_cci_clk_src-opp-handle = <&cam_cci>;
1050 qcom,cam_cc_ife_0_csid_clk_src-opp-handle = <&cam_csid0>;
1051 qcom,cam_cc_ife_0_clk_src-opp-handle = <&cam_vfe0>;
1052 qcom,cam_cc_ife_1_csid_clk_src-opp-handle = <&cam_csid1>;
1053 qcom,cam_cc_ife_1_clk_src-opp-handle = <&cam_vfe1>;
1054 qcom,cam_cc_ife_lite_csid_clk_src-opp-handle = <&cam_csid_lite>;
1055 qcom,cam_cc_ife_lite_clk_src-opp-handle = <&cam_vfe_lite>;
1056 qcom,cam_cc_icp_clk_src-opp-handle = <&cam_a5>;
1057 qcom,cam_cc_ipe_0_clk_src-opp-handle = <&cam_ipe0>;
1058 qcom,cam_cc_ipe_1_clk_src-opp-handle = <&cam_ipe1>;
1059 qcom,cam_cc_bps_clk_src-opp-handle = <&cam_bps>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1060 };
1061
1062 clock_dispcc: qcom,dispcc@af00000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1063 compatible = "qcom,dispcc-sdm670", "syscon";
1064 reg = <0xaf00000 0x10000>;
1065 reg-names = "cc_base";
1066 vdd_cx-supply = <&pm660l_s3_level>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1067 #clock-cells = <1>;
1068 #reset-cells = <1>;
1069 };
1070
1071 clock_gpucc: qcom,gpucc@5090000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1072 compatible = "qcom,gpucc-sdm670", "syscon";
1073 reg = <0x5090000 0x9000>;
1074 reg-names = "cc_base";
1075 vdd_cx-supply = <&pm660l_s3_level>;
1076 vdd_mx-supply = <&pm660l_s1_level>;
Odelu Kukatladc7ac7d2017-09-27 11:05:53 +0530[diff] [blame]1077 qcom,gpu_cc_gmu_clk_src-opp-handle = <&gmu>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1078 #clock-cells = <1>;
1079 #reset-cells = <1>;
1080 };
1081
1082 clock_gfx: qcom,gfxcc@5090000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1083 compatible = "qcom,gfxcc-sdm670";
1084 reg = <0x5090000 0x9000>;
1085 reg-names = "cc_base";
1086 vdd_gfx-supply = <&pm660l_s2_level>;
Odelu Kukatladc7ac7d2017-09-27 11:05:53 +0530[diff] [blame]1087 qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1088 #clock-cells = <1>;
1089 #reset-cells = <1>;
1090 };
1091
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1092 cpucc_debug: syscon@17970018 {
1093 compatible = "syscon";
1094 reg = <0x17970018 0x4>;
1095 };
1096
1097 clock_debug: qcom,cc-debug {
1098 compatible = "qcom,debugcc-sdm845";
1099 qcom,cc-count = <5>;
1100 qcom,gcc = <&clock_gcc>;
1101 qcom,videocc = <&clock_videocc>;
1102 qcom,camcc = <&clock_camcc>;
1103 qcom,dispcc = <&clock_dispcc>;
1104 qcom,gpucc = <&clock_gpucc>;
1105 qcom,cpucc = <&cpucc_debug>;
1106 clock-names = "xo_clk_src";
1107 clocks = <&clock_rpmh RPMH_CXO_CLK>;
1108 #clock-cells = <1>;
1109 };
1110
Odelu Kukatlaffce30a2017-09-23 17:20:48 +0530[diff] [blame]1111 clock_cpucc: qcom,cpucc@0x17d41000 {
1112 compatible = "qcom,clk-cpu-osm-sdm670";
1113 reg = <0x17d41000 0x1400>,
1114 <0x17d43000 0x1400>,
David Collins1e048402017-11-29 15:43:09 -0800[diff] [blame]1115 <0x17d45800 0x1400>;
1116 reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base";
Deepak Katragadda02617bd2017-11-10 16:03:43 -0800[diff] [blame]1117 vdd_l3_mx_ao-supply = <&pm660l_s1_level_ao>;
1118 vdd_pwrcl_mx_ao-supply = <&pm660l_s1_level_ao>;
Odelu Kukatlaffce30a2017-09-23 17:20:48 +0530[diff] [blame]1119
Odelu Kukatla86c179e2017-12-12 19:10:23 +0530[diff] [blame]1120 qcom,mx-turbo-freq = <1440000000 1708000000 3300000001>;
Santosh Mardi7790a432018-01-09 23:01:56 +0530[diff] [blame]1121 l3-devs = <&l3_cpu0 &l3_cpu6 &l3_cdsp>;
Odelu Kukatlaffce30a2017-09-23 17:20:48 +0530[diff] [blame]1122
1123 clock-names = "xo_ao";
1124 clocks = <&clock_rpmh RPMH_CXO_CLK_A>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1125 #clock-cells = <1>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1126 };
1127
Odelu Kukatla6f3ffa12017-08-10 12:31:06 +0530[diff] [blame]1128 clock_aop: qcom,aopclk {
Odelu Kukatla80f617f2017-09-15 19:30:25 +0530[diff] [blame]1129 compatible = "qcom,aop-qmp-clk-v1";
Odelu Kukatla6f3ffa12017-08-10 12:31:06 +0530[diff] [blame]1130 #clock-cells = <1>;
1131 mboxes = <&qmp_aop 0>;
1132 mbox-names = "qdss_clk";
1133 };
1134
Shrey Vijay6b6b3a52017-06-21 15:06:03 +0530[diff] [blame]1135 slim_aud: slim@62dc0000 {
1136 cell-index = <1>;
1137 compatible = "qcom,slim-ngd";
1138 reg = <0x62dc0000 0x2c000>,
1139 <0x62d84000 0x2a000>;
1140 reg-names = "slimbus_physical", "slimbus_bam_physical";
1141 interrupts = <0 163 0>, <0 164 0>;
1142 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
1143 qcom,apps-ch-pipes = <0x780000>;
1144 qcom,ea-pc = <0x290>;
1145 status = "disabled";
Dilip Kota0f5974d2017-08-17 15:13:08 +0530[diff] [blame]1146 qcom,iommu-s1-bypass;
1147
1148 iommu_slim_aud_ctrl_cb: qcom,iommu_slim_ctrl_cb {
1149 compatible = "qcom,iommu-slim-ctrl-cb";
1150 iommus = <&apps_smmu 0x1826 0x0>,
1151 <&apps_smmu 0x182d 0x0>,
1152 <&apps_smmu 0x182e 0x1>,
1153 <&apps_smmu 0x1830 0x1>;
1154 };
1155
Shrey Vijay6b6b3a52017-06-21 15:06:03 +0530[diff] [blame]1156 };
1157
1158 slim_qca: slim@62e40000 {
1159 cell-index = <3>;
1160 compatible = "qcom,slim-ngd";
1161 reg = <0x62e40000 0x2c000>,
1162 <0x62e04000 0x20000>;
1163 reg-names = "slimbus_physical", "slimbus_bam_physical";
1164 interrupts = <0 291 0>, <0 292 0>;
1165 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
Rupesh Tatiya7615f682017-10-11 12:30:20 +0530[diff] [blame]1166 status = "ok";
Dilip Kota0f5974d2017-08-17 15:13:08 +0530[diff] [blame]1167 qcom,iommu-s1-bypass;
1168
1169 iommu_slim_qca_ctrl_cb: qcom,iommu_slim_ctrl_cb {
1170 compatible = "qcom,iommu-slim-ctrl-cb";
1171 iommus = <&apps_smmu 0x1833 0x0>;
1172 };
1173
Rupesh Tatiya7615f682017-10-11 12:30:20 +0530[diff] [blame]1174 /* Slimbus Slave DT for WCN3990 */
1175 btfmslim_codec: wcn3990 {
1176 compatible = "qcom,btfmslim_slave";
1177 elemental-addr = [00 01 20 02 17 02];
1178 qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
1179 qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];
1180 };
Shrey Vijay6b6b3a52017-06-21 15:06:03 +0530[diff] [blame]1181 };
1182
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1183 wdog: qcom,wdt@17980000{
1184 compatible = "qcom,msm-watchdog";
1185 reg = <0x17980000 0x1000>;
1186 reg-names = "wdt-base";
Lingutla Chandrasekhar9fb9ba92017-10-08 21:59:19 +0530[diff] [blame]1187 interrupts = <0 0 0>, <0 1 0>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1188 qcom,bark-time = <11000>;
Neeraj Upadhyaydbc184d2017-12-07 16:05:39 +0530[diff] [blame]1189 qcom,pet-time = <9360>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1190 qcom,ipi-ping;
1191 qcom,wakeup-enable;
1192 };
1193
1194 qcom,msm-rtb {
1195 compatible = "qcom,msm-rtb";
1196 qcom,rtb-size = <0x100000>;
1197 };
1198
Lingutla Chandrasekhar4d78d722017-11-10 16:03:44 +0530[diff] [blame]1199 qcom,mpm2-sleep-counter@c221000 {
1200 compatible = "qcom,mpm2-sleep-counter";
1201 reg = <0x0c221000 0x1000>;
1202 clock-frequency = <32768>;
1203 };
1204
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1205 qcom,msm-imem@146bf000 {
1206 compatible = "qcom,msm-imem";
1207 reg = <0x146bf000 0x1000>;
1208 ranges = <0x0 0x146bf000 0x1000>;
1209 #address-cells = <1>;
1210 #size-cells = <1>;
1211
1212 mem_dump_table@10 {
1213 compatible = "qcom,msm-imem-mem_dump_table";
1214 reg = <0x10 8>;
1215 };
1216
Lingutla Chandrasekharfa5c13f2017-09-25 11:01:58 +0530[diff] [blame]1217 dload_type@1c {
1218 compatible = "qcom,msm-imem-dload-type";
1219 reg = <0x1c 0x4>;
1220 };
1221
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1222 restart_reason@65c {
1223 compatible = "qcom,msm-imem-restart_reason";
1224 reg = <0x65c 4>;
1225 };
1226
1227 pil@94c {
1228 compatible = "qcom,msm-imem-pil";
1229 reg = <0x94c 200>;
1230 };
1231
1232 kaslr_offset@6d0 {
1233 compatible = "qcom,msm-imem-kaslr_offset";
1234 reg = <0x6d0 12>;
1235 };
Lingutla Chandrasekhar3c51f0b2017-09-12 14:21:21 +0530[diff] [blame]1236
1237 boot_stats@6b0 {
1238 compatible = "qcom,msm-imem-boot_stats";
1239 reg = <0x6b0 0x20>;
1240 };
1241
1242 diag_dload@c8 {
1243 compatible = "qcom,msm-imem-diag-dload";
1244 reg = <0xc8 0xc8>;
1245 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1246 };
1247
Rama Krishna Phani A2acd96a2017-07-03 17:12:46 +0530[diff] [blame]1248 gpi_dma0: qcom,gpi-dma@0x800000 {
Jishnu Prakashfb619282017-11-06 11:07:53 +0530[diff] [blame]1249 #dma-cells = <5>;
Rama Krishna Phani A2acd96a2017-07-03 17:12:46 +0530[diff] [blame]1250 compatible = "qcom,gpi-dma";
1251 reg = <0x800000 0x60000>;
1252 reg-names = "gpi-top";
1253 interrupts = <0 244 0>, <0 245 0>, <0 246 0>, <0 247 0>,
1254 <0 248 0>, <0 249 0>, <0 250 0>, <0 251 0>,
1255 <0 252 0>, <0 253 0>, <0 254 0>, <0 255 0>,
1256 <0 256 0>;
1257 qcom,max-num-gpii = <13>;
1258 qcom,gpii-mask = <0xfa>;
1259 qcom,ev-factor = <2>;
1260 iommus = <&apps_smmu 0x0016 0x0>;
Jishnu Prakash71f42792017-11-02 16:04:21 +0530[diff] [blame]1261 qcom,smmu-cfg = <0x1>;
1262 qcom,iova-range = <0x0 0x100000 0x0 0x100000>;
Rama Krishna Phani A2acd96a2017-07-03 17:12:46 +0530[diff] [blame]1263 status = "ok";
1264 };
1265
1266 gpi_dma1: qcom,gpi-dma@0xa00000 {
Jishnu Prakashfb619282017-11-06 11:07:53 +0530[diff] [blame]1267 #dma-cells = <5>;
Rama Krishna Phani A2acd96a2017-07-03 17:12:46 +0530[diff] [blame]1268 compatible = "qcom,gpi-dma";
1269 reg = <0xa00000 0x60000>;
1270 reg-names = "gpi-top";
1271 interrupts = <0 279 0>, <0 280 0>, <0 281 0>, <0 282 0>,
1272 <0 283 0>, <0 284 0>, <0 293 0>, <0 294 0>,
1273 <0 295 0>, <0 296 0>, <0 297 0>, <0 298 0>,
1274 <0 299 0>;
1275 qcom,max-num-gpii = <13>;
1276 qcom,gpii-mask = <0xfa>;
1277 qcom,ev-factor = <2>;
Jishnu Prakash71f42792017-11-02 16:04:21 +0530[diff] [blame]1278 qcom,smmu-cfg = <0x1>;
1279 qcom,iova-range = <0x0 0x100000 0x0 0x100000>;
Rama Krishna Phani A2acd96a2017-07-03 17:12:46 +0530[diff] [blame]1280 iommus = <&apps_smmu 0x06d6 0x0>;
1281 status = "ok";
1282 };
1283
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1284 cpuss_dump {
1285 compatible = "qcom,cpuss-dump";
1286 qcom,l1_i_cache0 {
1287 qcom,dump-node = <&L1_I_0>;
1288 qcom,dump-id = <0x60>;
1289 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1290 qcom,l1_i_cache100 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1291 qcom,dump-node = <&L1_I_100>;
1292 qcom,dump-id = <0x61>;
1293 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1294 qcom,l1_i_cache200 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1295 qcom,dump-node = <&L1_I_200>;
1296 qcom,dump-id = <0x62>;
1297 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1298 qcom,l1_i_cache300 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1299 qcom,dump-node = <&L1_I_300>;
1300 qcom,dump-id = <0x63>;
1301 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1302 qcom,l1_i_cache400 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1303 qcom,dump-node = <&L1_I_400>;
1304 qcom,dump-id = <0x64>;
1305 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1306 qcom,l1_i_cache500 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1307 qcom,dump-node = <&L1_I_500>;
1308 qcom,dump-id = <0x65>;
1309 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1310 qcom,l1_i_cache600 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1311 qcom,dump-node = <&L1_I_600>;
1312 qcom,dump-id = <0x66>;
1313 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1314 qcom,l1_i_cache700 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1315 qcom,dump-node = <&L1_I_700>;
1316 qcom,dump-id = <0x67>;
1317 };
1318 qcom,l1_d_cache0 {
1319 qcom,dump-node = <&L1_D_0>;
1320 qcom,dump-id = <0x80>;
1321 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1322 qcom,l1_d_cache100 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1323 qcom,dump-node = <&L1_D_100>;
1324 qcom,dump-id = <0x81>;
1325 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1326 qcom,l1_d_cache200 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1327 qcom,dump-node = <&L1_D_200>;
1328 qcom,dump-id = <0x82>;
1329 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1330 qcom,l1_d_cache300 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1331 qcom,dump-node = <&L1_D_300>;
1332 qcom,dump-id = <0x83>;
1333 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1334 qcom,l1_d_cache400 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1335 qcom,dump-node = <&L1_D_400>;
1336 qcom,dump-id = <0x84>;
1337 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1338 qcom,l1_d_cache500 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1339 qcom,dump-node = <&L1_D_500>;
1340 qcom,dump-id = <0x85>;
1341 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1342 qcom,l1_d_cache600 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1343 qcom,dump-node = <&L1_D_600>;
1344 qcom,dump-id = <0x86>;
1345 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1346 qcom,l1_d_cache700 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1347 qcom,dump-node = <&L1_D_700>;
1348 qcom,dump-id = <0x87>;
1349 };
Lingutla Chandrasekharee4f1872017-06-07 13:50:53 +0530[diff] [blame]1350 qcom,llcc1_d_cache {
1351 qcom,dump-node = <&LLCC_1>;
1352 qcom,dump-id = <0x140>;
1353 };
1354 qcom,llcc2_d_cache {
1355 qcom,dump-node = <&LLCC_2>;
1356 qcom,dump-id = <0x141>;
1357 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1358 qcom,l1_tlb_dump0 {
1359 qcom,dump-node = <&L1_TLB_0>;
1360 qcom,dump-id = <0x20>;
1361 };
1362 qcom,l1_tlb_dump100 {
1363 qcom,dump-node = <&L1_TLB_100>;
1364 qcom,dump-id = <0x21>;
1365 };
1366 qcom,l1_tlb_dump200 {
1367 qcom,dump-node = <&L1_TLB_200>;
1368 qcom,dump-id = <0x22>;
1369 };
1370 qcom,l1_tlb_dump300 {
1371 qcom,dump-node = <&L1_TLB_300>;
1372 qcom,dump-id = <0x23>;
1373 };
1374 qcom,l1_tlb_dump400 {
1375 qcom,dump-node = <&L1_TLB_400>;
1376 qcom,dump-id = <0x24>;
1377 };
1378 qcom,l1_tlb_dump500 {
1379 qcom,dump-node = <&L1_TLB_500>;
1380 qcom,dump-id = <0x25>;
1381 };
1382 qcom,l1_tlb_dump600 {
1383 qcom,dump-node = <&L1_TLB_600>;
1384 qcom,dump-id = <0x26>;
1385 };
1386 qcom,l1_tlb_dump700 {
1387 qcom,dump-node = <&L1_TLB_700>;
1388 qcom,dump-id = <0x27>;
1389 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1390 };
1391
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1392 mem_dump {
1393 compatible = "qcom,mem-dump";
1394 memory-region = <&dump_mem>;
1395
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1396 rpmh {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1397 qcom,dump-size = <0x2000000>;
1398 qcom,dump-id = <0xec>;
1399 };
1400
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1401 rpm_sw {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1402 qcom,dump-size = <0x28000>;
1403 qcom,dump-id = <0xea>;
1404 };
1405
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1406 pmic {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1407 qcom,dump-size = <0x10000>;
1408 qcom,dump-id = <0xe4>;
1409 };
1410
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1411 tmc_etf {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1412 qcom,dump-size = <0x10000>;
1413 qcom,dump-id = <0xf0>;
1414 };
1415
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1416 tmc_etfswao {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1417 qcom,dump-size = <0x8400>;
1418 qcom,dump-id = <0xf1>;
1419 };
1420
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1421 tmc_etr_reg {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1422 qcom,dump-size = <0x1000>;
1423 qcom,dump-id = <0x100>;
1424 };
1425
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1426 tmc_etf_reg {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1427 qcom,dump-size = <0x1000>;
1428 qcom,dump-id = <0x101>;
1429 };
1430
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1431 etfswao_reg {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1432 qcom,dump-size = <0x1000>;
1433 qcom,dump-id = <0x102>;
1434 };
1435
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1436 misc_data {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1437 qcom,dump-size = <0x1000>;
1438 qcom,dump-id = <0xe8>;
1439 };
1440
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1441 power_regs {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1442 qcom,dump-size = <0x100000>;
1443 qcom,dump-id = <0xed>;
1444 };
1445 };
1446
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1447 kryo3xx-erp {
1448 compatible = "arm,arm64-kryo3xx-cpu-erp";
1449 interrupts = <1 6 4>,
1450 <1 7 4>,
1451 <0 34 4>,
1452 <0 35 4>;
1453
1454 interrupt-names = "l1-l2-faultirq",
1455 "l1-l2-errirq",
1456 "l3-scu-errirq",
1457 "l3-scu-faultirq";
1458 };
1459
Dhoat Harpala24cb2c2017-06-06 20:39:54 +0530[diff] [blame]1460 qcom,ipc-spinlock@1f40000 {
1461 compatible = "qcom,ipc-spinlock-sfpb";
1462 reg = <0x1f40000 0x8000>;
1463 qcom,num-locks = <8>;
1464 };
1465
Dhoat Harpaldd9bfaf2017-06-06 20:43:16 +0530[diff] [blame]1466 qcom,smem@86000000 {
1467 compatible = "qcom,smem";
1468 reg = <0x86000000 0x200000>,
1469 <0x17911008 0x4>,
1470 <0x778000 0x7000>,
1471 <0x1fd4000 0x8>;
1472 reg-names = "smem", "irq-reg-base", "aux-mem1",
1473 "smem_targ_info_reg";
1474 qcom,mpu-enabled;
1475 };
1476
Dhoat Harpalebc9e562017-07-30 20:53:03 +0530[diff] [blame]1477 qmp_aop: qcom,qmp-aop@c300000 {
Dhoat Harpal5f909ef2017-06-09 21:18:00 +0530[diff] [blame]1478 compatible = "qcom,qmp-mbox";
1479 label = "aop";
1480 reg = <0xc300000 0x100000>,
1481 <0x1799000c 0x4>;
1482 reg-names = "msgram", "irq-reg-base";
1483 qcom,irq-mask = <0x1>;
1484 interrupts = <0 389 1>;
Dhoat Harpalebc9e562017-07-30 20:53:03 +0530[diff] [blame]1485 priority = <0>;
Dhoat Harpal5f909ef2017-06-09 21:18:00 +0530[diff] [blame]1486 mbox-desc-offset = <0x0>;
1487 #mbox-cells = <1>;
1488 };
1489
Dhoat Harpal466ffcc2017-06-06 20:54:51 +0530[diff] [blame]1490 qcom,glink-smem-native-xprt-modem@86000000 {
1491 compatible = "qcom,glink-smem-native-xprt";
1492 reg = <0x86000000 0x200000>,
1493 <0x1799000c 0x4>;
1494 reg-names = "smem", "irq-reg-base";
1495 qcom,irq-mask = <0x1000>;
1496 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
1497 label = "mpss";
1498 };
1499
1500 qcom,glink-smem-native-xprt-adsp@86000000 {
1501 compatible = "qcom,glink-smem-native-xprt";
1502 reg = <0x86000000 0x200000>,
1503 <0x1799000c 0x4>;
1504 reg-names = "smem", "irq-reg-base";
Dhoat Harpal3adebbe2017-07-06 15:59:13 +0530[diff] [blame]1505 qcom,irq-mask = <0x1000000>;
1506 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
Dhoat Harpal466ffcc2017-06-06 20:54:51 +0530[diff] [blame]1507 label = "lpass";
1508 qcom,qos-config = <&glink_qos_adsp>;
1509 qcom,ramp-time = <0xaf>;
1510 };
1511
1512 glink_qos_adsp: qcom,glink-qos-config-adsp {
1513 compatible = "qcom,glink-qos-config";
1514 qcom,flow-info = <0x3c 0x0>,
1515 <0x3c 0x0>,
1516 <0x3c 0x0>,
1517 <0x3c 0x0>;
1518 qcom,mtu-size = <0x800>;
1519 qcom,tput-stats-cycle = <0xa>;
1520 };
1521
1522 glink_spi_xprt_wdsp: qcom,glink-spi-xprt-wdsp {
1523 compatible = "qcom,glink-spi-xprt";
1524 label = "wdsp";
1525 qcom,remote-fifo-config = <&glink_fifo_wdsp>;
1526 qcom,qos-config = <&glink_qos_wdsp>;
1527 qcom,ramp-time = <0x10>,
1528 <0x20>,
1529 <0x30>,
1530 <0x40>;
1531 };
1532
1533 glink_fifo_wdsp: qcom,glink-fifo-config-wdsp {
1534 compatible = "qcom,glink-fifo-config";
1535 qcom,out-read-idx-reg = <0x12000>;
1536 qcom,out-write-idx-reg = <0x12004>;
1537 qcom,in-read-idx-reg = <0x1200C>;
1538 qcom,in-write-idx-reg = <0x12010>;
1539 };
1540
1541 glink_qos_wdsp: qcom,glink-qos-config-wdsp {
1542 compatible = "qcom,glink-qos-config";
1543 qcom,flow-info = <0x80 0x0>,
1544 <0x70 0x1>,
1545 <0x60 0x2>,
1546 <0x50 0x3>;
1547 qcom,mtu-size = <0x800>;
1548 qcom,tput-stats-cycle = <0xa>;
1549 };
1550
1551 qcom,glink-smem-native-xprt-cdsp@86000000 {
1552 compatible = "qcom,glink-smem-native-xprt";
1553 reg = <0x86000000 0x200000>,
1554 <0x1799000c 0x4>;
1555 reg-names = "smem", "irq-reg-base";
1556 qcom,irq-mask = <0x10>;
1557 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
1558 label = "cdsp";
1559 };
1560
Dhoat Harpal9cb73cc2017-06-06 20:58:14 +0530[diff] [blame]1561 glink_mpss: qcom,glink-ssr-modem {
1562 compatible = "qcom,glink_ssr";
1563 label = "modem";
1564 qcom,edge = "mpss";
1565 qcom,notify-edges = <&glink_lpass>, <&glink_cdsp>;
1566 qcom,xprt = "smem";
1567 };
1568
1569 glink_lpass: qcom,glink-ssr-adsp {
1570 compatible = "qcom,glink_ssr";
1571 label = "adsp";
1572 qcom,edge = "lpass";
1573 qcom,notify-edges = <&glink_mpss>, <&glink_cdsp>;
1574 qcom,xprt = "smem";
1575 };
1576
1577 glink_cdsp: qcom,glink-ssr-cdsp {
1578 compatible = "qcom,glink_ssr";
1579 label = "cdsp";
1580 qcom,edge = "cdsp";
1581 qcom,notify-edges = <&glink_mpss>, <&glink_lpass>;
1582 qcom,xprt = "smem";
1583 };
1584
Dhoat Harpal22dafa92017-06-06 21:03:34 +0530[diff] [blame]1585 qcom,ipc_router {
1586 compatible = "qcom,ipc_router";
1587 qcom,node-id = <1>;
1588 };
1589
1590 qcom,ipc_router_modem_xprt {
1591 compatible = "qcom,ipc_router_glink_xprt";
1592 qcom,ch-name = "IPCRTR";
1593 qcom,xprt-remote = "mpss";
1594 qcom,glink-xprt = "smem";
1595 qcom,xprt-linkid = <1>;
1596 qcom,xprt-version = <1>;
1597 qcom,fragmented-data;
1598 };
1599
1600 qcom,ipc_router_q6_xprt {
1601 compatible = "qcom,ipc_router_glink_xprt";
1602 qcom,ch-name = "IPCRTR";
1603 qcom,xprt-remote = "lpass";
1604 qcom,glink-xprt = "smem";
1605 qcom,xprt-linkid = <1>;
1606 qcom,xprt-version = <1>;
1607 qcom,fragmented-data;
1608 };
1609
1610 qcom,ipc_router_cdsp_xprt {
1611 compatible = "qcom,ipc_router_glink_xprt";
1612 qcom,ch-name = "IPCRTR";
1613 qcom,xprt-remote = "cdsp";
1614 qcom,glink-xprt = "smem";
1615 qcom,xprt-linkid = <1>;
1616 qcom,xprt-version = <1>;
1617 qcom,fragmented-data;
1618 };
1619
Dhoat Harpal11d34482017-06-06 21:00:14 +0530[diff] [blame]1620 qcom,glink_pkt {
1621 compatible = "qcom,glinkpkt";
1622
1623 qcom,glinkpkt-at-mdm0 {
1624 qcom,glinkpkt-transport = "smem";
1625 qcom,glinkpkt-edge = "mpss";
1626 qcom,glinkpkt-ch-name = "DS";
1627 qcom,glinkpkt-dev-name = "at_mdm0";
1628 };
1629
1630 qcom,glinkpkt-loopback_cntl {
1631 qcom,glinkpkt-transport = "lloop";
1632 qcom,glinkpkt-edge = "local";
1633 qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT";
1634 qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl";
1635 };
1636
1637 qcom,glinkpkt-loopback_data {
1638 qcom,glinkpkt-transport = "lloop";
1639 qcom,glinkpkt-edge = "local";
1640 qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT";
1641 qcom,glinkpkt-dev-name = "glink_pkt_loopback";
1642 };
1643
1644 qcom,glinkpkt-apr-apps2 {
1645 qcom,glinkpkt-transport = "smem";
1646 qcom,glinkpkt-edge = "adsp";
1647 qcom,glinkpkt-ch-name = "apr_apps2";
1648 qcom,glinkpkt-dev-name = "apr_apps2";
1649 };
1650
1651 qcom,glinkpkt-data40-cntl {
1652 qcom,glinkpkt-transport = "smem";
1653 qcom,glinkpkt-edge = "mpss";
1654 qcom,glinkpkt-ch-name = "DATA40_CNTL";
1655 qcom,glinkpkt-dev-name = "smdcntl8";
1656 };
1657
1658 qcom,glinkpkt-data1 {
1659 qcom,glinkpkt-transport = "smem";
1660 qcom,glinkpkt-edge = "mpss";
1661 qcom,glinkpkt-ch-name = "DATA1";
1662 qcom,glinkpkt-dev-name = "smd7";
1663 };
1664
1665 qcom,glinkpkt-data4 {
1666 qcom,glinkpkt-transport = "smem";
1667 qcom,glinkpkt-edge = "mpss";
1668 qcom,glinkpkt-ch-name = "DATA4";
1669 qcom,glinkpkt-dev-name = "smd8";
1670 };
1671
1672 qcom,glinkpkt-data11 {
1673 qcom,glinkpkt-transport = "smem";
1674 qcom,glinkpkt-edge = "mpss";
1675 qcom,glinkpkt-ch-name = "DATA11";
1676 qcom,glinkpkt-dev-name = "smd11";
1677 };
1678 };
1679
Gaurav Kohlid1131902018-02-21 13:21:25 +0530[diff] [blame]1680 qcom,chd_silver {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1681 compatible = "qcom,core-hang-detect";
1682 label = "silver";
1683 qcom,threshold-arr = <0x17e00058 0x17e10058 0x17e20058
1684 0x17e30058 0x17e40058 0x17e50058>;
1685 qcom,config-arr = <0x17e00060 0x17e10060 0x17e20060
1686 0x17e30060 0x17e40060 0x17e50060>;
1687 };
1688
1689 qcom,chd_gold {
1690 compatible = "qcom,core-hang-detect";
1691 label = "gold";
1692 qcom,threshold-arr = <0x17e60058 0x17e70058>;
1693 qcom,config-arr = <0x17e60060 0x17e70060>;
1694 };
1695
1696 qcom,ghd {
1697 compatible = "qcom,gladiator-hang-detect-v2";
1698 qcom,threshold-arr = <0x1799041c 0x17990420>;
1699 qcom,config-reg = <0x17990434>;
1700 };
1701
1702 qcom,msm-gladiator-v3@17900000 {
1703 compatible = "qcom,msm-gladiator-v3";
1704 reg = <0x17900000 0xd080>;
1705 reg-names = "gladiator_base";
1706 interrupts = <0 17 0>;
1707 };
1708
Lingutla Chandrasekhar88f9e7b2017-09-15 18:29:25 +0530[diff] [blame]1709 eud: qcom,msm-eud@88e0000 {
1710 compatible = "qcom,msm-eud";
1711 interrupt-names = "eud_irq";
1712 interrupts = <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>;
1713 reg = <0x88e0000 0x2000>;
1714 reg-names = "eud_base";
Lingutla Chandrasekhar5422daf2017-10-26 11:27:32 +0530[diff] [blame]1715 clocks = <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
1716 clock-names = "cfg_ahb_clk";
Lingutla Chandrasekhar88f9e7b2017-09-15 18:29:25 +0530[diff] [blame]1717 };
1718
Lingutla Chandrasekharee4f1872017-06-07 13:50:53 +0530[diff] [blame]1719 qcom,llcc@1100000 {
1720 compatible = "qcom,llcc-core", "syscon", "simple-mfd";
1721 reg = <0x1100000 0x250000>;
1722 reg-names = "llcc_base";
1723 qcom,llcc-banks-off = <0x0 0x80000 >;
1724 qcom,llcc-broadcast-off = <0x200000>;
1725
1726 llcc: qcom,sdm670-llcc {
1727 compatible = "qcom,sdm670-llcc";
1728 #cache-cells = <1>;
1729 max-slices = <32>;
1730 qcom,dump-size = <0x80000>;
1731 };
1732
Sankaran Nampoothiri0c5dac02017-11-06 11:53:52 +0530[diff] [blame]1733 qcom,llcc-perfmon {
1734 compatible = "qcom,llcc-perfmon";
1735 };
1736
Lingutla Chandrasekharee4f1872017-06-07 13:50:53 +0530[diff] [blame]1737 qcom,llcc-erp {
1738 compatible = "qcom,llcc-erp";
1739 interrupt-names = "ecc_irq";
1740 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1741 };
1742
1743 qcom,llcc-amon {
1744 compatible = "qcom,llcc-amon";
1745 };
1746
1747 LLCC_1: llcc_1_dcache {
1748 qcom,dump-size = <0xd8000>;
1749 };
1750
1751 LLCC_2: llcc_2_dcache {
1752 qcom,dump-size = <0xd8000>;
1753 };
1754 };
1755
Maulik Shah210773d2017-06-15 09:49:12 +0530[diff] [blame]1756 cmd_db: qcom,cmd-db@c3f000c {
1757 compatible = "qcom,cmd-db";
1758 reg = <0xc3f000c 0x8>;
1759 };
1760
Maulik Shahc77d1d22017-06-15 14:04:50 +0530[diff] [blame]1761 apps_rsc: mailbox@179e0000 {
1762 compatible = "qcom,tcs-drv";
1763 label = "apps_rsc";
1764 reg = <0x179e0000 0x100>, <0x179e0d00 0x3000>;
1765 interrupts = <0 5 0>;
1766 #mbox-cells = <1>;
1767 qcom,drv-id = <2>;
1768 qcom,tcs-config = <ACTIVE_TCS 2>,
1769 <SLEEP_TCS 3>,
1770 <WAKE_TCS 3>,
1771 <CONTROL_TCS 1>;
1772 };
1773
Maulik Shahda3941f2017-06-15 09:41:38 +0530[diff] [blame]1774 disp_rsc: mailbox@af20000 {
1775 compatible = "qcom,tcs-drv";
1776 label = "display_rsc";
1777 reg = <0xaf20000 0x100>, <0xaf21c00 0x3000>;
1778 interrupts = <0 129 0>;
1779 #mbox-cells = <1>;
1780 qcom,drv-id = <0>;
1781 qcom,tcs-config = <SLEEP_TCS 1>,
1782 <WAKE_TCS 1>,
1783 <ACTIVE_TCS 0>,
1784 <CONTROL_TCS 1>;
1785 };
1786
Maulik Shah0dd203f2017-06-15 09:44:59 +0530[diff] [blame]1787 system_pm {
1788 compatible = "qcom,system-pm";
1789 mboxes = <&apps_rsc 0>;
1790 };
1791
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1792 dcc: dcc_v2@10a2000 {
1793 compatible = "qcom,dcc_v2";
1794 reg = <0x10a2000 0x1000>,
1795 <0x10ae000 0x2000>;
1796 reg-names = "dcc-base", "dcc-ram-base";
Saranya Chidurac0a161c2017-08-28 13:06:10 +0530[diff] [blame]1797
1798 dcc-ram-offset = <0x6000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1799 };
1800
Tirupathi Reddy9ae4c892017-06-09 12:30:31 +0530[diff] [blame]1801 spmi_bus: qcom,spmi@c440000 {
1802 compatible = "qcom,spmi-pmic-arb";
1803 reg = <0xc440000 0x1100>,
1804 <0xc600000 0x2000000>,
1805 <0xe600000 0x100000>,
1806 <0xe700000 0xa0000>,
1807 <0xc40a000 0x26000>;
1808 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1809 interrupt-names = "periph_irq";
1810 interrupts = <GIC_SPI 481 IRQ_TYPE_NONE>;
1811 qcom,ee = <0>;
1812 qcom,channel = <0>;
1813 #address-cells = <2>;
1814 #size-cells = <0>;
1815 interrupt-controller;
1816 #interrupt-cells = <4>;
1817 cell-index = <0>;
1818 };
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1819
Neeraj Soni3c041f12018-01-19 16:45:44 +0530[diff] [blame]1820 ufs_ice: ufsice@1d90000 {
1821 compatible = "qcom,ice";
1822 reg = <0x1d90000 0x8000>;
1823 qcom,enable-ice-clk;
1824 clock-names = "ufs_core_clk", "bus_clk",
1825 "iface_clk", "ice_core_clk";
1826 clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>,
1827 <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,
1828 <&clock_gcc GCC_UFS_PHY_AHB_CLK>,
1829 <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1830 qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;
1831 vdd-hba-supply = <&ufs_phy_gdsc>;
1832 qcom,msm-bus,name = "ufs_ice_noc";
1833 qcom,msm-bus,num-cases = <2>;
1834 qcom,msm-bus,num-paths = <1>;
1835 qcom,msm-bus,vectors-KBps =
1836 <1 650 0 0>, /* No vote */
1837 <1 650 1000 0>; /* Max. bandwidth */
1838 qcom,bus-vector-names = "MIN",
1839 "MAX";
1840 qcom,instance-type = "ufs";
1841 };
1842
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1843 ufsphy_mem: ufsphy_mem@1d87000 {
1844 reg = <0x1d87000 0xe00>; /* PHY regs */
1845 reg-names = "phy_mem";
1846 #phy-cells = <0>;
1847
1848 lanes-per-direction = <1>;
1849
1850 clock-names = "ref_clk_src",
1851 "ref_clk",
1852 "ref_aux_clk";
1853 clocks = <&clock_rpmh RPMH_CXO_CLK>,
1854 <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,
1855 <&clock_gcc GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK>;
1856
1857 status = "disabled";
1858 };
1859
1860 ufshc_mem: ufshc@1d84000 {
1861 compatible = "qcom,ufshc";
1862 reg = <0x1d84000 0x3000>;
1863 interrupts = <0 265 0>;
1864 phys = <&ufsphy_mem>;
1865 phy-names = "ufsphy";
Neeraj Soni3c041f12018-01-19 16:45:44 +0530[diff] [blame]1866 ufs-qcom-crypto = <&ufs_ice>;
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1867
1868 lanes-per-direction = <1>;
1869 dev-ref-clk-freq = <0>; /* 19.2 MHz */
1870
1871 clock-names =
1872 "core_clk",
1873 "bus_aggr_clk",
1874 "iface_clk",
1875 "core_clk_unipro",
1876 "core_clk_ice",
1877 "ref_clk",
1878 "tx_lane0_sync_clk",
1879 "rx_lane0_sync_clk";
1880 clocks =
1881 <&clock_gcc GCC_UFS_PHY_AXI_HW_CTL_CLK>,
1882 <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK>,
1883 <&clock_gcc GCC_UFS_PHY_AHB_CLK>,
1884 <&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK>,
1885 <&clock_gcc GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK>,
1886 <&clock_rpmh RPMH_CXO_CLK>,
1887 <&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1888 <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
1889 freq-table-hz =
1890 <50000000 200000000>,
1891 <0 0>,
1892 <0 0>,
1893 <37500000 150000000>,
1894 <75000000 300000000>,
1895 <0 0>,
1896 <0 0>,
1897 <0 0>;
1898
Sayali Lokhandeaa3db742017-10-09 15:13:01 +0530[diff] [blame]1899 non-removable;
Sayali Lokhande9ad47f02017-08-02 12:44:31 +0530[diff] [blame]1900 qcom,msm-bus,name = "ufshc_mem";
1901 qcom,msm-bus,num-cases = <12>;
1902 qcom,msm-bus,num-paths = <2>;
1903 qcom,msm-bus,vectors-KBps =
1904 /*
1905 * During HS G3 UFS runs at nominal voltage corner, vote
1906 * higher bandwidth to push other buses in the data path
1907 * to run at nominal to achieve max throughput.
1908 * 4GBps pushes BIMC to run at nominal.
1909 * 200MBps pushes CNOC to run at nominal.
1910 * Vote for half of this bandwidth for HS G3 1-lane.
1911 * For max bandwidth, vote high enough to push the buses
1912 * to run in turbo voltage corner.
1913 */
1914 <123 512 0 0>, <1 757 0 0>, /* No vote */
1915 <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */
1916 <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */
1917 <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */
1918 <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */
1919 <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */
1920 <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */
1921 <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */
1922 <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */
1923 <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */
1924 <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */
1925 <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */
1926
1927 qcom,bus-vector-names = "MIN",
1928 "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
1929 "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
1930 "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
1931 "MAX";
1932
1933 /* PM QoS */
1934 qcom,pm-qos-cpu-groups = <0x3f 0xC0>;
Maulik Shah0223afc2018-02-09 12:47:28 +0530[diff] [blame]1935 qcom,pm-qos-cpu-group-latency-us = <67 67>;
Sayali Lokhande9ad47f02017-08-02 12:44:31 +0530[diff] [blame]1936 qcom,pm-qos-default-cpu = <0>;
1937
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1938 resets = <&clock_gcc GCC_UFS_PHY_BCR>;
1939 reset-names = "core_reset";
1940
1941 status = "disabled";
1942 };
Gaurav Kohlib28d5562017-06-12 11:26:27 +0530[diff] [blame]1943
1944 qcom,lpass@62400000 {
1945 compatible = "qcom,pil-tz-generic";
1946 reg = <0x62400000 0x00100>;
1947 interrupts = <0 162 1>;
1948
1949 vdd_cx-supply = <&pm660l_l9_level>;
1950 qcom,proxy-reg-names = "vdd_cx";
1951 qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
1952
1953 clocks = <&clock_rpmh RPMH_CXO_CLK>;
1954 clock-names = "xo";
1955 qcom,proxy-clock-names = "xo";
1956
1957 qcom,pas-id = <1>;
1958 qcom,proxy-timeout-ms = <10000>;
1959 qcom,smem-id = <423>;
1960 qcom,sysmon-id = <1>;
1961 qcom,ssctl-instance-id = <0x14>;
1962 qcom,firmware-name = "adsp";
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]1963 qcom,signal-aop;
Gaurav Kohlib28d5562017-06-12 11:26:27 +0530[diff] [blame]1964 memory-region = <&pil_adsp_mem>;
1965
1966 /* GPIO inputs from lpass */
1967 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>;
1968 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>;
1969 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>;
1970 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>;
1971
1972 /* GPIO output to lpass */
1973 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>;
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]1974
1975 mboxes = <&qmp_aop 0>;
1976 mbox-names = "adsp-pil";
Gaurav Kohlib28d5562017-06-12 11:26:27 +0530[diff] [blame]1977 status = "ok";
1978 };
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]1979
Sahitya Tummala02e49182017-09-19 10:54:42 +0530[diff] [blame]1980 qcom,rmtfs_sharedmem@0 {
1981 compatible = "qcom,sharedmem-uio";
1982 reg = <0x0 0x200000>;
1983 reg-names = "rmtfs";
1984 qcom,client-id = <0x00000001>;
Sahitya Tummala57f7b572017-10-23 10:29:03 +0530[diff] [blame]1985 qcom,guard-memory;
Sahitya Tummala02e49182017-09-19 10:54:42 +0530[diff] [blame]1986 };
1987
Mohammed Javidf97a10e2017-10-08 13:11:26 +0530[diff] [blame]1988 qcom,msm_gsi {
1989 compatible = "qcom,msm_gsi";
1990 };
1991
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]1992 qcom,rmnet-ipa {
1993 compatible = "qcom,rmnet-ipa3";
1994 qcom,rmnet-ipa-ssr;
1995 qcom,ipa-loaduC;
1996 qcom,ipa-advertise-sg-support;
1997 qcom,ipa-napi-enable;
1998 };
1999
2000 ipa_hw: qcom,ipa@01e00000 {
2001 compatible = "qcom,ipa";
2002 reg = <0x1e00000 0x34000>,
2003 <0x1e04000 0x2c000>;
2004 reg-names = "ipa-base", "gsi-base";
2005 interrupts =
2006 <0 311 0>,
2007 <0 432 0>;
2008 interrupt-names = "ipa-irq", "gsi-irq";
2009 qcom,ipa-hw-ver = <13>; /* IPA core version = IPAv3.5.1 */
2010 qcom,ipa-hw-mode = <1>;
2011 qcom,ee = <0>;
2012 qcom,use-ipa-tethering-bridge;
2013 qcom,modem-cfg-emb-pipe-flt;
2014 qcom,ipa-wdi2;
2015 qcom,use-64-bit-dma-mask;
2016 qcom,arm-smmu;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2017 qcom,bandwidth-vote-for-ipa;
2018 qcom,msm-bus,name = "ipa";
Mohammed Javid963acd02018-01-17 12:59:40 +0530[diff] [blame]2019 qcom,msm-bus,num-cases = <5>;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2020 qcom,msm-bus,num-paths = <4>;
2021 qcom,msm-bus,vectors-KBps =
2022 /* No vote */
2023 <90 512 0 0>,
2024 <90 585 0 0>,
2025 <1 676 0 0>,
2026 <143 777 0 0>,
Mohammed Javid963acd02018-01-17 12:59:40 +0530[diff] [blame]2027 /* SVS2 */
2028 <90 512 80000 600000>,
2029 <90 585 80000 350000>,
2030 <1 676 40000 40000>, /*gcc_config_noc_clk_src */
2031 <143 777 0 75>, /* IB defined for IPA2X_clk in MHz*/
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2032 /* SVS */
2033 <90 512 80000 640000>,
2034 <90 585 80000 640000>,
2035 <1 676 80000 80000>,
Mohammed Javid963acd02018-01-17 12:59:40 +0530[diff] [blame]2036 <143 777 0 150>, /* IB defined for IPA2X_clk in MHz*/
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2037 /* NOMINAL */
2038 <90 512 206000 960000>,
2039 <90 585 206000 960000>,
2040 <1 676 206000 160000>,
Mohammed Javid963acd02018-01-17 12:59:40 +0530[diff] [blame]2041 <143 777 0 300>, /* IB defined for IPA2X_clk in MHz*/
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2042 /* TURBO */
2043 <90 512 206000 3600000>,
2044 <90 585 206000 3600000>,
2045 <1 676 206000 300000>,
Mohammed Javid6c065482017-09-19 19:19:27 +0530[diff] [blame]2046 <143 777 0 355>; /* IB defined for IPA clk in MHz*/
Mohammed Javid963acd02018-01-17 12:59:40 +0530[diff] [blame]2047 qcom,bus-vector-names =
2048 "MIN", "SVS2", "SVS", "NOMINAL", "TURBO";
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2049
2050 /* IPA RAM mmap */
2051 qcom,ipa-ram-mmap = <
2052 0x280 /* ofst_start; */
2053 0x0 /* nat_ofst; */
2054 0x0 /* nat_size; */
2055 0x288 /* v4_flt_hash_ofst; */
2056 0x78 /* v4_flt_hash_size; */
2057 0x4000 /* v4_flt_hash_size_ddr; */
2058 0x308 /* v4_flt_nhash_ofst; */
2059 0x78 /* v4_flt_nhash_size; */
2060 0x4000 /* v4_flt_nhash_size_ddr; */
2061 0x388 /* v6_flt_hash_ofst; */
2062 0x78 /* v6_flt_hash_size; */
2063 0x4000 /* v6_flt_hash_size_ddr; */
2064 0x408 /* v6_flt_nhash_ofst; */
2065 0x78 /* v6_flt_nhash_size; */
2066 0x4000 /* v6_flt_nhash_size_ddr; */
2067 0xf /* v4_rt_num_index; */
2068 0x0 /* v4_modem_rt_index_lo; */
2069 0x7 /* v4_modem_rt_index_hi; */
2070 0x8 /* v4_apps_rt_index_lo; */
2071 0xe /* v4_apps_rt_index_hi; */
2072 0x488 /* v4_rt_hash_ofst; */
2073 0x78 /* v4_rt_hash_size; */
2074 0x4000 /* v4_rt_hash_size_ddr; */
2075 0x508 /* v4_rt_nhash_ofst; */
2076 0x78 /* v4_rt_nhash_size; */
2077 0x4000 /* v4_rt_nhash_size_ddr; */
2078 0xf /* v6_rt_num_index; */
2079 0x0 /* v6_modem_rt_index_lo; */
2080 0x7 /* v6_modem_rt_index_hi; */
2081 0x8 /* v6_apps_rt_index_lo; */
2082 0xe /* v6_apps_rt_index_hi; */
2083 0x588 /* v6_rt_hash_ofst; */
2084 0x78 /* v6_rt_hash_size; */
2085 0x4000 /* v6_rt_hash_size_ddr; */
2086 0x608 /* v6_rt_nhash_ofst; */
2087 0x78 /* v6_rt_nhash_size; */
2088 0x4000 /* v6_rt_nhash_size_ddr; */
2089 0x688 /* modem_hdr_ofst; */
2090 0x140 /* modem_hdr_size; */
2091 0x7c8 /* apps_hdr_ofst; */
2092 0x0 /* apps_hdr_size; */
2093 0x800 /* apps_hdr_size_ddr; */
2094 0x7d0 /* modem_hdr_proc_ctx_ofst; */
2095 0x200 /* modem_hdr_proc_ctx_size; */
2096 0x9d0 /* apps_hdr_proc_ctx_ofst; */
2097 0x200 /* apps_hdr_proc_ctx_size; */
2098 0x0 /* apps_hdr_proc_ctx_size_ddr; */
2099 0x0 /* modem_comp_decomp_ofst; diff */
2100 0x0 /* modem_comp_decomp_size; diff */
2101 0xbd8 /* modem_ofst; */
2102 0x1024 /* modem_size; */
2103 0x2000 /* apps_v4_flt_hash_ofst; */
2104 0x0 /* apps_v4_flt_hash_size; */
2105 0x2000 /* apps_v4_flt_nhash_ofst; */
2106 0x0 /* apps_v4_flt_nhash_size; */
2107 0x2000 /* apps_v6_flt_hash_ofst; */
2108 0x0 /* apps_v6_flt_hash_size; */
2109 0x2000 /* apps_v6_flt_nhash_ofst; */
2110 0x0 /* apps_v6_flt_nhash_size; */
2111 0x80 /* uc_info_ofst; */
2112 0x200 /* uc_info_size; */
2113 0x2000 /* end_ofst; */
2114 0x2000 /* apps_v4_rt_hash_ofst; */
2115 0x0 /* apps_v4_rt_hash_size; */
2116 0x2000 /* apps_v4_rt_nhash_ofst; */
2117 0x0 /* apps_v4_rt_nhash_size; */
2118 0x2000 /* apps_v6_rt_hash_ofst; */
2119 0x0 /* apps_v6_rt_hash_size; */
2120 0x2000 /* apps_v6_rt_nhash_ofst; */
2121 0x0 /* apps_v6_rt_nhash_size; */
2122 0x1c00 /* uc_event_ring_ofst; */
2123 0x400 /* uc_event_ring_size; */
2124 >;
2125
2126 /* smp2p gpio information */
2127 qcom,smp2pgpio_map_ipa_1_out {
2128 compatible = "qcom,smp2pgpio-map-ipa-1-out";
2129 gpios = <&smp2pgpio_ipa_1_out 0 0>;
2130 };
2131
2132 qcom,smp2pgpio_map_ipa_1_in {
2133 compatible = "qcom,smp2pgpio-map-ipa-1-in";
2134 gpios = <&smp2pgpio_ipa_1_in 0 0>;
2135 };
2136
2137 ipa_smmu_ap: ipa_smmu_ap {
2138 compatible = "qcom,ipa-smmu-ap-cb";
Mohammed Javidcc505a62017-10-25 11:36:02 +0530[diff] [blame]2139 qcom,smmu-s1-bypass;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2140 iommus = <&apps_smmu 0x720 0x0>;
2141 qcom,iova-mapping = <0x20000000 0x40000000>;
2142 };
2143
2144 ipa_smmu_wlan: ipa_smmu_wlan {
2145 compatible = "qcom,ipa-smmu-wlan-cb";
Mohammed Javidcc505a62017-10-25 11:36:02 +0530[diff] [blame]2146 qcom,smmu-s1-bypass;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2147 iommus = <&apps_smmu 0x721 0x0>;
2148 };
2149
2150 ipa_smmu_uc: ipa_smmu_uc {
2151 compatible = "qcom,ipa-smmu-uc-cb";
Mohammed Javidcc505a62017-10-25 11:36:02 +0530[diff] [blame]2152 qcom,smmu-s1-bypass;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2153 iommus = <&apps_smmu 0x722 0x0>;
2154 qcom,iova-mapping = <0x40000000 0x20000000>;
2155 };
2156 };
2157
2158 qcom,ipa_fws {
2159 compatible = "qcom,pil-tz-generic";
2160 qcom,pas-id = <0xf>;
2161 qcom,firmware-name = "ipa_fws";
Mohammed Javid42445cb2018-02-01 18:22:17 +0530[diff] [blame]2162 qcom,pil-force-shutdown;
Mohammed Javide0dd2a32018-01-25 14:18:56 +0530[diff] [blame]2163 memory-region = <&pil_ipa_fw_mem>;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2164 };
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2165
2166 pil_modem: qcom,mss@4080000 {
2167 compatible = "qcom,pil-q6v55-mss";
2168 reg = <0x4080000 0x100>,
2169 <0x1f63000 0x008>,
2170 <0x1f65000 0x008>,
2171 <0x1f64000 0x008>,
2172 <0x4180000 0x020>,
2173 <0xc2b0000 0x004>,
2174 <0xb2e0100 0x004>,
2175 <0x4180044 0x004>;
2176 reg-names = "qdsp6_base", "halt_q6", "halt_modem",
2177 "halt_nc", "rmb_base", "restart_reg",
2178 "pdc_sync", "alt_reset";
2179
2180 clocks = <&clock_rpmh RPMH_CXO_CLK>,
2181 <&clock_gcc GCC_MSS_CFG_AHB_CLK>,
2182 <&clock_gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
2183 <&clock_gcc GCC_BOOT_ROM_AHB_CLK>,
2184 <&clock_gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
2185 <&clock_gcc GCC_MSS_SNOC_AXI_CLK>,
2186 <&clock_gcc GCC_MSS_MFAB_AXIS_CLK>,
2187 <&clock_gcc GCC_PRNG_AHB_CLK>;
2188 clock-names = "xo", "iface_clk", "bus_clk",
2189 "mem_clk", "gpll0_mss_clk", "snoc_axi_clk",
2190 "mnoc_axi_clk", "prng_clk";
2191 qcom,proxy-clock-names = "xo", "prng_clk";
2192 qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk",
2193 "gpll0_mss_clk", "snoc_axi_clk",
2194 "mnoc_axi_clk";
2195
2196 interrupts = <0 266 1>;
2197 vdd_cx-supply = <&pm660l_s3_level>;
2198 vdd_cx-voltage = <RPMH_REGULATOR_LEVEL_TURBO>;
2199 vdd_mx-supply = <&pm660l_s1_level>;
2200 vdd_mx-uV = <RPMH_REGULATOR_LEVEL_TURBO>;
Jitendra Sharma2e981ef2017-10-30 12:16:23 +0530[diff] [blame]2201 vdd_mss-supply = <&pm660_s5_level>;
2202 vdd_mss-uV = <RPMH_REGULATOR_LEVEL_TURBO>;
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2203 qcom,firmware-name = "modem";
2204 qcom,pil-self-auth;
2205 qcom,sysmon-id = <0>;
Avaneesh Kumar Dwivedi8d336612017-11-09 16:48:25 +0530[diff] [blame]2206 qcom,minidump-id = <3>;
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2207 qcom,ssctl-instance-id = <0x12>;
2208 qcom,override-acc;
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]2209 qcom,signal-aop;
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2210 qcom,qdsp6v65-1-0;
Jitendra Sharma93dd7fc2017-10-14 17:38:55 +0530[diff] [blame]2211 qcom,mss_pdc_offset = <9>;
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2212 status = "ok";
2213 memory-region = <&pil_modem_mem>;
2214 qcom,mem-protect-id = <0xF>;
2215
2216 /* GPIO inputs from mss */
2217 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
2218 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>;
2219 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;
2220 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>;
2221 qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>;
2222
2223 /* GPIO output to mss */
2224 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]2225
2226 mboxes = <&qmp_aop 0>;
2227 mbox-names = "mss-pil";
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2228 qcom,mba-mem@0 {
2229 compatible = "qcom,pil-mba-mem";
2230 memory-region = <&pil_mba_mem>;
2231 };
2232 };
Gaurav Kohli985a99d2017-07-25 18:46:45 +0530[diff] [blame]2233
2234 qcom,venus@aae0000 {
2235 compatible = "qcom,pil-tz-generic";
2236 reg = <0xaae0000 0x4000>;
2237
2238 vdd-supply = <&venus_gdsc>;
2239 qcom,proxy-reg-names = "vdd";
2240
2241 clocks = <&clock_videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
2242 <&clock_videocc VIDEO_CC_VENUS_AHB_CLK>,
2243 <&clock_videocc VIDEO_CC_VENUS_CTL_AXI_CLK>;
2244 clock-names = "core_clk", "iface_clk", "bus_clk";
2245 qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk";
2246
2247 qcom,pas-id = <9>;
2248 qcom,msm-bus,name = "pil-venus";
2249 qcom,msm-bus,num-cases = <2>;
2250 qcom,msm-bus,num-paths = <1>;
2251 qcom,msm-bus,vectors-KBps =
2252 <63 512 0 0>,
2253 <63 512 0 304000>;
2254 qcom,proxy-timeout-ms = <100>;
2255 qcom,firmware-name = "venus";
2256 memory-region = <&pil_video_mem>;
2257 status = "ok";
2258 };
Gaurav Kohli106f4882017-06-29 12:29:12 +0530[diff] [blame]2259
2260 qcom,turing@8300000 {
2261 compatible = "qcom,pil-tz-generic";
2262 reg = <0x8300000 0x100000>;
2263 interrupts = <0 578 1>;
2264
2265 vdd_cx-supply = <&pm660l_s3_level>;
2266 qcom,proxy-reg-names = "vdd_cx";
2267 qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
2268
2269 clocks = <&clock_rpmh RPMH_CXO_CLK>;
2270 clock-names = "xo";
2271 qcom,proxy-clock-names = "xo";
2272
2273 qcom,pas-id = <18>;
2274 qcom,proxy-timeout-ms = <10000>;
2275 qcom,smem-id = <601>;
2276 qcom,sysmon-id = <7>;
2277 qcom,ssctl-instance-id = <0x17>;
2278 qcom,firmware-name = "cdsp";
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]2279 qcom,signal-aop;
Gaurav Kohli106f4882017-06-29 12:29:12 +0530[diff] [blame]2280 memory-region = <&pil_cdsp_mem>;
2281
2282 /* GPIO inputs from turing */
2283 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_5_in 0 0>;
2284 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_5_in 2 0>;
2285 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_5_in 1 0>;
2286 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_5_in 3 0>;
2287
2288 /* GPIO output to turing*/
2289 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_5_out 0 0>;
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]2290
2291 mboxes = <&qmp_aop 0>;
2292 mbox-names = "cdsp-pil";
Gaurav Kohli106f4882017-06-29 12:29:12 +0530[diff] [blame]2293 status = "ok";
2294 };
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2295
Neeraj Soni27efd652017-11-01 18:17:58 +0530[diff] [blame]2296 sdcc1_ice: sdcc1ice@7c8000 {
2297 compatible = "qcom,ice";
2298 reg = <0x7c8000 0x8000>;
2299 qcom,enable-ice-clk;
2300 clock-names = "ice_core_clk_src", "ice_core_clk",
2301 "bus_clk", "iface_clk";
2302 clocks = <&clock_gcc GCC_SDCC1_ICE_CORE_CLK_SRC>,
2303 <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>,
2304 <&clock_gcc GCC_SDCC1_APPS_CLK>,
2305 <&clock_gcc GCC_SDCC1_AHB_CLK>;
2306 qcom,op-freq-hz = <300000000>, <0>, <0>, <0>;
2307 qcom,msm-bus,name = "sdcc_ice_noc";
2308 qcom,msm-bus,num-cases = <2>;
2309 qcom,msm-bus,num-paths = <1>;
2310 qcom,msm-bus,vectors-KBps =
2311 <150 512 0 0>, /* No vote */
2312 <150 512 1000 0>; /* Max. bandwidth */
2313 qcom,bus-vector-names = "MIN",
2314 "MAX";
2315 qcom,instance-type = "sdcc";
2316 };
2317
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2318 sdhc_1: sdhci@7c4000 {
2319 compatible = "qcom,sdhci-msm-v5";
2320 reg = <0x7C4000 0x1000>, <0x7C5000 0x1000>;
2321 reg-names = "hc_mem", "cmdq_mem";
2322
2323 interrupts = <0 641 0>, <0 644 0>;
2324 interrupt-names = "hc_irq", "pwr_irq";
2325
2326 qcom,bus-width = <8>;
2327 qcom,large-address-bus;
Neeraj Soni27efd652017-11-01 18:17:58 +0530[diff] [blame]2328 sdhc-msm-crypto = <&sdcc1_ice>;
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2329
Vijay Viswanath6f83cbf2017-08-30 16:41:48 +0530[diff] [blame]2330 qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
2331 192000000 384000000>;
Vijay Viswanath01db23a2017-11-09 15:46:22 +0530[diff] [blame]2332 qcom,bus-aggr-clk-rates = <50000000 50000000 50000000 50000000
2333 100000000 200000000 200000000>;
Vijay Viswanath6f83cbf2017-08-30 16:41:48 +0530[diff] [blame]2334 qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
2335
2336 qcom,devfreq,freq-table = <50000000 200000000>;
2337
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2338 qcom,msm-bus,name = "sdhc1";
2339 qcom,msm-bus,num-cases = <9>;
2340 qcom,msm-bus,num-paths = <2>;
2341 qcom,msm-bus,vectors-KBps =
2342 /* No vote */
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2343 <150 512 0 0>, <1 782 0 0>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2344 /* 400 KB/s*/
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2345 <150 512 1046 1600>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2346 <1 782 1600 1600>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2347 /* 20 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2348 <150 512 52286 80000>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2349 <1 782 80000 80000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2350 /* 25 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2351 <150 512 65360 100000>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2352 <1 782 100000 100000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2353 /* 50 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2354 <150 512 130718 200000>,
Vijay Viswanath655407f2017-11-09 12:37:34 +0530[diff] [blame]2355 <1 782 100000 100000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2356 /* 100 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2357 <150 512 130718 200000>,
Vijay Viswanath655407f2017-11-09 12:37:34 +0530[diff] [blame]2358 <1 782 130000 130000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2359 /* 200 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2360 <150 512 261438 400000>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2361 <1 782 300000 300000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2362 /* 400 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2363 <150 512 261438 400000>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2364 <1 782 300000 300000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2365 /* Max. bandwidth */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2366 <150 512 1338562 4096000>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2367 <1 782 1338562 4096000>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2368 qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
2369 100000000 200000000 400000000 4294967295>;
2370
2371 /* PM QoS */
2372 qcom,pm-qos-irq-type = "affine_irq";
Vijay Viswanathcac6f862018-03-20 11:40:54 +0530[diff] [blame]2373 qcom,pm-qos-irq-latency = <67 67>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2374 qcom,pm-qos-cpu-groups = <0x3f 0xc0>;
Maulik Shah0223afc2018-02-09 12:47:28 +0530[diff] [blame]2375 qcom,pm-qos-cmdq-latency-us = <67 67>, <67 67>;
2376 qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2377
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2378 clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>,
Vijay Viswanathcebae3a2017-10-05 14:33:17 +0530[diff] [blame]2379 <&clock_gcc GCC_SDCC1_APPS_CLK>,
Vijay Viswanath7e20ddc2017-10-07 14:23:38 +0530[diff] [blame]2380 <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>,
2381 <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
2382 clock-names = "iface_clk", "core_clk", "ice_core_clk",
2383 "bus_aggr_clk";
Vijay Viswanathcebae3a2017-10-05 14:33:17 +0530[diff] [blame]2384
2385 qcom,ice-clk-rates = <300000000 75000000>;
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2386
Vijay Viswanathd4dcf5f2017-10-17 15:42:00 +0530[diff] [blame]2387 qcom,ddr-config = <0xC3040873>;
2388
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2389 qcom,nonremovable;
Asutosh Das3d37f972018-01-12 15:48:25 +0530[diff] [blame]2390 nvmem-cells = <&minor_rev>;
2391 nvmem-cell-names = "minor_rev";
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2392
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2393 status = "disabled";
2394 };
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2395
Vijay Viswanathee4340d2017-08-28 09:50:18 +0530[diff] [blame]2396 sdhc_2: sdhci@8804000 {
2397 compatible = "qcom,sdhci-msm-v5";
2398 reg = <0x8804000 0x1000>;
2399 reg-names = "hc_mem";
2400
2401 interrupts = <0 204 0>, <0 222 0>;
2402 interrupt-names = "hc_irq", "pwr_irq";
2403
2404 qcom,bus-width = <4>;
2405 qcom,large-address-bus;
2406
Vijay Viswanath6f83cbf2017-08-30 16:41:48 +0530[diff] [blame]2407 qcom,clk-rates = <400000 20000000 25000000
2408 50000000 100000000 201500000>;
2409 qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
2410 "SDR104";
2411
2412 qcom,devfreq,freq-table = <50000000 201500000>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2413
2414 qcom,msm-bus,name = "sdhc2";
2415 qcom,msm-bus,num-cases = <8>;
2416 qcom,msm-bus,num-paths = <2>;
2417 qcom,msm-bus,vectors-KBps =
2418 /* No vote */
2419 <81 512 0 0>, <1 608 0 0>,
2420 /* 400 KB/s*/
2421 <81 512 1046 1600>,
2422 <1 608 1600 1600>,
2423 /* 20 MB/s */
2424 <81 512 52286 80000>,
2425 <1 608 80000 80000>,
2426 /* 25 MB/s */
2427 <81 512 65360 100000>,
2428 <1 608 100000 100000>,
2429 /* 50 MB/s */
2430 <81 512 130718 200000>,
Vijay Viswanath655407f2017-11-09 12:37:34 +0530[diff] [blame]2431 <1 608 100000 100000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2432 /* 100 MB/s */
2433 <81 512 261438 200000>,
Vijay Viswanath655407f2017-11-09 12:37:34 +0530[diff] [blame]2434 <1 608 130000 130000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2435 /* 200 MB/s */
2436 <81 512 261438 400000>,
2437 <1 608 300000 300000>,
2438 /* Max. bandwidth */
2439 <81 512 1338562 4096000>,
2440 <1 608 1338562 4096000>;
2441 qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
2442 100000000 200000000 4294967295>;
2443
2444 /* PM QoS */
2445 qcom,pm-qos-irq-type = "affine_irq";
Maulik Shah0223afc2018-02-09 12:47:28 +0530[diff] [blame]2446 qcom,pm-qos-irq-latency = <67 67>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2447 qcom,pm-qos-cpu-groups = <0x3f 0xc0>;
Maulik Shah0223afc2018-02-09 12:47:28 +0530[diff] [blame]2448 qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2449
Vijay Viswanathee4340d2017-08-28 09:50:18 +0530[diff] [blame]2450 clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>,
2451 <&clock_gcc GCC_SDCC2_APPS_CLK>;
2452 clock-names = "iface_clk", "core_clk";
2453
2454 status = "disabled";
2455 };
2456
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2457 qcom,msm-cdsp-loader {
2458 compatible = "qcom,cdsp-loader";
2459 qcom,proc-img-to-load = "cdsp";
2460 };
2461
2462 qcom,msm-adsprpc-mem {
2463 compatible = "qcom,msm-adsprpc-mem-region";
2464 memory-region = <&adsp_mem>;
Tharun Kumar Merugu8bb71292018-01-17 15:55:05 +0530[diff] [blame]2465 restrict-access;
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2466 };
2467
2468 qcom,msm_fastrpc {
2469 compatible = "qcom,msm-fastrpc-compute";
Tharun Kumar Merugubbebad12017-12-21 16:33:03 +0530[diff] [blame]2470 qcom,adsp-remoteheap-vmid = <22 37>;
Tharun Kumar Merugu1cb19c62018-01-18 12:20:16 +0530[diff] [blame]2471 qcom,fastrpc-adsp-audio-pdr;
Tharun Kumar Merugub67b0ef2018-02-07 21:30:39 +0530[diff] [blame^]2472 qcom,fastrpc-adsp-sensors-pdr;
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2473
2474 qcom,msm_fastrpc_compute_cb1 {
2475 compatible = "qcom,msm-fastrpc-compute-cb";
2476 label = "cdsprpc-smd";
2477 iommus = <&apps_smmu 0x1421 0x30>;
2478 dma-coherent;
2479 };
2480 qcom,msm_fastrpc_compute_cb2 {
2481 compatible = "qcom,msm-fastrpc-compute-cb";
2482 label = "cdsprpc-smd";
2483 iommus = <&apps_smmu 0x1422 0x30>;
2484 dma-coherent;
2485 };
2486 qcom,msm_fastrpc_compute_cb3 {
2487 compatible = "qcom,msm-fastrpc-compute-cb";
2488 label = "cdsprpc-smd";
2489 iommus = <&apps_smmu 0x1423 0x30>;
2490 dma-coherent;
2491 };
2492 qcom,msm_fastrpc_compute_cb4 {
2493 compatible = "qcom,msm-fastrpc-compute-cb";
2494 label = "cdsprpc-smd";
2495 iommus = <&apps_smmu 0x1424 0x30>;
2496 dma-coherent;
2497 };
2498 qcom,msm_fastrpc_compute_cb5 {
2499 compatible = "qcom,msm-fastrpc-compute-cb";
2500 label = "cdsprpc-smd";
2501 iommus = <&apps_smmu 0x1425 0x30>;
2502 dma-coherent;
2503 };
2504 qcom,msm_fastrpc_compute_cb6 {
2505 compatible = "qcom,msm-fastrpc-compute-cb";
2506 label = "cdsprpc-smd";
2507 iommus = <&apps_smmu 0x1426 0x30>;
2508 dma-coherent;
2509 };
2510 qcom,msm_fastrpc_compute_cb7 {
2511 compatible = "qcom,msm-fastrpc-compute-cb";
2512 label = "cdsprpc-smd";
2513 qcom,secure-context-bank;
2514 iommus = <&apps_smmu 0x1429 0x30>;
2515 dma-coherent;
2516 };
2517 qcom,msm_fastrpc_compute_cb8 {
2518 compatible = "qcom,msm-fastrpc-compute-cb";
2519 label = "cdsprpc-smd";
2520 qcom,secure-context-bank;
2521 iommus = <&apps_smmu 0x142A 0x30>;
2522 dma-coherent;
2523 };
2524 qcom,msm_fastrpc_compute_cb9 {
2525 compatible = "qcom,msm-fastrpc-compute-cb";
2526 label = "adsprpc-smd";
2527 iommus = <&apps_smmu 0x1803 0x0>;
2528 dma-coherent;
2529 };
2530 qcom,msm_fastrpc_compute_cb10 {
2531 compatible = "qcom,msm-fastrpc-compute-cb";
2532 label = "adsprpc-smd";
2533 iommus = <&apps_smmu 0x1804 0x0>;
2534 dma-coherent;
2535 };
2536 qcom,msm_fastrpc_compute_cb11 {
2537 compatible = "qcom,msm-fastrpc-compute-cb";
2538 label = "adsprpc-smd";
2539 iommus = <&apps_smmu 0x1805 0x0>;
2540 dma-coherent;
2541 };
c_mtharu92125922017-10-16 14:06:39 +0530[diff] [blame]2542 qcom,msm_fastrpc_compute_cb12 {
2543 compatible = "qcom,msm-fastrpc-compute-cb";
2544 label = "adsprpc-smd";
2545 iommus = <&apps_smmu 0x1806 0x0>;
2546 dma-coherent;
Tharun Kumar Merugub67b0ef2018-02-07 21:30:39 +0530[diff] [blame^]2547 shared-cb;
c_mtharu92125922017-10-16 14:06:39 +0530[diff] [blame]2548 };
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2549 };
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2550
Rupesh Tatiyaf2072952017-10-08 19:57:12 +0530[diff] [blame]2551 bluetooth: bt_wcn3990 {
2552 compatible = "qca,wcn3990";
2553 qca,bt-vdd-core-supply = <&pm660_l9>;
2554 qca,bt-vdd-pa-supply = <&pm660_l6>;
2555 qca,bt-vdd-ldo-supply = <&pm660_l19>;
2556
2557 qca,bt-vdd-core-voltage-level = <1800000 1900000>;
2558 qca,bt-vdd-pa-voltage-level = <1304000 1370000>;
2559 qca,bt-vdd-ldo-voltage-level = <3312000 3400000>;
2560
2561 qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */
2562 qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */
2563 qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */
2564 };
2565
Sarada Prasanna Garnayakd5ccc902018-02-22 15:54:50 +0530[diff] [blame]2566 icnss: qcom,icnss@18800000 {
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2567 compatible = "qcom,icnss";
Anurag Chouhand22b18a2017-10-08 15:16:08 +0530[diff] [blame]2568 reg = <0x18800000 0x800000>,
2569 <0xa0000000 0x10000000>,
2570 <0xb0000000 0x10000>;
2571 reg-names = "membase", "smmu_iova_base", "smmu_iova_ipa";
2572 iommus = <&apps_smmu 0x0040 0x1>;
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2573 interrupts = <0 414 0 /* CE0 */ >,
2574 <0 415 0 /* CE1 */ >,
2575 <0 416 0 /* CE2 */ >,
2576 <0 417 0 /* CE3 */ >,
2577 <0 418 0 /* CE4 */ >,
2578 <0 419 0 /* CE5 */ >,
2579 <0 420 0 /* CE6 */ >,
2580 <0 421 0 /* CE7 */ >,
2581 <0 422 0 /* CE8 */ >,
2582 <0 423 0 /* CE9 */ >,
2583 <0 424 0 /* CE10 */ >,
2584 <0 425 0 /* CE11 */ >;
Anurag Chouhand22b18a2017-10-08 15:16:08 +0530[diff] [blame]2585 vdd-0.8-cx-mx-supply = <&pm660_l5>;
2586 vdd-1.8-xo-supply = <&pm660_l9>;
2587 vdd-1.3-rfa-supply = <&pm660_l6>;
2588 vdd-3.3-ch0-supply = <&pm660_l19>;
Hardik Kantilal Patel25c05b42017-12-08 11:10:27 +0530[diff] [blame]2589 qcom,vdd-3.3-ch0-config = <3000000 3312000>;
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2590 qcom,wlan-msa-memory = <0x100000>;
Anurag Chouhana4f55db2017-11-22 16:35:27 +0530[diff] [blame]2591 qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
Hardik Kantilal Patel1697bd12018-03-05 14:46:29 +0530[diff] [blame]2592 qcom,gpio-force-fatal-error = <&smp2pgpio_wlan_1_in 0 0>;
2593 qcom,gpio-early-crash-ind = <&smp2pgpio_wlan_1_in 1 0>;
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2594 qcom,smmu-s1-bypass;
2595 };
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2596
2597 cpubw: qcom,cpubw {
2598 compatible = "qcom,devbw";
2599 governor = "performance";
2600 qcom,src-dst-ports =
Santosh Mardidfc78812017-10-05 13:15:20 +0530[diff] [blame]2601 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2602 qcom,active-only;
2603 qcom,bw-tbl =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2604 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2605 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2606 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2607 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2608 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2609 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2610 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2611 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2612 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2613 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2614 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2615 };
2616
Santosh Mardidfc78812017-10-05 13:15:20 +0530[diff] [blame]2617 bwmon: qcom,cpu-bwmon {
2618 compatible = "qcom,bimc-bwmon4";
2619 reg = <0x1436400 0x300>, <0x1436300 0x200>;
2620 reg-names = "base", "global_base";
2621 interrupts = <0 581 4>;
2622 qcom,mport = <0>;
Santosh Mardida0b0f82017-10-13 23:30:22 +0530[diff] [blame]2623 qcom,count-unit = <0x10000>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2624 qcom,hw-timer-hz = <19200000>;
Santosh Mardidfc78812017-10-05 13:15:20 +0530[diff] [blame]2625 qcom,target-dev = <&cpubw>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2626 };
2627
2628 memlat_cpu0: qcom,memlat-cpu0 {
2629 compatible = "qcom,devbw";
2630 governor = "powersave";
2631 qcom,src-dst-ports = <1 512>;
2632 qcom,active-only;
2633 qcom,bw-tbl =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2634 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2635 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2636 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2637 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2638 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2639 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2640 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2641 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2642 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2643 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2644 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2645 };
2646
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2647 memlat_cpu6: qcom,memlat-cpu6 {
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2648 compatible = "qcom,devbw";
2649 governor = "powersave";
2650 qcom,src-dst-ports = <1 512>;
2651 qcom,active-only;
2652 status = "ok";
2653 qcom,bw-tbl =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2654 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2655 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2656 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2657 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2658 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2659 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2660 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2661 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2662 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2663 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2664 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2665 };
2666
Odelu Kukatlafe8d3302017-11-17 10:54:32 +0530[diff] [blame]2667 snoc_cnoc_keepalive: qcom,snoc_cnoc_keepalive {
2668 compatible = "qcom,devbw";
2669 governor = "powersave";
2670 qcom,src-dst-ports = <139 627>;
2671 qcom,active-only;
2672 status = "ok";
2673 qcom,bw-tbl =
2674 < 1 >;
2675 };
2676
Odelu Kukatla95e7aea2018-02-27 15:46:39 +0530[diff] [blame]2677 bus_proxy_client: qcom,bus_proxy_client {
2678 compatible = "qcom,bus-proxy-client";
2679 qcom,msm-bus,name = "bus-proxy-client";
2680 qcom,msm-bus,num-cases = <2>;
2681 qcom,msm-bus,num-paths = <2>;
2682 qcom,msm-bus,vectors-KBps =
2683 <22 512 0 0>, <23 512 0 0>,
2684 <22 512 0 5000000>, <23 512 0 5000000>;
2685 qcom,msm-bus,active-only;
2686 status = "ok";
2687 };
2688
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2689 devfreq_memlat_0: qcom,cpu0-memlat-mon {
2690 compatible = "qcom,arm-memlat-mon";
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2691 qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2692 qcom,target-dev = <&memlat_cpu0>;
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2693 qcom,cachemiss-ev = <0x2a>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2694 qcom,core-dev-table =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2695 < 748800 MHZ_TO_MBPS( 300, 4) >,
2696 < 998400 MHZ_TO_MBPS( 451, 4) >,
2697 < 1209600 MHZ_TO_MBPS( 547, 4) >,
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2698 < 1516800 MHZ_TO_MBPS( 768, 4) >,
2699 < 1708000 MHZ_TO_MBPS(1017, 4) >;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2700 };
2701
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2702 devfreq_memlat_6: qcom,cpu6-memlat-mon {
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2703 compatible = "qcom,arm-memlat-mon";
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2704 qcom,cpulist = <&CPU6 &CPU7>;
2705 qcom,target-dev = <&memlat_cpu6>;
2706 qcom,cachemiss-ev = <0x2a>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2707 qcom,core-dev-table =
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2708 < 825600 MHZ_TO_MBPS( 300, 4) >,
2709 < 1132800 MHZ_TO_MBPS( 547, 4) >,
2710 < 1363200 MHZ_TO_MBPS(1017, 4) >,
2711 < 1996800 MHZ_TO_MBPS(1555, 4) >,
2712 < 2457600 MHZ_TO_MBPS(1804, 4) >;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2713 };
2714
2715 l3_cpu0: qcom,l3-cpu0 {
2716 compatible = "devfreq-simple-dev";
2717 clock-names = "devfreq_clk";
2718 clocks = <&clock_cpucc L3_CLUSTER0_VOTE_CLK>;
2719 governor = "performance";
2720 };
2721
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2722 l3_cpu6: qcom,l3-cpu6 {
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2723 compatible = "devfreq-simple-dev";
2724 clock-names = "devfreq_clk";
2725 clocks = <&clock_cpucc L3_CLUSTER1_VOTE_CLK>;
2726 governor = "performance";
2727 };
2728
2729 devfreq_l3lat_0: qcom,cpu0-l3lat-mon {
2730 compatible = "qcom,arm-memlat-mon";
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2731 qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2732 qcom,target-dev = <&l3_cpu0>;
2733 qcom,cachemiss-ev = <0x17>;
2734 qcom,core-dev-table =
Santosh Mardi10d45032017-11-02 17:25:54 +0530[diff] [blame]2735 < 576000 300000000 >,
Santosh Mardi831cc872018-01-11 14:52:32 +0530[diff] [blame]2736 < 998400 556800000 >,
2737 < 1209660 844800000 >,
2738 < 1516800 940800000 >,
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2739 < 1612800 1382400000 >,
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2740 < 1708000 1440000000 >;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2741 };
2742
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2743 devfreq_l3lat_6: qcom,cpu6-l3lat-mon {
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2744 compatible = "qcom,arm-memlat-mon";
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2745 qcom,cpulist = <&CPU6 &CPU7>;
2746 qcom,target-dev = <&l3_cpu6>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2747 qcom,cachemiss-ev = <0x17>;
2748 qcom,core-dev-table =
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2749 < 1132800 556800000 >,
2750 < 1363200 806400000 >,
2751 < 1747200 940800000 >,
2752 < 1996800 1190400000 >,
2753 < 2457600 1440000000 >;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2754 };
2755
2756 mincpubw: qcom,mincpubw {
2757 compatible = "qcom,devbw";
2758 governor = "powersave";
2759 qcom,src-dst-ports = <1 512>;
2760 qcom,active-only;
2761 qcom,bw-tbl =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2762 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2763 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2764 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2765 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2766 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2767 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2768 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2769 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2770 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2771 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2772 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2773 };
2774
2775 devfreq-cpufreq {
2776 mincpubw-cpufreq {
2777 target-dev = <&mincpubw>;
2778 cpu-to-dev-map-0 =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2779 < 748800 MHZ_TO_MBPS( 300, 4) >,
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2780 < 1209660 MHZ_TO_MBPS( 451, 4) >,
2781 < 1612800 MHZ_TO_MBPS( 547, 4) >,
2782 < 1708000 MHZ_TO_MBPS( 768, 4) >;
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2783 cpu-to-dev-map-6 =
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2784 < 1132800 MHZ_TO_MBPS( 300, 4) >,
2785 < 1363200 MHZ_TO_MBPS( 547, 4) >,
2786 < 1747200 MHZ_TO_MBPS( 768, 4) >,
2787 < 1996800 MHZ_TO_MBPS(1017, 4) >,
2788 < 2457600 MHZ_TO_MBPS(1804, 4) >;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2789 };
2790 };
Amit Nischal199f15d2017-09-12 10:58:51 +0530[diff] [blame]2791
Jonathan Avilac7a6fd52017-10-12 15:24:05 -0700[diff] [blame]2792 mincpu0bw: qcom,mincpu0bw {
2793 compatible = "qcom,devbw";
2794 governor = "powersave";
2795 qcom,src-dst-ports = <1 512>;
2796 qcom,active-only;
2797 qcom,bw-tbl =
2798 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2799 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2800 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2801 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2802 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2803 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2804 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2805 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2806 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2807 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2808 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
2809 };
2810
2811 mincpu6bw: qcom,mincpu6bw {
2812 compatible = "qcom,devbw";
2813 governor = "powersave";
2814 qcom,src-dst-ports = <1 512>;
2815 qcom,active-only;
2816 qcom,bw-tbl =
2817 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2818 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2819 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2820 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2821 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2822 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2823 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2824 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2825 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2826 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2827 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
2828 };
2829
2830 devfreq_compute0: qcom,devfreq-compute0 {
2831 compatible = "qcom,arm-cpu-mon";
2832 qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
2833 qcom,target-dev = <&mincpu0bw>;
2834 qcom,core-dev-table =
2835 < 748800 MHZ_TO_MBPS( 300, 4) >,
2836 < 1209660 MHZ_TO_MBPS( 451, 4) >,
2837 < 1612800 MHZ_TO_MBPS( 547, 4) >,
2838 < 1708000 MHZ_TO_MBPS( 768, 4) >;
2839 };
2840
2841 devfreq_compute6: qcom,devfreq-compute6 {
2842 compatible = "qcom,arm-cpu-mon";
2843 qcom,cpulist = <&CPU6 &CPU7>;
2844 qcom,target-dev = <&mincpu6bw>;
2845 qcom,core-dev-table =
2846 < 1132800 MHZ_TO_MBPS( 300, 4) >,
2847 < 1363200 MHZ_TO_MBPS( 547, 4) >,
2848 < 1747200 MHZ_TO_MBPS( 768, 4) >,
2849 < 1996800 MHZ_TO_MBPS(1017, 4) >,
2850 < 2457600 MHZ_TO_MBPS(1804, 4) >;
2851 };
2852
Santosh Mardi7790a432018-01-09 23:01:56 +0530[diff] [blame]2853 l3_cdsp: qcom,l3-cdsp {
2854 compatible = "devfreq-simple-dev";
2855 clock-names = "devfreq_clk";
2856 clocks = <&clock_cpucc L3_MISC_VOTE_CLK>;
2857 governor = "powersave";
2858 };
2859
Raghavendra Rao Ananta28dd4502017-10-18 10:28:31 -0700[diff] [blame]2860 cpu_pmu: cpu-pmu {
2861 compatible = "arm,armv8-pmuv3";
2862 qcom,irq-is-percpu;
2863 interrupts = <1 5 4>;
2864 };
2865
Amit Nischal199f15d2017-09-12 10:58:51 +0530[diff] [blame]2866 gpu_gx_domain_addr: syscon@0x5091508 {
2867 compatible = "syscon";
2868 reg = <0x5091508 0x4>;
2869 };
2870
2871 gpu_gx_sw_reset: syscon@0x5091008 {
2872 compatible = "syscon";
2873 reg = <0x5091008 0x4>;
2874 };
Prakash Gupta325dff62018-01-09 15:38:09 +0530[diff] [blame]2875
2876 qfprom: qfprom@0x780000 {
2877 compatible = "qcom,qfprom";
Prakash Gupta50a47e52018-01-29 16:11:19 +0530[diff] [blame]2878 reg = <0x00784000 0x1000>;
Prakash Gupta325dff62018-01-09 15:38:09 +0530[diff] [blame]2879 #address-cells = <1>;
2880 #size-cells = <1>;
2881 ranges;
2882
Prakash Gupta50a47e52018-01-29 16:11:19 +0530[diff] [blame]2883 minor_rev: minor_rev@0x78414c {
Prakash Gupta325dff62018-01-09 15:38:09 +0530[diff] [blame]2884 reg = <0x14c 0x4>;
Prakash Gupta50a47e52018-01-29 16:11:19 +0530[diff] [blame]2885 bits = <0 30>; /* Access 30 bits from bit offset 0 */
Prakash Gupta325dff62018-01-09 15:38:09 +0530[diff] [blame]2886 };
2887 };
2888
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]2889};
2890
Ashay Jaiswal81940302017-09-20 15:17:58 +0530[diff] [blame]2891#include "pm660.dtsi"
2892#include "pm660l.dtsi"
2893#include "sdm670-regulator.dtsi"
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]2894#include "sdm670-pinctrl.dtsi"
Vijayanand Jittad48c4082017-06-07 15:07:51 +0530[diff] [blame]2895#include "msm-arm-smmu-sdm670.dtsi"
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2896#include "msm-gdsc-sdm845.dtsi"
Maulik Shahd313ea82017-06-14 13:10:52 +0530[diff] [blame]2897#include "sdm670-pm.dtsi"
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2898
2899&usb30_prim_gdsc {
2900 status = "ok";
2901};
2902
2903&ufs_phy_gdsc {
2904 status = "ok";
2905};
2906
2907&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc {
2908 status = "ok";
2909};
2910
2911&hlos1_vote_aggre_noc_mmu_tbu1_gdsc {
2912 status = "ok";
2913};
2914
2915&hlos1_vote_aggre_noc_mmu_tbu2_gdsc {
2916 status = "ok";
2917};
2918
Odelu Kukatla1186d2e2017-08-04 17:28:46 +0530[diff] [blame]2919&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
2920 status = "ok";
2921};
2922
2923&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
2924 status = "ok";
2925};
2926
2927&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {
2928 status = "ok";
2929};
2930
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2931&bps_gdsc {
Odelu Kukatla4328a432017-12-06 18:16:59 +0530[diff] [blame]2932 qcom,support-hw-trigger;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2933 status = "ok";
2934};
2935
2936&ife_0_gdsc {
2937 status = "ok";
2938};
2939
2940&ife_1_gdsc {
2941 status = "ok";
2942};
2943
2944&ipe_0_gdsc {
Odelu Kukatla4328a432017-12-06 18:16:59 +0530[diff] [blame]2945 qcom,support-hw-trigger;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2946 status = "ok";
2947};
2948
2949&ipe_1_gdsc {
Odelu Kukatla4328a432017-12-06 18:16:59 +0530[diff] [blame]2950 qcom,support-hw-trigger;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2951 status = "ok";
2952};
2953
2954&titan_top_gdsc {
2955 status = "ok";
2956};
2957
2958&mdss_core_gdsc {
2959 status = "ok";
Sandeep Pandaae888352017-11-15 13:15:31 +0530[diff] [blame]2960 proxy-supply = <&mdss_core_gdsc>;
2961 qcom,proxy-consumer-enable;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2962};
2963
2964&gpu_cx_gdsc {
2965 status = "ok";
2966};
2967
2968&gpu_gx_gdsc {
2969 clock-names = "core_root_clk";
2970 clocks = <&clock_gfx GPU_CC_GX_GFX3D_CLK_SRC>;
2971 qcom,force-enable-root-clk;
Odelu Kukatla1186d2e2017-08-04 17:28:46 +0530[diff] [blame]2972 parent-supply = <&pm660l_s2_level>;
Amit Nischal199f15d2017-09-12 10:58:51 +0530[diff] [blame]2973 domain-addr = <&gpu_gx_domain_addr>;
2974 sw-reset = <&gpu_gx_sw_reset>;
2975 qcom,reset-aon-logic;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2976 status = "ok";
2977};
2978
2979&vcodec0_gdsc {
2980 qcom,support-hw-trigger;
2981 status = "ok";
2982};
2983
2984&vcodec1_gdsc {
2985 qcom,support-hw-trigger;
2986 status = "ok";
2987};
2988
2989&venus_gdsc {
2990 status = "ok";
2991};
Tirupathi Reddy0cfe2082017-06-08 14:24:13 +0530[diff] [blame]2992
Sandeep Panda229db242017-10-03 11:32:29 +0530[diff] [blame]2993&mdss_dsi0 {
2994 qcom,core-supply-entries {
2995 #address-cells = <1>;
2996 #size-cells = <0>;
2997
2998 qcom,core-supply-entry@0 {
2999 reg = <0>;
3000 qcom,supply-name = "refgen";
3001 qcom,supply-min-voltage = <0>;
3002 qcom,supply-max-voltage = <0>;
3003 qcom,supply-enable-load = <0>;
3004 qcom,supply-disable-load = <0>;
3005 };
3006 };
3007};
3008
3009&mdss_dsi1 {
3010 qcom,core-supply-entries {
3011 #address-cells = <1>;
3012 #size-cells = <0>;
3013
3014 qcom,core-supply-entry@0 {
3015 reg = <0>;
3016 qcom,supply-name = "refgen";
3017 qcom,supply-min-voltage = <0>;
3018 qcom,supply-max-voltage = <0>;
3019 qcom,supply-enable-load = <0>;
3020 qcom,supply-disable-load = <0>;
3021 };
3022 };
3023};
3024
Padmanabhan Komanduru07137332017-10-20 12:53:23 +0530[diff] [blame]3025&sde_dp {
3026 qcom,core-supply-entries {
3027 #address-cells = <1>;
3028 #size-cells = <0>;
3029
3030 qcom,core-supply-entry@0 {
3031 reg = <0>;
3032 qcom,supply-name = "refgen";
3033 qcom,supply-min-voltage = <0>;
3034 qcom,supply-max-voltage = <0>;
3035 qcom,supply-enable-load = <0>;
3036 qcom,supply-disable-load = <0>;
3037 };
3038 };
3039};
3040
Rohit Kumar14051282017-07-12 11:18:48 +0530[diff] [blame]3041#include "sdm670-audio.dtsi"
Pratham Pratap9e420a32017-09-05 11:26:57 +0530[diff] [blame]3042#include "sdm670-usb.dtsi"
Rajesh Kemisettiba56c482017-08-31 18:12:35 +0530[diff] [blame]3043#include "sdm670-gpu.dtsi"
Suresh Vankadara402d0ca2017-10-26 22:54:54 +0530[diff] [blame]3044#include "sdm670-camera.dtsi"
Manaf Meethalavalappu Pallikunhi52c7ba12017-09-07 01:41:43 +0530[diff] [blame]3045#include "sdm670-thermal.dtsi"
Odelu Kukatlaf197e382017-07-04 19:47:35 +0530[diff] [blame]3046#include "sdm670-bus.dtsi"
Tirupathi Reddyf805ac72017-10-12 14:22:17 +0530[diff] [blame]3047
3048&pm660_div_clk {
3049 status = "ok";
3050};
Tirupathi Reddy53b92a62017-10-26 13:57:42 +0530[diff] [blame]3051
3052&qupv3_se10_i2c {
3053 nx30p6093: nx30p6093@36 {
3054 status = "disabled";
3055 compatible = "nxp,nx30p6093";
3056 reg = <0x36>;
3057 interrupt-parent = <&tlmm>;
3058 interrupts = <5 IRQ_TYPE_NONE>;
3059 nxp,long-wakeup-sec = <28800>; /* 8 hours */
3060 nxp,short-wakeup-ms = <180000>; /* 3 mins */
3061 pinctrl-names = "default";
3062 pinctrl-0 = <&nx30p6093_intr_default>;
3063 };
3064};