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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mm/tlb-v6.S
3 *
4 * Copyright (C) 1997-2002 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * ARM architecture version 6 TLB handling functions.
11 * These assume a split I/D TLB.
12 */
Tim Abbott991da172009-04-27 14:02:22 -040013#include <linux/init.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/linkage.h>
Sam Ravnborge6ae7442005-09-09 21:08:59 +020015#include <asm/asm-offsets.h>
Russell King6ebbf2c2014-06-30 16:29:12 +010016#include <asm/assembler.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <asm/page.h>
18#include <asm/tlbflush.h>
19#include "proc-macros.S"
20
21#define HARVARD_TLB
22
23/*
24 * v6wbi_flush_user_tlb_range(start, end, vma)
25 *
26 * Invalidate a range of TLB entries in the specified address space.
27 *
28 * - start - start address (may not be aligned)
29 * - end - end address (exclusive, may not be aligned)
30 * - vma - vma_struct describing address range
31 *
32 * It is assumed that:
33 * - the "Invalidate single entry" instruction will invalidate
34 * both the I and the D TLBs on Harvard-style TLBs
35 */
36ENTRY(v6wbi_flush_user_tlb_range)
37 vma_vm_mm r3, r2 @ get vma->vm_mm
38 mov ip, #0
39 mmid r3, r3 @ get vm_mm->context.id
40 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
41 mov r0, r0, lsr #PAGE_SHIFT @ align address
42 mov r1, r1, lsr #PAGE_SHIFT
43 asid r3, r3 @ mask ASID
44 orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA
45 mov r1, r1, lsl #PAGE_SHIFT
46 vma_vm_flags r2, r2 @ get vma->vm_flags
471:
48#ifdef HARVARD_TLB
49 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
50 tst r2, #VM_EXEC @ Executable area ?
51 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
52#else
53 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
54#endif
55 add r0, r0, #PAGE_SZ
56 cmp r0, r1
57 blo 1b
Catalin Marinase6a5d662007-02-05 14:47:51 +010058 mcr p15, 0, ip, c7, c10, 4 @ data synchronization barrier
Russell King6ebbf2c2014-06-30 16:29:12 +010059 ret lr
Linus Torvalds1da177e2005-04-16 15:20:36 -070060
61/*
62 * v6wbi_flush_kern_tlb_range(start,end)
63 *
64 * Invalidate a range of kernel TLB entries
65 *
66 * - start - start address (may not be aligned)
67 * - end - end address (exclusive, may not be aligned)
68 */
69ENTRY(v6wbi_flush_kern_tlb_range)
70 mov r2, #0
71 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
72 mov r0, r0, lsr #PAGE_SHIFT @ align address
73 mov r1, r1, lsr #PAGE_SHIFT
74 mov r0, r0, lsl #PAGE_SHIFT
75 mov r1, r1, lsl #PAGE_SHIFT
761:
77#ifdef HARVARD_TLB
78 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
79 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
80#else
81 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
82#endif
83 add r0, r0, #PAGE_SZ
84 cmp r0, r1
85 blo 1b
Catalin Marinas6a0e2432006-03-07 14:42:27 +000086 mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier
Russell King43488102011-07-05 09:01:13 +010087 mcr p15, 0, r2, c7, c5, 4 @ prefetch flush (isb)
Russell King6ebbf2c2014-06-30 16:29:12 +010088 ret lr
Linus Torvalds1da177e2005-04-16 15:20:36 -070089
Tim Abbott991da172009-04-27 14:02:22 -040090 __INIT
Linus Torvalds1da177e2005-04-16 15:20:36 -070091
Dave Martin3b7f39f2011-06-23 17:31:01 +010092 /* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
93 define_tlb_functions v6wbi, v6wbi_tlb_flags