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Erik Gillingc5f80062010-01-21 16:53:02 -08001/*
Erik Gillingc5f80062010-01-21 16:53:02 -08002 * Copyright (C) 2010 Google, Inc.
3 *
4 * Author:
5 * Colin Cross <ccross@google.com>
6 * Erik Gilling <konkers@google.com>
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19#ifndef __MACH_TEGRA_IOMAP_H
20#define __MACH_TEGRA_IOMAP_H
21
Stephen Warren6dee8202013-10-29 13:47:21 -060022#include <asm/pgtable.h>
Erik Gillingc5f80062010-01-21 16:53:02 -080023#include <asm/sizes.h>
24
Colin Crossc231d692010-07-27 21:34:38 -070025#define TEGRA_IRAM_BASE 0x40000000
26#define TEGRA_IRAM_SIZE SZ_256K
27
Erik Gillingc5f80062010-01-21 16:53:02 -080028#define TEGRA_ARM_PERIF_BASE 0x50040000
29#define TEGRA_ARM_PERIF_SIZE SZ_8K
30
31#define TEGRA_ARM_INT_DIST_BASE 0x50041000
32#define TEGRA_ARM_INT_DIST_SIZE SZ_4K
33
Erik Gillingc5f80062010-01-21 16:53:02 -080034#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
35#define TEGRA_PRIMARY_ICTLR_SIZE SZ_64
36
37#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100
38#define TEGRA_SECONDARY_ICTLR_SIZE SZ_64
39
40#define TEGRA_TERTIARY_ICTLR_BASE 0x60004200
41#define TEGRA_TERTIARY_ICTLR_SIZE SZ_64
42
43#define TEGRA_QUATERNARY_ICTLR_BASE 0x60004300
44#define TEGRA_QUATERNARY_ICTLR_SIZE SZ_64
45
Peter De Schrijvercaa48682012-01-05 03:31:45 +000046#define TEGRA_QUINARY_ICTLR_BASE 0x60004400
47#define TEGRA_QUINARY_ICTLR_SIZE SZ_64
48
Erik Gillingc5f80062010-01-21 16:53:02 -080049#define TEGRA_TMR1_BASE 0x60005000
50#define TEGRA_TMR1_SIZE SZ_8
51
52#define TEGRA_TMR2_BASE 0x60005008
53#define TEGRA_TMR2_SIZE SZ_8
54
55#define TEGRA_TMRUS_BASE 0x60005010
56#define TEGRA_TMRUS_SIZE SZ_64
57
58#define TEGRA_TMR3_BASE 0x60005050
59#define TEGRA_TMR3_SIZE SZ_8
60
61#define TEGRA_TMR4_BASE 0x60005058
62#define TEGRA_TMR4_SIZE SZ_8
63
64#define TEGRA_CLK_RESET_BASE 0x60006000
65#define TEGRA_CLK_RESET_SIZE SZ_4K
66
67#define TEGRA_FLOW_CTRL_BASE 0x60007000
68#define TEGRA_FLOW_CTRL_SIZE 20
69
Peter De Schrijverb36ab972012-02-10 01:47:45 +020070#define TEGRA_SB_BASE 0x6000C200
71#define TEGRA_SB_SIZE 256
72
Erik Gillingc5f80062010-01-21 16:53:02 -080073#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000
74#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K
75
76#define TEGRA_APB_MISC_BASE 0x70000000
77#define TEGRA_APB_MISC_SIZE SZ_4K
78
Erik Gillingc5f80062010-01-21 16:53:02 -080079#define TEGRA_UARTA_BASE 0x70006000
80#define TEGRA_UARTA_SIZE SZ_64
81
82#define TEGRA_UARTB_BASE 0x70006040
83#define TEGRA_UARTB_SIZE SZ_64
84
85#define TEGRA_UARTC_BASE 0x70006200
86#define TEGRA_UARTC_SIZE SZ_256
87
88#define TEGRA_UARTD_BASE 0x70006300
89#define TEGRA_UARTD_SIZE SZ_256
90
91#define TEGRA_UARTE_BASE 0x70006400
92#define TEGRA_UARTE_SIZE SZ_256
93
Erik Gillingc5f80062010-01-21 16:53:02 -080094#define TEGRA_PMC_BASE 0x7000E400
95#define TEGRA_PMC_SIZE SZ_256
96
Erik Gillingc5f80062010-01-21 16:53:02 -080097#define TEGRA_EMC_BASE 0x7000F400
98#define TEGRA_EMC_SIZE SZ_1K
99
100#define TEGRA_FUSE_BASE 0x7000F800
101#define TEGRA_FUSE_SIZE SZ_1K
102
Joseph Loe9f62442013-08-12 17:40:06 +0800103#define TEGRA_EMC0_BASE 0x7001A000
104#define TEGRA_EMC0_SIZE SZ_2K
105
106#define TEGRA_EMC1_BASE 0x7001A800
107#define TEGRA_EMC1_SIZE SZ_2K
108
Joseph Lof0c4ac12013-10-11 17:58:38 +0800109#define TEGRA124_EMC_BASE 0x7001B000
110#define TEGRA124_EMC_SIZE SZ_2K
111
Erik Gillingc5f80062010-01-21 16:53:02 -0800112#define TEGRA_CSITE_BASE 0x70040000
113#define TEGRA_CSITE_SIZE SZ_256K
114
Rob Herring6c38e252012-02-10 21:22:00 -0600115/* On TEGRA, many peripherals are very closely packed in
116 * two 256MB io windows (that actually only use about 64KB
117 * at the start of each).
118 *
Stephen Warren6dee8202013-10-29 13:47:21 -0600119 * We will just map the first MMU section of each window (to minimize
Rob Herring6c38e252012-02-10 21:22:00 -0600120 * pt entries needed) and provide a macro to transform physical
121 * io addresses to an appropriate void __iomem *.
Rob Herring6c38e252012-02-10 21:22:00 -0600122 */
123
Rob Herring6c38e252012-02-10 21:22:00 -0600124#define IO_IRAM_PHYS 0x40000000
125#define IO_IRAM_VIRT IOMEM(0xFE400000)
126#define IO_IRAM_SIZE SZ_256K
127
Stephen Warren6dee8202013-10-29 13:47:21 -0600128#define IO_CPU_PHYS 0x50040000
129#define IO_CPU_VIRT IOMEM(0xFE440000)
Rob Herring6c38e252012-02-10 21:22:00 -0600130#define IO_CPU_SIZE SZ_16K
131
132#define IO_PPSB_PHYS 0x60000000
133#define IO_PPSB_VIRT IOMEM(0xFE200000)
Stephen Warren6dee8202013-10-29 13:47:21 -0600134#define IO_PPSB_SIZE SECTION_SIZE
Rob Herring6c38e252012-02-10 21:22:00 -0600135
136#define IO_APB_PHYS 0x70000000
Stephen Warren6dee8202013-10-29 13:47:21 -0600137#define IO_APB_VIRT IOMEM(0xFE000000)
138#define IO_APB_SIZE SECTION_SIZE
Rob Herring6c38e252012-02-10 21:22:00 -0600139
140#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz)))
141#define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst)))
142
143#define IO_TO_VIRT(n) ( \
144 IO_TO_VIRT_BETWEEN((n), IO_PPSB_PHYS, IO_PPSB_SIZE) ? \
145 IO_TO_VIRT_XLATE((n), IO_PPSB_PHYS, IO_PPSB_VIRT) : \
146 IO_TO_VIRT_BETWEEN((n), IO_APB_PHYS, IO_APB_SIZE) ? \
147 IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) : \
148 IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ? \
149 IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) : \
150 IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ? \
151 IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) : \
152 NULL)
153
154#define IO_ADDRESS(n) (IO_TO_VIRT(n))
155
Erik Gillingc5f80062010-01-21 16:53:02 -0800156#endif