Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 1 | /************************************************************************** |
| 2 | * |
Sinclair Yeh | 54fbde8 | 2015-07-29 12:38:02 -0700 | [diff] [blame] | 3 | * Copyright © 2009-2015 VMware, Inc., Palo Alto, CA., USA |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 4 | * All Rights Reserved. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the |
| 8 | * "Software"), to deal in the Software without restriction, including |
| 9 | * without limitation the rights to use, copy, modify, merge, publish, |
| 10 | * distribute, sub license, and/or sell copies of the Software, and to |
| 11 | * permit persons to whom the Software is furnished to do so, subject to |
| 12 | * the following conditions: |
| 13 | * |
| 14 | * The above copyright notice and this permission notice (including the |
| 15 | * next paragraph) shall be included in all copies or substantial portions |
| 16 | * of the Software. |
| 17 | * |
| 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| 21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| 22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| 23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| 24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 25 | * |
| 26 | **************************************************************************/ |
| 27 | |
| 28 | #include "vmwgfx_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 29 | #include <drm/drmP.h> |
| 30 | #include <drm/ttm/ttm_placement.h> |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 31 | |
Thomas Hellstrom | d80efd5 | 2015-08-10 10:39:35 -0700 | [diff] [blame] | 32 | struct vmw_temp_set_context { |
| 33 | SVGA3dCmdHeader header; |
| 34 | SVGA3dCmdDXTempSetContext body; |
| 35 | }; |
| 36 | |
Jakob Bornecrantz | 8e19a95 | 2010-01-30 03:38:06 +0000 | [diff] [blame] | 37 | bool vmw_fifo_have_3d(struct vmw_private *dev_priv) |
| 38 | { |
Thomas Hellstrom | b9eb1a6 | 2015-04-02 02:39:45 -0700 | [diff] [blame] | 39 | u32 __iomem *fifo_mem = dev_priv->mmio_virt; |
Jakob Bornecrantz | 8e19a95 | 2010-01-30 03:38:06 +0000 | [diff] [blame] | 40 | uint32_t fifo_min, hwversion; |
Thomas Hellstrom | ebd4c6f | 2011-11-28 13:19:08 +0100 | [diff] [blame] | 41 | const struct vmw_fifo_state *fifo = &dev_priv->fifo; |
Jakob Bornecrantz | 8e19a95 | 2010-01-30 03:38:06 +0000 | [diff] [blame] | 42 | |
Thomas Hellstrom | d8c08b2 | 2012-11-21 12:18:31 +0100 | [diff] [blame] | 43 | if (!(dev_priv->capabilities & SVGA_CAP_3D)) |
| 44 | return false; |
| 45 | |
| 46 | if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { |
| 47 | uint32_t result; |
| 48 | |
| 49 | if (!dev_priv->has_mob) |
| 50 | return false; |
| 51 | |
Thomas Hellstrom | 496eb6f | 2015-01-14 02:33:39 -0800 | [diff] [blame] | 52 | spin_lock(&dev_priv->cap_lock); |
Thomas Hellstrom | d8c08b2 | 2012-11-21 12:18:31 +0100 | [diff] [blame] | 53 | vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D); |
| 54 | result = vmw_read(dev_priv, SVGA_REG_DEV_CAP); |
Thomas Hellstrom | 496eb6f | 2015-01-14 02:33:39 -0800 | [diff] [blame] | 55 | spin_unlock(&dev_priv->cap_lock); |
Thomas Hellstrom | d8c08b2 | 2012-11-21 12:18:31 +0100 | [diff] [blame] | 56 | |
| 57 | return (result != 0); |
| 58 | } |
| 59 | |
Jakob Bornecrantz | d7e1958 | 2010-05-28 11:21:59 +0200 | [diff] [blame] | 60 | if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)) |
| 61 | return false; |
| 62 | |
Jakob Bornecrantz | 8e19a95 | 2010-01-30 03:38:06 +0000 | [diff] [blame] | 63 | fifo_min = ioread32(fifo_mem + SVGA_FIFO_MIN); |
| 64 | if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int)) |
| 65 | return false; |
| 66 | |
Thomas Hellstrom | ebd4c6f | 2011-11-28 13:19:08 +0100 | [diff] [blame] | 67 | hwversion = ioread32(fifo_mem + |
| 68 | ((fifo->capabilities & |
| 69 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ? |
| 70 | SVGA_FIFO_3D_HWVERSION_REVISED : |
| 71 | SVGA_FIFO_3D_HWVERSION)); |
| 72 | |
Jakob Bornecrantz | 8e19a95 | 2010-01-30 03:38:06 +0000 | [diff] [blame] | 73 | if (hwversion == 0) |
| 74 | return false; |
| 75 | |
Thomas Hellstrom | b7b7002 | 2011-10-04 20:13:23 +0200 | [diff] [blame] | 76 | if (hwversion < SVGA3D_HWVERSION_WS8_B1) |
Jakob Bornecrantz | 8e19a95 | 2010-01-30 03:38:06 +0000 | [diff] [blame] | 77 | return false; |
| 78 | |
Sinclair Yeh | c8261a9 | 2015-06-26 01:23:42 -0700 | [diff] [blame] | 79 | /* Legacy Display Unit does not support surfaces */ |
| 80 | if (dev_priv->active_display_unit == vmw_du_legacy) |
Jakob Bornecrantz | 01e8141 | 2011-10-04 20:13:24 +0200 | [diff] [blame] | 81 | return false; |
| 82 | |
Jakob Bornecrantz | 8e19a95 | 2010-01-30 03:38:06 +0000 | [diff] [blame] | 83 | return true; |
| 84 | } |
| 85 | |
Jakob Bornecrantz | d7e1958 | 2010-05-28 11:21:59 +0200 | [diff] [blame] | 86 | bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv) |
| 87 | { |
Thomas Hellstrom | b9eb1a6 | 2015-04-02 02:39:45 -0700 | [diff] [blame] | 88 | u32 __iomem *fifo_mem = dev_priv->mmio_virt; |
Jakob Bornecrantz | d7e1958 | 2010-05-28 11:21:59 +0200 | [diff] [blame] | 89 | uint32_t caps; |
| 90 | |
| 91 | if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)) |
| 92 | return false; |
| 93 | |
| 94 | caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES); |
| 95 | if (caps & SVGA_FIFO_CAP_PITCHLOCK) |
| 96 | return true; |
| 97 | |
| 98 | return false; |
| 99 | } |
| 100 | |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 101 | int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) |
| 102 | { |
Thomas Hellstrom | b9eb1a6 | 2015-04-02 02:39:45 -0700 | [diff] [blame] | 103 | u32 __iomem *fifo_mem = dev_priv->mmio_virt; |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 104 | uint32_t max; |
| 105 | uint32_t min; |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 106 | |
Thomas Hellstrom | d80efd5 | 2015-08-10 10:39:35 -0700 | [diff] [blame] | 107 | fifo->dx = false; |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 108 | fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE; |
| 109 | fifo->static_buffer = vmalloc(fifo->static_buffer_size); |
| 110 | if (unlikely(fifo->static_buffer == NULL)) |
| 111 | return -ENOMEM; |
| 112 | |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 113 | fifo->dynamic_buffer = NULL; |
| 114 | fifo->reserved_size = 0; |
| 115 | fifo->using_bounce_buffer = false; |
| 116 | |
Thomas Hellstrom | 85b9e48 | 2010-02-08 09:57:25 +0000 | [diff] [blame] | 117 | mutex_init(&fifo->fifo_mutex); |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 118 | init_rwsem(&fifo->rwsem); |
| 119 | |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 120 | DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH)); |
| 121 | DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT)); |
| 122 | DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL)); |
| 123 | |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 124 | dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); |
| 125 | dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); |
Thomas Hellstrom | 30c78bb | 2010-10-01 10:21:48 +0200 | [diff] [blame] | 126 | dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); |
Thomas Hellstrom | 153b3d5 | 2015-06-25 10:47:43 -0700 | [diff] [blame] | 127 | |
Sinclair Yeh | 8ce75f8 | 2015-07-08 21:20:39 -0700 | [diff] [blame] | 128 | vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE | |
| 129 | SVGA_REG_ENABLE_HIDE); |
Thomas Hellstrom | 153b3d5 | 2015-06-25 10:47:43 -0700 | [diff] [blame] | 130 | vmw_write(dev_priv, SVGA_REG_TRACES, 0); |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 131 | |
| 132 | min = 4; |
| 133 | if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO) |
| 134 | min = vmw_read(dev_priv, SVGA_REG_MEM_REGS); |
| 135 | min <<= 2; |
| 136 | |
| 137 | if (min < PAGE_SIZE) |
| 138 | min = PAGE_SIZE; |
| 139 | |
| 140 | iowrite32(min, fifo_mem + SVGA_FIFO_MIN); |
| 141 | iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX); |
| 142 | wmb(); |
| 143 | iowrite32(min, fifo_mem + SVGA_FIFO_NEXT_CMD); |
| 144 | iowrite32(min, fifo_mem + SVGA_FIFO_STOP); |
| 145 | iowrite32(0, fifo_mem + SVGA_FIFO_BUSY); |
| 146 | mb(); |
| 147 | |
| 148 | vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 149 | |
| 150 | max = ioread32(fifo_mem + SVGA_FIFO_MAX); |
| 151 | min = ioread32(fifo_mem + SVGA_FIFO_MIN); |
| 152 | fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES); |
| 153 | |
| 154 | DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n", |
| 155 | (unsigned int) max, |
| 156 | (unsigned int) min, |
| 157 | (unsigned int) fifo->capabilities); |
| 158 | |
Thomas Hellstrom | 6bcd8d3c | 2011-09-01 20:18:42 +0000 | [diff] [blame] | 159 | atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno); |
| 160 | iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE); |
| 161 | vmw_marker_queue_init(&fifo->marker_queue); |
Thomas Hellstrom | 153b3d5 | 2015-06-25 10:47:43 -0700 | [diff] [blame] | 162 | |
| 163 | return 0; |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 164 | } |
| 165 | |
Thomas Hellstrom | 496eb6f | 2015-01-14 02:33:39 -0800 | [diff] [blame] | 166 | void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason) |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 167 | { |
Thomas Hellstrom | b9eb1a6 | 2015-04-02 02:39:45 -0700 | [diff] [blame] | 168 | u32 __iomem *fifo_mem = dev_priv->mmio_virt; |
Thomas Hellstrom | 496eb6f | 2015-01-14 02:33:39 -0800 | [diff] [blame] | 169 | static DEFINE_SPINLOCK(ping_lock); |
| 170 | unsigned long irq_flags; |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 171 | |
Thomas Hellstrom | 496eb6f | 2015-01-14 02:33:39 -0800 | [diff] [blame] | 172 | /* |
| 173 | * The ping_lock is needed because we don't have an atomic |
| 174 | * test-and-set of the SVGA_FIFO_BUSY register. |
| 175 | */ |
| 176 | spin_lock_irqsave(&ping_lock, irq_flags); |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 177 | if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) { |
| 178 | iowrite32(1, fifo_mem + SVGA_FIFO_BUSY); |
| 179 | vmw_write(dev_priv, SVGA_REG_SYNC, reason); |
| 180 | } |
Thomas Hellstrom | 496eb6f | 2015-01-14 02:33:39 -0800 | [diff] [blame] | 181 | spin_unlock_irqrestore(&ping_lock, irq_flags); |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 182 | } |
| 183 | |
| 184 | void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) |
| 185 | { |
Thomas Hellstrom | b9eb1a6 | 2015-04-02 02:39:45 -0700 | [diff] [blame] | 186 | u32 __iomem *fifo_mem = dev_priv->mmio_virt; |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 187 | |
Thomas Hellstrom | f01ea0c | 2014-08-28 11:53:23 +0200 | [diff] [blame] | 188 | vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 189 | while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0) |
Thomas Hellstrom | f01ea0c | 2014-08-28 11:53:23 +0200 | [diff] [blame] | 190 | ; |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 191 | |
Thomas Hellstrom | 6bcd8d3c | 2011-09-01 20:18:42 +0000 | [diff] [blame] | 192 | dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE); |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 193 | |
| 194 | vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, |
| 195 | dev_priv->config_done_state); |
| 196 | vmw_write(dev_priv, SVGA_REG_ENABLE, |
| 197 | dev_priv->enable_state); |
Thomas Hellstrom | 30c78bb | 2010-10-01 10:21:48 +0200 | [diff] [blame] | 198 | vmw_write(dev_priv, SVGA_REG_TRACES, |
| 199 | dev_priv->traces_state); |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 200 | |
Thomas Hellstrom | 6bcd8d3c | 2011-09-01 20:18:42 +0000 | [diff] [blame] | 201 | vmw_marker_queue_takedown(&fifo->marker_queue); |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 202 | |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 203 | if (likely(fifo->static_buffer != NULL)) { |
| 204 | vfree(fifo->static_buffer); |
| 205 | fifo->static_buffer = NULL; |
| 206 | } |
| 207 | |
| 208 | if (likely(fifo->dynamic_buffer != NULL)) { |
| 209 | vfree(fifo->dynamic_buffer); |
| 210 | fifo->dynamic_buffer = NULL; |
| 211 | } |
| 212 | } |
| 213 | |
| 214 | static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes) |
| 215 | { |
Thomas Hellstrom | b9eb1a6 | 2015-04-02 02:39:45 -0700 | [diff] [blame] | 216 | u32 __iomem *fifo_mem = dev_priv->mmio_virt; |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 217 | uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX); |
| 218 | uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); |
| 219 | uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN); |
| 220 | uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP); |
| 221 | |
| 222 | return ((max - next_cmd) + (stop - min) <= bytes); |
| 223 | } |
| 224 | |
| 225 | static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv, |
| 226 | uint32_t bytes, bool interruptible, |
| 227 | unsigned long timeout) |
| 228 | { |
| 229 | int ret = 0; |
| 230 | unsigned long end_jiffies = jiffies + timeout; |
| 231 | DEFINE_WAIT(__wait); |
| 232 | |
| 233 | DRM_INFO("Fifo wait noirq.\n"); |
| 234 | |
| 235 | for (;;) { |
| 236 | prepare_to_wait(&dev_priv->fifo_queue, &__wait, |
| 237 | (interruptible) ? |
| 238 | TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); |
| 239 | if (!vmw_fifo_is_full(dev_priv, bytes)) |
| 240 | break; |
| 241 | if (time_after_eq(jiffies, end_jiffies)) { |
| 242 | ret = -EBUSY; |
| 243 | DRM_ERROR("SVGA device lockup.\n"); |
| 244 | break; |
| 245 | } |
| 246 | schedule_timeout(1); |
| 247 | if (interruptible && signal_pending(current)) { |
Thomas Hellstrom | 3d3a5b3 | 2009-12-08 12:59:34 +0100 | [diff] [blame] | 248 | ret = -ERESTARTSYS; |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 249 | break; |
| 250 | } |
| 251 | } |
| 252 | finish_wait(&dev_priv->fifo_queue, &__wait); |
| 253 | wake_up_all(&dev_priv->fifo_queue); |
| 254 | DRM_INFO("Fifo noirq exit.\n"); |
| 255 | return ret; |
| 256 | } |
| 257 | |
| 258 | static int vmw_fifo_wait(struct vmw_private *dev_priv, |
| 259 | uint32_t bytes, bool interruptible, |
| 260 | unsigned long timeout) |
| 261 | { |
| 262 | long ret = 1L; |
| 263 | unsigned long irq_flags; |
| 264 | |
| 265 | if (likely(!vmw_fifo_is_full(dev_priv, bytes))) |
| 266 | return 0; |
| 267 | |
| 268 | vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL); |
| 269 | if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK)) |
| 270 | return vmw_fifo_wait_noirq(dev_priv, bytes, |
| 271 | interruptible, timeout); |
| 272 | |
Thomas Hellstrom | 496eb6f | 2015-01-14 02:33:39 -0800 | [diff] [blame] | 273 | spin_lock(&dev_priv->waiter_lock); |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 274 | if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) { |
| 275 | spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); |
| 276 | outl(SVGA_IRQFLAG_FIFO_PROGRESS, |
| 277 | dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); |
Thomas Hellstrom | 57c5ee7 | 2011-10-10 12:23:26 +0200 | [diff] [blame] | 278 | dev_priv->irq_mask |= SVGA_IRQFLAG_FIFO_PROGRESS; |
| 279 | vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 280 | spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); |
| 281 | } |
Thomas Hellstrom | 496eb6f | 2015-01-14 02:33:39 -0800 | [diff] [blame] | 282 | spin_unlock(&dev_priv->waiter_lock); |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 283 | |
| 284 | if (interruptible) |
| 285 | ret = wait_event_interruptible_timeout |
| 286 | (dev_priv->fifo_queue, |
| 287 | !vmw_fifo_is_full(dev_priv, bytes), timeout); |
| 288 | else |
| 289 | ret = wait_event_timeout |
| 290 | (dev_priv->fifo_queue, |
| 291 | !vmw_fifo_is_full(dev_priv, bytes), timeout); |
| 292 | |
Thomas Hellstrom | 3d3a5b3 | 2009-12-08 12:59:34 +0100 | [diff] [blame] | 293 | if (unlikely(ret == 0)) |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 294 | ret = -EBUSY; |
| 295 | else if (likely(ret > 0)) |
| 296 | ret = 0; |
| 297 | |
Thomas Hellstrom | 496eb6f | 2015-01-14 02:33:39 -0800 | [diff] [blame] | 298 | spin_lock(&dev_priv->waiter_lock); |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 299 | if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) { |
| 300 | spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); |
Thomas Hellstrom | 57c5ee7 | 2011-10-10 12:23:26 +0200 | [diff] [blame] | 301 | dev_priv->irq_mask &= ~SVGA_IRQFLAG_FIFO_PROGRESS; |
| 302 | vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 303 | spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); |
| 304 | } |
Thomas Hellstrom | 496eb6f | 2015-01-14 02:33:39 -0800 | [diff] [blame] | 305 | spin_unlock(&dev_priv->waiter_lock); |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 306 | |
| 307 | return ret; |
| 308 | } |
| 309 | |
Jakob Bornecrantz | de12d44 | 2011-10-04 20:13:13 +0200 | [diff] [blame] | 310 | /** |
| 311 | * Reserve @bytes number of bytes in the fifo. |
| 312 | * |
| 313 | * This function will return NULL (error) on two conditions: |
| 314 | * If it timeouts waiting for fifo space, or if @bytes is larger than the |
| 315 | * available fifo space. |
| 316 | * |
| 317 | * Returns: |
| 318 | * Pointer to the fifo, or null on error (possible hardware hang). |
| 319 | */ |
Thomas Hellstrom | 3eab3d9 | 2015-06-25 11:57:56 -0700 | [diff] [blame] | 320 | static void *vmw_local_fifo_reserve(struct vmw_private *dev_priv, |
| 321 | uint32_t bytes) |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 322 | { |
| 323 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; |
Thomas Hellstrom | b9eb1a6 | 2015-04-02 02:39:45 -0700 | [diff] [blame] | 324 | u32 __iomem *fifo_mem = dev_priv->mmio_virt; |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 325 | uint32_t max; |
| 326 | uint32_t min; |
| 327 | uint32_t next_cmd; |
| 328 | uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE; |
| 329 | int ret; |
| 330 | |
Thomas Hellstrom | 85b9e48 | 2010-02-08 09:57:25 +0000 | [diff] [blame] | 331 | mutex_lock(&fifo_state->fifo_mutex); |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 332 | max = ioread32(fifo_mem + SVGA_FIFO_MAX); |
| 333 | min = ioread32(fifo_mem + SVGA_FIFO_MIN); |
| 334 | next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); |
| 335 | |
| 336 | if (unlikely(bytes >= (max - min))) |
| 337 | goto out_err; |
| 338 | |
| 339 | BUG_ON(fifo_state->reserved_size != 0); |
| 340 | BUG_ON(fifo_state->dynamic_buffer != NULL); |
| 341 | |
| 342 | fifo_state->reserved_size = bytes; |
| 343 | |
| 344 | while (1) { |
| 345 | uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP); |
| 346 | bool need_bounce = false; |
| 347 | bool reserve_in_place = false; |
| 348 | |
| 349 | if (next_cmd >= stop) { |
| 350 | if (likely((next_cmd + bytes < max || |
| 351 | (next_cmd + bytes == max && stop > min)))) |
| 352 | reserve_in_place = true; |
| 353 | |
| 354 | else if (vmw_fifo_is_full(dev_priv, bytes)) { |
| 355 | ret = vmw_fifo_wait(dev_priv, bytes, |
| 356 | false, 3 * HZ); |
| 357 | if (unlikely(ret != 0)) |
| 358 | goto out_err; |
| 359 | } else |
| 360 | need_bounce = true; |
| 361 | |
| 362 | } else { |
| 363 | |
| 364 | if (likely((next_cmd + bytes < stop))) |
| 365 | reserve_in_place = true; |
| 366 | else { |
| 367 | ret = vmw_fifo_wait(dev_priv, bytes, |
| 368 | false, 3 * HZ); |
| 369 | if (unlikely(ret != 0)) |
| 370 | goto out_err; |
| 371 | } |
| 372 | } |
| 373 | |
| 374 | if (reserve_in_place) { |
| 375 | if (reserveable || bytes <= sizeof(uint32_t)) { |
| 376 | fifo_state->using_bounce_buffer = false; |
| 377 | |
| 378 | if (reserveable) |
| 379 | iowrite32(bytes, fifo_mem + |
| 380 | SVGA_FIFO_RESERVED); |
Thomas Hellstrom | b9eb1a6 | 2015-04-02 02:39:45 -0700 | [diff] [blame] | 381 | return (void __force *) (fifo_mem + |
| 382 | (next_cmd >> 2)); |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 383 | } else { |
| 384 | need_bounce = true; |
| 385 | } |
| 386 | } |
| 387 | |
| 388 | if (need_bounce) { |
| 389 | fifo_state->using_bounce_buffer = true; |
| 390 | if (bytes < fifo_state->static_buffer_size) |
| 391 | return fifo_state->static_buffer; |
| 392 | else { |
| 393 | fifo_state->dynamic_buffer = vmalloc(bytes); |
| 394 | return fifo_state->dynamic_buffer; |
| 395 | } |
| 396 | } |
| 397 | } |
| 398 | out_err: |
| 399 | fifo_state->reserved_size = 0; |
Thomas Hellstrom | 85b9e48 | 2010-02-08 09:57:25 +0000 | [diff] [blame] | 400 | mutex_unlock(&fifo_state->fifo_mutex); |
Thomas Hellstrom | 3eab3d9 | 2015-06-25 11:57:56 -0700 | [diff] [blame] | 401 | |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 402 | return NULL; |
| 403 | } |
| 404 | |
Thomas Hellstrom | d80efd5 | 2015-08-10 10:39:35 -0700 | [diff] [blame] | 405 | void *vmw_fifo_reserve_dx(struct vmw_private *dev_priv, uint32_t bytes, |
| 406 | int ctx_id) |
Thomas Hellstrom | 3eab3d9 | 2015-06-25 11:57:56 -0700 | [diff] [blame] | 407 | { |
| 408 | void *ret; |
| 409 | |
| 410 | if (dev_priv->cman) |
| 411 | ret = vmw_cmdbuf_reserve(dev_priv->cman, bytes, |
Thomas Hellstrom | d80efd5 | 2015-08-10 10:39:35 -0700 | [diff] [blame] | 412 | ctx_id, false, NULL); |
| 413 | else if (ctx_id == SVGA3D_INVALID_ID) |
Thomas Hellstrom | 3eab3d9 | 2015-06-25 11:57:56 -0700 | [diff] [blame] | 414 | ret = vmw_local_fifo_reserve(dev_priv, bytes); |
Thomas Hellstrom | d80efd5 | 2015-08-10 10:39:35 -0700 | [diff] [blame] | 415 | else { |
| 416 | WARN_ON("Command buffer has not been allocated.\n"); |
| 417 | ret = NULL; |
| 418 | } |
Thomas Hellstrom | 3eab3d9 | 2015-06-25 11:57:56 -0700 | [diff] [blame] | 419 | if (IS_ERR_OR_NULL(ret)) { |
| 420 | DRM_ERROR("Fifo reserve failure of %u bytes.\n", |
| 421 | (unsigned) bytes); |
| 422 | dump_stack(); |
| 423 | return NULL; |
| 424 | } |
| 425 | |
| 426 | return ret; |
| 427 | } |
| 428 | |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 429 | static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state, |
Thomas Hellstrom | b9eb1a6 | 2015-04-02 02:39:45 -0700 | [diff] [blame] | 430 | u32 __iomem *fifo_mem, |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 431 | uint32_t next_cmd, |
| 432 | uint32_t max, uint32_t min, uint32_t bytes) |
| 433 | { |
| 434 | uint32_t chunk_size = max - next_cmd; |
| 435 | uint32_t rest; |
| 436 | uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ? |
| 437 | fifo_state->dynamic_buffer : fifo_state->static_buffer; |
| 438 | |
| 439 | if (bytes < chunk_size) |
| 440 | chunk_size = bytes; |
| 441 | |
| 442 | iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED); |
| 443 | mb(); |
| 444 | memcpy_toio(fifo_mem + (next_cmd >> 2), buffer, chunk_size); |
| 445 | rest = bytes - chunk_size; |
| 446 | if (rest) |
| 447 | memcpy_toio(fifo_mem + (min >> 2), buffer + (chunk_size >> 2), |
| 448 | rest); |
| 449 | } |
| 450 | |
| 451 | static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state, |
Thomas Hellstrom | b9eb1a6 | 2015-04-02 02:39:45 -0700 | [diff] [blame] | 452 | u32 __iomem *fifo_mem, |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 453 | uint32_t next_cmd, |
| 454 | uint32_t max, uint32_t min, uint32_t bytes) |
| 455 | { |
| 456 | uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ? |
| 457 | fifo_state->dynamic_buffer : fifo_state->static_buffer; |
| 458 | |
| 459 | while (bytes > 0) { |
| 460 | iowrite32(*buffer++, fifo_mem + (next_cmd >> 2)); |
| 461 | next_cmd += sizeof(uint32_t); |
| 462 | if (unlikely(next_cmd == max)) |
| 463 | next_cmd = min; |
| 464 | mb(); |
| 465 | iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD); |
| 466 | mb(); |
| 467 | bytes -= sizeof(uint32_t); |
| 468 | } |
| 469 | } |
| 470 | |
Thomas Hellstrom | b9eb1a6 | 2015-04-02 02:39:45 -0700 | [diff] [blame] | 471 | static void vmw_local_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes) |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 472 | { |
| 473 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; |
Thomas Hellstrom | b9eb1a6 | 2015-04-02 02:39:45 -0700 | [diff] [blame] | 474 | u32 __iomem *fifo_mem = dev_priv->mmio_virt; |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 475 | uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); |
| 476 | uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX); |
| 477 | uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN); |
| 478 | bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE; |
| 479 | |
Thomas Hellstrom | d80efd5 | 2015-08-10 10:39:35 -0700 | [diff] [blame] | 480 | if (fifo_state->dx) |
| 481 | bytes += sizeof(struct vmw_temp_set_context); |
| 482 | |
| 483 | fifo_state->dx = false; |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 484 | BUG_ON((bytes & 3) != 0); |
| 485 | BUG_ON(bytes > fifo_state->reserved_size); |
| 486 | |
| 487 | fifo_state->reserved_size = 0; |
| 488 | |
| 489 | if (fifo_state->using_bounce_buffer) { |
| 490 | if (reserveable) |
| 491 | vmw_fifo_res_copy(fifo_state, fifo_mem, |
| 492 | next_cmd, max, min, bytes); |
| 493 | else |
| 494 | vmw_fifo_slow_copy(fifo_state, fifo_mem, |
| 495 | next_cmd, max, min, bytes); |
| 496 | |
| 497 | if (fifo_state->dynamic_buffer) { |
| 498 | vfree(fifo_state->dynamic_buffer); |
| 499 | fifo_state->dynamic_buffer = NULL; |
| 500 | } |
| 501 | |
| 502 | } |
| 503 | |
Thomas Hellstrom | 85b9e48 | 2010-02-08 09:57:25 +0000 | [diff] [blame] | 504 | down_write(&fifo_state->rwsem); |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 505 | if (fifo_state->using_bounce_buffer || reserveable) { |
| 506 | next_cmd += bytes; |
| 507 | if (next_cmd >= max) |
| 508 | next_cmd -= max - min; |
| 509 | mb(); |
| 510 | iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD); |
| 511 | } |
| 512 | |
| 513 | if (reserveable) |
| 514 | iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED); |
| 515 | mb(); |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 516 | up_write(&fifo_state->rwsem); |
Thomas Hellstrom | 85b9e48 | 2010-02-08 09:57:25 +0000 | [diff] [blame] | 517 | vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC); |
| 518 | mutex_unlock(&fifo_state->fifo_mutex); |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 519 | } |
| 520 | |
Thomas Hellstrom | 3eab3d9 | 2015-06-25 11:57:56 -0700 | [diff] [blame] | 521 | void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes) |
| 522 | { |
| 523 | if (dev_priv->cman) |
| 524 | vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, false); |
| 525 | else |
| 526 | vmw_local_fifo_commit(dev_priv, bytes); |
| 527 | } |
| 528 | |
| 529 | |
| 530 | /** |
| 531 | * vmw_fifo_commit_flush - Commit fifo space and flush any buffered commands. |
| 532 | * |
| 533 | * @dev_priv: Pointer to device private structure. |
| 534 | * @bytes: Number of bytes to commit. |
| 535 | */ |
Thomas Hellstrom | d80efd5 | 2015-08-10 10:39:35 -0700 | [diff] [blame] | 536 | void vmw_fifo_commit_flush(struct vmw_private *dev_priv, uint32_t bytes) |
Thomas Hellstrom | 3eab3d9 | 2015-06-25 11:57:56 -0700 | [diff] [blame] | 537 | { |
| 538 | if (dev_priv->cman) |
| 539 | vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, true); |
| 540 | else |
| 541 | vmw_local_fifo_commit(dev_priv, bytes); |
| 542 | } |
| 543 | |
| 544 | /** |
| 545 | * vmw_fifo_flush - Flush any buffered commands and make sure command processing |
| 546 | * starts. |
| 547 | * |
| 548 | * @dev_priv: Pointer to device private structure. |
| 549 | * @interruptible: Whether to wait interruptible if function needs to sleep. |
| 550 | */ |
| 551 | int vmw_fifo_flush(struct vmw_private *dev_priv, bool interruptible) |
| 552 | { |
| 553 | might_sleep(); |
| 554 | |
| 555 | if (dev_priv->cman) |
| 556 | return vmw_cmdbuf_cur_flush(dev_priv->cman, interruptible); |
| 557 | else |
| 558 | return 0; |
| 559 | } |
| 560 | |
Thomas Hellstrom | 6bcd8d3c | 2011-09-01 20:18:42 +0000 | [diff] [blame] | 561 | int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno) |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 562 | { |
| 563 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; |
| 564 | struct svga_fifo_cmd_fence *cmd_fence; |
Thomas Hellstrom | b9eb1a6 | 2015-04-02 02:39:45 -0700 | [diff] [blame] | 565 | u32 *fm; |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 566 | int ret = 0; |
Thomas Hellstrom | b9eb1a6 | 2015-04-02 02:39:45 -0700 | [diff] [blame] | 567 | uint32_t bytes = sizeof(u32) + sizeof(*cmd_fence); |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 568 | |
| 569 | fm = vmw_fifo_reserve(dev_priv, bytes); |
| 570 | if (unlikely(fm == NULL)) { |
Thomas Hellstrom | 6bcd8d3c | 2011-09-01 20:18:42 +0000 | [diff] [blame] | 571 | *seqno = atomic_read(&dev_priv->marker_seq); |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 572 | ret = -ENOMEM; |
Thomas Hellstrom | 6bcd8d3c | 2011-09-01 20:18:42 +0000 | [diff] [blame] | 573 | (void)vmw_fallback_wait(dev_priv, false, true, *seqno, |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 574 | false, 3*HZ); |
| 575 | goto out_err; |
| 576 | } |
| 577 | |
| 578 | do { |
Thomas Hellstrom | 6bcd8d3c | 2011-09-01 20:18:42 +0000 | [diff] [blame] | 579 | *seqno = atomic_add_return(1, &dev_priv->marker_seq); |
| 580 | } while (*seqno == 0); |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 581 | |
| 582 | if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) { |
| 583 | |
| 584 | /* |
| 585 | * Don't request hardware to send a fence. The |
| 586 | * waiting code in vmwgfx_irq.c will emulate this. |
| 587 | */ |
| 588 | |
| 589 | vmw_fifo_commit(dev_priv, 0); |
| 590 | return 0; |
| 591 | } |
| 592 | |
Thomas Hellstrom | b9eb1a6 | 2015-04-02 02:39:45 -0700 | [diff] [blame] | 593 | *fm++ = SVGA_CMD_FENCE; |
| 594 | cmd_fence = (struct svga_fifo_cmd_fence *) fm; |
| 595 | cmd_fence->fence = *seqno; |
Thomas Hellstrom | 3eab3d9 | 2015-06-25 11:57:56 -0700 | [diff] [blame] | 596 | vmw_fifo_commit_flush(dev_priv, bytes); |
Thomas Hellstrom | 6bcd8d3c | 2011-09-01 20:18:42 +0000 | [diff] [blame] | 597 | (void) vmw_marker_push(&fifo_state->marker_queue, *seqno); |
| 598 | vmw_update_seqno(dev_priv, fifo_state); |
Jakob Bornecrantz | fb1d973 | 2009-12-10 00:19:58 +0000 | [diff] [blame] | 599 | |
| 600 | out_err: |
| 601 | return ret; |
| 602 | } |
Thomas Hellstrom | e2fa3a7 | 2011-10-04 20:13:30 +0200 | [diff] [blame] | 603 | |
| 604 | /** |
Thomas Hellstrom | ddcda24 | 2012-11-21 11:26:55 +0100 | [diff] [blame] | 605 | * vmw_fifo_emit_dummy_legacy_query - emits a dummy query to the fifo using |
| 606 | * legacy query commands. |
Thomas Hellstrom | e2fa3a7 | 2011-10-04 20:13:30 +0200 | [diff] [blame] | 607 | * |
| 608 | * @dev_priv: The device private structure. |
| 609 | * @cid: The hardware context id used for the query. |
| 610 | * |
Thomas Hellstrom | ddcda24 | 2012-11-21 11:26:55 +0100 | [diff] [blame] | 611 | * See the vmw_fifo_emit_dummy_query documentation. |
Thomas Hellstrom | e2fa3a7 | 2011-10-04 20:13:30 +0200 | [diff] [blame] | 612 | */ |
Thomas Hellstrom | ddcda24 | 2012-11-21 11:26:55 +0100 | [diff] [blame] | 613 | static int vmw_fifo_emit_dummy_legacy_query(struct vmw_private *dev_priv, |
| 614 | uint32_t cid) |
Thomas Hellstrom | e2fa3a7 | 2011-10-04 20:13:30 +0200 | [diff] [blame] | 615 | { |
| 616 | /* |
| 617 | * A query wait without a preceding query end will |
| 618 | * actually finish all queries for this cid |
| 619 | * without writing to the query result structure. |
| 620 | */ |
| 621 | |
Thomas Hellstrom | 459d0fa | 2015-06-26 00:25:37 -0700 | [diff] [blame] | 622 | struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base; |
Thomas Hellstrom | e2fa3a7 | 2011-10-04 20:13:30 +0200 | [diff] [blame] | 623 | struct { |
| 624 | SVGA3dCmdHeader header; |
| 625 | SVGA3dCmdWaitForQuery body; |
| 626 | } *cmd; |
| 627 | |
| 628 | cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd)); |
| 629 | |
| 630 | if (unlikely(cmd == NULL)) { |
| 631 | DRM_ERROR("Out of fifo space for dummy query.\n"); |
| 632 | return -ENOMEM; |
| 633 | } |
| 634 | |
| 635 | cmd->header.id = SVGA_3D_CMD_WAIT_FOR_QUERY; |
| 636 | cmd->header.size = sizeof(cmd->body); |
| 637 | cmd->body.cid = cid; |
| 638 | cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION; |
| 639 | |
| 640 | if (bo->mem.mem_type == TTM_PL_VRAM) { |
| 641 | cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER; |
| 642 | cmd->body.guestResult.offset = bo->offset; |
| 643 | } else { |
| 644 | cmd->body.guestResult.gmrId = bo->mem.start; |
| 645 | cmd->body.guestResult.offset = 0; |
| 646 | } |
| 647 | |
| 648 | vmw_fifo_commit(dev_priv, sizeof(*cmd)); |
| 649 | |
| 650 | return 0; |
| 651 | } |
Thomas Hellstrom | ddcda24 | 2012-11-21 11:26:55 +0100 | [diff] [blame] | 652 | |
| 653 | /** |
| 654 | * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using |
| 655 | * guest-backed resource query commands. |
| 656 | * |
| 657 | * @dev_priv: The device private structure. |
| 658 | * @cid: The hardware context id used for the query. |
| 659 | * |
| 660 | * See the vmw_fifo_emit_dummy_query documentation. |
| 661 | */ |
| 662 | static int vmw_fifo_emit_dummy_gb_query(struct vmw_private *dev_priv, |
| 663 | uint32_t cid) |
| 664 | { |
| 665 | /* |
| 666 | * A query wait without a preceding query end will |
| 667 | * actually finish all queries for this cid |
| 668 | * without writing to the query result structure. |
| 669 | */ |
| 670 | |
Thomas Hellstrom | 459d0fa | 2015-06-26 00:25:37 -0700 | [diff] [blame] | 671 | struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base; |
Thomas Hellstrom | ddcda24 | 2012-11-21 11:26:55 +0100 | [diff] [blame] | 672 | struct { |
| 673 | SVGA3dCmdHeader header; |
| 674 | SVGA3dCmdWaitForGBQuery body; |
| 675 | } *cmd; |
| 676 | |
| 677 | cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd)); |
| 678 | |
| 679 | if (unlikely(cmd == NULL)) { |
| 680 | DRM_ERROR("Out of fifo space for dummy query.\n"); |
| 681 | return -ENOMEM; |
| 682 | } |
| 683 | |
| 684 | cmd->header.id = SVGA_3D_CMD_WAIT_FOR_GB_QUERY; |
| 685 | cmd->header.size = sizeof(cmd->body); |
| 686 | cmd->body.cid = cid; |
| 687 | cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION; |
| 688 | BUG_ON(bo->mem.mem_type != VMW_PL_MOB); |
| 689 | cmd->body.mobid = bo->mem.start; |
| 690 | cmd->body.offset = 0; |
| 691 | |
| 692 | vmw_fifo_commit(dev_priv, sizeof(*cmd)); |
| 693 | |
| 694 | return 0; |
| 695 | } |
| 696 | |
| 697 | |
| 698 | /** |
| 699 | * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using |
| 700 | * appropriate resource query commands. |
| 701 | * |
| 702 | * @dev_priv: The device private structure. |
| 703 | * @cid: The hardware context id used for the query. |
| 704 | * |
| 705 | * This function is used to emit a dummy occlusion query with |
| 706 | * no primitives rendered between query begin and query end. |
| 707 | * It's used to provide a query barrier, in order to know that when |
| 708 | * this query is finished, all preceding queries are also finished. |
| 709 | * |
| 710 | * A Query results structure should have been initialized at the start |
| 711 | * of the dev_priv->dummy_query_bo buffer object. And that buffer object |
| 712 | * must also be either reserved or pinned when this function is called. |
| 713 | * |
| 714 | * Returns -ENOMEM on failure to reserve fifo space. |
| 715 | */ |
| 716 | int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv, |
| 717 | uint32_t cid) |
| 718 | { |
| 719 | if (dev_priv->has_mob) |
| 720 | return vmw_fifo_emit_dummy_gb_query(dev_priv, cid); |
| 721 | |
| 722 | return vmw_fifo_emit_dummy_legacy_query(dev_priv, cid); |
| 723 | } |
Thomas Hellstrom | d80efd5 | 2015-08-10 10:39:35 -0700 | [diff] [blame] | 724 | |
| 725 | void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes) |
| 726 | { |
| 727 | return vmw_fifo_reserve_dx(dev_priv, bytes, SVGA3D_INVALID_ID); |
| 728 | } |