blob: 95edcbd2aec64c0107e8dab5ca233706af65ca76 [file] [log] [blame]
Steve Birtles3ad09202008-02-09 04:49:55 +01001/*
2 * linux/arch/arm/mach-at91/board-yl-9200.c
3 *
Andrew Victore3ba22d2008-05-24 17:06:45 +01004 * Adapted from various board files in arch/arm/mach-at91
5 *
6 * Modifications for YL-9200 platform:
7 * Copyright (C) 2007 S. Birtles
Steve Birtles3ad09202008-02-09 04:49:55 +01008 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/types.h>
25#include <linux/init.h>
26#include <linux/mm.h>
27#include <linux/module.h>
Andrew Victore3ba22d2008-05-24 17:06:45 +010028#include <linux/dma-mapping.h>
Steve Birtles3ad09202008-02-09 04:49:55 +010029#include <linux/platform_device.h>
30#include <linux/spi/spi.h>
Steve Birtles3ad09202008-02-09 04:49:55 +010031#include <linux/spi/ads7846.h>
32#include <linux/mtd/physmap.h>
Andrew Victore3ba22d2008-05-24 17:06:45 +010033#include <linux/gpio_keys.h>
34#include <linux/input.h>
Steve Birtles3ad09202008-02-09 04:49:55 +010035
Steve Birtles3ad09202008-02-09 04:49:55 +010036#include <asm/setup.h>
37#include <asm/mach-types.h>
38#include <asm/irq.h>
39
40#include <asm/mach/arch.h>
41#include <asm/mach/map.h>
42#include <asm/mach/irq.h>
43
Andrew Victore5052402008-09-21 21:30:02 +010044#include <mach/hardware.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010045#include <mach/board.h>
46#include <mach/gpio.h>
47#include <mach/at91rm9200_mc.h>
Jean-Christophe PLAGNIOL-VILLARDe57556e32011-04-24 11:40:22 +080048#include <mach/cpu.h>
Steve Birtles3ad09202008-02-09 04:49:55 +010049
50#include "generic.h"
Steve Birtles3ad09202008-02-09 04:49:55 +010051
Steve Birtles3ad09202008-02-09 04:49:55 +010052
Jean-Christophe PLAGNIOL-VILLARD1b021a32011-04-28 20:19:32 +080053static void __init yl9200_init_early(void)
Steve Birtles3ad09202008-02-09 04:49:55 +010054{
Jean-Christophe PLAGNIOL-VILLARDe57556e32011-04-24 11:40:22 +080055 /* Set cpu type: PQFP */
56 at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
57
Steve Birtles3ad09202008-02-09 04:49:55 +010058 /* Initialize processor: 18.432 MHz crystal */
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +080059 at91_initialize(18432000);
Steve Birtles3ad09202008-02-09 04:49:55 +010060
Andrew Victore3ba22d2008-05-24 17:06:45 +010061 /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */
62 at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17);
Steve Birtles3ad09202008-02-09 04:49:55 +010063
Andrew Victore3ba22d2008-05-24 17:06:45 +010064 /* DBGU on ttyS0. (Rx & Tx only) */
65 at91_register_uart(0, 0, 0);
66
67 /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
68 at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
69 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
70 | ATMEL_UART_RI);
71
72 /* USART0 on ttyS2. (Rx & Tx only to JP3) */
73 at91_register_uart(AT91RM9200_ID_US0, 2, 0);
74
75 /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */
76 at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS);
77
78 /* set serial console to ttyS0 (ie, DBGU) */
79 at91_set_serial_console(0);
Steve Birtles3ad09202008-02-09 04:49:55 +010080}
81
Steve Birtles3ad09202008-02-09 04:49:55 +010082/*
Andrew Victore3ba22d2008-05-24 17:06:45 +010083 * LEDs
84 */
85static struct gpio_led yl9200_leds[] = {
86 { /* D2 */
87 .name = "led2",
88 .gpio = AT91_PIN_PB17,
89 .active_low = 1,
90 .default_trigger = "timer",
91 },
92 { /* D3 */
93 .name = "led3",
94 .gpio = AT91_PIN_PB16,
95 .active_low = 1,
96 .default_trigger = "heartbeat",
97 },
98 { /* D4 */
99 .name = "led4",
100 .gpio = AT91_PIN_PB15,
101 .active_low = 1,
102 },
103 { /* D5 */
104 .name = "led5",
105 .gpio = AT91_PIN_PB8,
106 .active_low = 1,
107 }
108};
109
110/*
111 * Ethernet
112 */
113static struct at91_eth_data __initdata yl9200_eth_data = {
114 .phy_irq_pin = AT91_PIN_PB28,
115 .is_rmii = 1,
116};
117
118/*
119 * USB Host
120 */
121static struct at91_usbh_data __initdata yl9200_usbh_data = {
122 .ports = 1, /* PQFP version of AT91RM9200 */
123};
124
125/*
126 * USB Device
127 */
128static struct at91_udc_data __initdata yl9200_udc_data = {
129 .pullup_pin = AT91_PIN_PC4,
130 .vbus_pin = AT91_PIN_PC5,
131 .pullup_active_low = 1, /* Active Low due to PNP transistor (pg 7) */
Steve Birtles3ad09202008-02-09 04:49:55 +0100132
133};
Andrew Victore3ba22d2008-05-24 17:06:45 +0100134
135/*
136 * MMC
137 */
138static struct at91_mmc_data __initdata yl9200_mmc_data = {
139 .det_pin = AT91_PIN_PB9,
140 // .wp_pin = ... not connected
Steve Birtles3ad09202008-02-09 04:49:55 +0100141 .wire4 = 1,
Steve Birtles3ad09202008-02-09 04:49:55 +0100142};
143
Andrew Victore3ba22d2008-05-24 17:06:45 +0100144/*
145 * NAND Flash
146 */
147static struct mtd_partition __initdata yl9200_nand_partition[] = {
Steve Birtles3ad09202008-02-09 04:49:55 +0100148 {
149 .name = "AT91 NAND partition 1, boot",
150 .offset = 0,
Andrew Victore5052402008-09-21 21:30:02 +0100151 .size = SZ_256K
Steve Birtles3ad09202008-02-09 04:49:55 +0100152 },
153 {
154 .name = "AT91 NAND partition 2, kernel",
Andrew Victore5052402008-09-21 21:30:02 +0100155 .offset = MTDPART_OFS_NXTBLK,
156 .size = (2 * SZ_1M) - SZ_256K
Steve Birtles3ad09202008-02-09 04:49:55 +0100157 },
158 {
159 .name = "AT91 NAND partition 3, filesystem",
Andrew Victore5052402008-09-21 21:30:02 +0100160 .offset = MTDPART_OFS_NXTBLK,
Steve Birtles3ad09202008-02-09 04:49:55 +0100161 .size = 14 * SZ_1M
162 },
163 {
164 .name = "AT91 NAND partition 4, storage",
Andrew Victore5052402008-09-21 21:30:02 +0100165 .offset = MTDPART_OFS_NXTBLK,
166 .size = SZ_16M
Steve Birtles3ad09202008-02-09 04:49:55 +0100167 },
168 {
169 .name = "AT91 NAND partition 5, ext-fs",
Andrew Victore5052402008-09-21 21:30:02 +0100170 .offset = MTDPART_OFS_NXTBLK,
171 .size = SZ_32M
Andrew Victore3ba22d2008-05-24 17:06:45 +0100172 }
Steve Birtles3ad09202008-02-09 04:49:55 +0100173};
174
175static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
176{
Andrew Victore3ba22d2008-05-24 17:06:45 +0100177 *num_partitions = ARRAY_SIZE(yl9200_nand_partition);
178 return yl9200_nand_partition;
Steve Birtles3ad09202008-02-09 04:49:55 +0100179}
180
David Woodhouseff877ea2008-07-25 10:40:14 -0400181static struct atmel_nand_data __initdata yl9200_nand_data = {
Andrew Victore3ba22d2008-05-24 17:06:45 +0100182 .ale = 6,
183 .cle = 7,
184 // .det_pin = ... not connected
185 .rdy_pin = AT91_PIN_PC14, /* R/!B (Sheet10) */
186 .enable_pin = AT91_PIN_PC15, /* !CE (Sheet10) */
Steve Birtles3ad09202008-02-09 04:49:55 +0100187 .partition_info = nand_partitions,
188};
189
Steve Birtles3ad09202008-02-09 04:49:55 +0100190/*
Andrew Victore3ba22d2008-05-24 17:06:45 +0100191 * NOR Flash
192 */
193#define YL9200_FLASH_BASE AT91_CHIPSELECT_0
Andrew Victore5052402008-09-21 21:30:02 +0100194#define YL9200_FLASH_SIZE SZ_16M
Steve Birtles3ad09202008-02-09 04:49:55 +0100195
Andrew Victore3ba22d2008-05-24 17:06:45 +0100196static struct mtd_partition yl9200_flash_partitions[] = {
Steve Birtles3ad09202008-02-09 04:49:55 +0100197 {
Andrew Victore3ba22d2008-05-24 17:06:45 +0100198 .name = "Bootloader",
Andrew Victore3ba22d2008-05-24 17:06:45 +0100199 .offset = 0,
Andrew Victore5052402008-09-21 21:30:02 +0100200 .size = SZ_256K,
Andrew Victore3ba22d2008-05-24 17:06:45 +0100201 .mask_flags = MTD_WRITEABLE, /* force read-only */
202 },
203 {
204 .name = "Kernel",
Andrew Victore5052402008-09-21 21:30:02 +0100205 .offset = MTDPART_OFS_NXTBLK,
206 .size = (2 * SZ_1M) - SZ_256K
Andrew Victore3ba22d2008-05-24 17:06:45 +0100207 },
208 {
209 .name = "Filesystem",
Andrew Victore5052402008-09-21 21:30:02 +0100210 .offset = MTDPART_OFS_NXTBLK,
211 .size = MTDPART_SIZ_FULL
Steve Birtles3ad09202008-02-09 04:49:55 +0100212 }
213};
214
Andrew Victore3ba22d2008-05-24 17:06:45 +0100215static struct physmap_flash_data yl9200_flash_data = {
216 .width = 2,
217 .parts = yl9200_flash_partitions,
218 .nr_parts = ARRAY_SIZE(yl9200_flash_partitions),
219};
220
221static struct resource yl9200_flash_resources[] = {
222 {
223 .start = YL9200_FLASH_BASE,
224 .end = YL9200_FLASH_BASE + YL9200_FLASH_SIZE - 1,
225 .flags = IORESOURCE_MEM,
226 }
227};
228
229static struct platform_device yl9200_flash = {
Steve Birtles3ad09202008-02-09 04:49:55 +0100230 .name = "physmap-flash",
231 .id = 0,
232 .dev = {
Andrew Victore3ba22d2008-05-24 17:06:45 +0100233 .platform_data = &yl9200_flash_data,
Steve Birtles3ad09202008-02-09 04:49:55 +0100234 },
Andrew Victore3ba22d2008-05-24 17:06:45 +0100235 .resource = yl9200_flash_resources,
236 .num_resources = ARRAY_SIZE(yl9200_flash_resources),
Steve Birtles3ad09202008-02-09 04:49:55 +0100237};
238
Andrew Victore3ba22d2008-05-24 17:06:45 +0100239/*
240 * I2C (TWI)
Steve Birtles3ad09202008-02-09 04:49:55 +0100241 */
Andrew Victore3ba22d2008-05-24 17:06:45 +0100242static struct i2c_board_info __initdata yl9200_i2c_devices[] = {
243 { /* EEPROM */
244 I2C_BOARD_INFO("24c128", 0x50),
245 }
246};
247
248/*
249 * GPIO Buttons
250*/
Steve Birtles3ad09202008-02-09 04:49:55 +0100251#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
Andrew Victore3ba22d2008-05-24 17:06:45 +0100252static struct gpio_keys_button yl9200_buttons[] = {
Steve Birtles3ad09202008-02-09 04:49:55 +0100253 {
254 .gpio = AT91_PIN_PA24,
Andrew Victore3ba22d2008-05-24 17:06:45 +0100255 .code = BTN_2,
Steve Birtles3ad09202008-02-09 04:49:55 +0100256 .desc = "SW2",
257 .active_low = 1,
258 .wakeup = 1,
259 },
260 {
261 .gpio = AT91_PIN_PB1,
Andrew Victore3ba22d2008-05-24 17:06:45 +0100262 .code = BTN_3,
Steve Birtles3ad09202008-02-09 04:49:55 +0100263 .desc = "SW3",
264 .active_low = 1,
265 .wakeup = 1,
266 },
267 {
268 .gpio = AT91_PIN_PB2,
Andrew Victore3ba22d2008-05-24 17:06:45 +0100269 .code = BTN_4,
Steve Birtles3ad09202008-02-09 04:49:55 +0100270 .desc = "SW4",
271 .active_low = 1,
272 .wakeup = 1,
273 },
274 {
275 .gpio = AT91_PIN_PB6,
Andrew Victore3ba22d2008-05-24 17:06:45 +0100276 .code = BTN_5,
Steve Birtles3ad09202008-02-09 04:49:55 +0100277 .desc = "SW5",
278 .active_low = 1,
279 .wakeup = 1,
Andrew Victore3ba22d2008-05-24 17:06:45 +0100280 }
Steve Birtles3ad09202008-02-09 04:49:55 +0100281};
282
Andrew Victore3ba22d2008-05-24 17:06:45 +0100283static struct gpio_keys_platform_data yl9200_button_data = {
284 .buttons = yl9200_buttons,
285 .nbuttons = ARRAY_SIZE(yl9200_buttons),
Steve Birtles3ad09202008-02-09 04:49:55 +0100286};
287
Andrew Victore3ba22d2008-05-24 17:06:45 +0100288static struct platform_device yl9200_button_device = {
Steve Birtles3ad09202008-02-09 04:49:55 +0100289 .name = "gpio-keys",
290 .id = -1,
291 .num_resources = 0,
292 .dev = {
Andrew Victore3ba22d2008-05-24 17:06:45 +0100293 .platform_data = &yl9200_button_data,
Steve Birtles3ad09202008-02-09 04:49:55 +0100294 }
295};
296
Andrew Victore3ba22d2008-05-24 17:06:45 +0100297static void __init yl9200_add_device_buttons(void)
Steve Birtles3ad09202008-02-09 04:49:55 +0100298{
Andrew Victore3ba22d2008-05-24 17:06:45 +0100299 at91_set_gpio_input(AT91_PIN_PA24, 1); /* SW2 */
Steve Birtles3ad09202008-02-09 04:49:55 +0100300 at91_set_deglitch(AT91_PIN_PA24, 1);
Andrew Victore3ba22d2008-05-24 17:06:45 +0100301 at91_set_gpio_input(AT91_PIN_PB1, 1); /* SW3 */
Steve Birtles3ad09202008-02-09 04:49:55 +0100302 at91_set_deglitch(AT91_PIN_PB1, 1);
Andrew Victore3ba22d2008-05-24 17:06:45 +0100303 at91_set_gpio_input(AT91_PIN_PB2, 1); /* SW4 */
Steve Birtles3ad09202008-02-09 04:49:55 +0100304 at91_set_deglitch(AT91_PIN_PB2, 1);
Andrew Victore3ba22d2008-05-24 17:06:45 +0100305 at91_set_gpio_input(AT91_PIN_PB6, 1); /* SW5 */
Steve Birtles3ad09202008-02-09 04:49:55 +0100306 at91_set_deglitch(AT91_PIN_PB6, 1);
307
Andrew Victore3ba22d2008-05-24 17:06:45 +0100308 /* Enable buttons (Sheet 5) */
309 at91_set_gpio_output(AT91_PIN_PB7, 1);
Steve Birtles3ad09202008-02-09 04:49:55 +0100310
Andrew Victore3ba22d2008-05-24 17:06:45 +0100311 platform_device_register(&yl9200_button_device);
Steve Birtles3ad09202008-02-09 04:49:55 +0100312}
313#else
Andrew Victore3ba22d2008-05-24 17:06:45 +0100314static void __init yl9200_add_device_buttons(void) {}
Steve Birtles3ad09202008-02-09 04:49:55 +0100315#endif
316
Andrew Victore3ba22d2008-05-24 17:06:45 +0100317/*
318 * Touchscreen
319 */
320#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
321static int ads7843_pendown_state(void)
322{
323 return !at91_get_gpio_value(AT91_PIN_PB11); /* Touchscreen PENIRQ */
324}
325
326static struct ads7846_platform_data ads_info = {
327 .model = 7843,
328 .x_min = 150,
329 .x_max = 3830,
330 .y_min = 190,
331 .y_max = 3830,
332 .vref_delay_usecs = 100,
333
334 /* For a 8" touch-screen */
335 // .x_plate_ohms = 603,
336 // .y_plate_ohms = 332,
337
338 /* For a 10.4" touch-screen */
339 // .x_plate_ohms = 611,
340 // .y_plate_ohms = 325,
341
342 .x_plate_ohms = 576,
343 .y_plate_ohms = 366,
344
345 .pressure_max = 15000, /* generally nonsense on the 7843 */
346 .debounce_max = 1,
347 .debounce_rep = 0,
348 .debounce_tol = (~0),
349 .get_pendown_state = ads7843_pendown_state,
350};
351
352static void __init yl9200_add_device_ts(void)
353{
354 at91_set_gpio_input(AT91_PIN_PB11, 1); /* Touchscreen interrupt pin */
355 at91_set_gpio_input(AT91_PIN_PB10, 1); /* Touchscreen BUSY signal - not used! */
356}
357#else
358static void __init yl9200_add_device_ts(void) {}
359#endif
360
361/*
362 * SPI devices
363 */
364static struct spi_board_info yl9200_spi_devices[] = {
365#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
366 { /* Touchscreen */
367 .modalias = "ads7846",
368 .chip_select = 0,
369 .max_speed_hz = 5000 * 26,
370 .platform_data = &ads_info,
371 .irq = AT91_PIN_PB11,
372 },
373#endif
374 { /* CAN */
375 .modalias = "mcp2510",
376 .chip_select = 1,
377 .max_speed_hz = 25000 * 26,
378 .irq = AT91_PIN_PC0,
379 }
380};
381
382/*
383 * LCD / VGA
384 *
385 * EPSON S1D13806 FB (discontinued chip)
386 * EPSON S1D13506 FB
387 */
Jean-Christophe PLAGNIOL-VILLARD3b24f092010-11-21 11:24:07 +0800388#if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE)
Steve Birtles3ad09202008-02-09 04:49:55 +0100389#include <video/s1d13xxxfb.h>
390
Steve Birtles3ad09202008-02-09 04:49:55 +0100391
Andrew Victore3ba22d2008-05-24 17:06:45 +0100392static void __init yl9200_init_video(void)
Steve Birtles3ad09202008-02-09 04:49:55 +0100393{
Andrew Victore3ba22d2008-05-24 17:06:45 +0100394 /* NWAIT Signal */
395 at91_set_A_periph(AT91_PIN_PC6, 0);
Steve Birtles3ad09202008-02-09 04:49:55 +0100396
Andrew Victore3ba22d2008-05-24 17:06:45 +0100397 /* Initialization of the Static Memory Controller for Chip Select 2 */
398 at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
399 | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4) /* wait states */
400 | AT91_SMC_TDF_(0x100) /* float time */
Steve Birtles3ad09202008-02-09 04:49:55 +0100401 );
Steve Birtles3ad09202008-02-09 04:49:55 +0100402}
403
Andrew Victore3ba22d2008-05-24 17:06:45 +0100404static struct s1d13xxxfb_regval yl9200_s1dfb_initregs[] =
Steve Birtles3ad09202008-02-09 04:49:55 +0100405{
Andrew Victore3ba22d2008-05-24 17:06:45 +0100406 {S1DREG_MISC, 0x00}, /* Miscellaneous Register*/
407 {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
408 {S1DREG_GPIO_CNF0, 0x00}, /* General IO Pins Configuration Register*/
409 {S1DREG_GPIO_CTL0, 0x00}, /* General IO Pins Control Register*/
410 {S1DREG_CLK_CNF, 0x11}, /* Memory Clock Configuration Register*/
411 {S1DREG_LCD_CLK_CNF, 0x10}, /* LCD Pixel Clock Configuration Register*/
412 {S1DREG_CRT_CLK_CNF, 0x12}, /* CRT/TV Pixel Clock Configuration Register*/
413 {S1DREG_MPLUG_CLK_CNF, 0x01}, /* MediaPlug Clock Configuration Register*/
414 {S1DREG_CPU2MEM_WST_SEL, 0x02}, /* CPU To Memory Wait State Select Register*/
415 {S1DREG_MEM_CNF, 0x00}, /* Memory Configuration Register*/
416 {S1DREG_SDRAM_REF_RATE, 0x04}, /* DRAM Refresh Rate Register, MCLK source*/
417 {S1DREG_SDRAM_TC0, 0x12}, /* DRAM Timings Control Register 0*/
418 {S1DREG_SDRAM_TC1, 0x02}, /* DRAM Timings Control Register 1*/
419 {S1DREG_PANEL_TYPE, 0x25}, /* Panel Type Register*/
420 {S1DREG_MOD_RATE, 0x00}, /* MOD Rate Register*/
421 {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* LCD Horizontal Display Width Register*/
422 {S1DREG_LCD_NDISP_HPER, 0x13}, /* LCD Horizontal Non-Display Period Register*/
423 {S1DREG_TFT_FPLINE_START, 0x01}, /* TFT FPLINE Start Position Register*/
424 {S1DREG_TFT_FPLINE_PWIDTH, 0x0c}, /* TFT FPLINE Pulse Width Register*/
425 {S1DREG_LCD_DISP_VHEIGHT0, 0xDF}, /* LCD Vertical Display Height Register 0*/
426 {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* LCD Vertical Display Height Register 1*/
427 {S1DREG_LCD_NDISP_VPER, 0x2c}, /* LCD Vertical Non-Display Period Register*/
428 {S1DREG_TFT_FPFRAME_START, 0x0a}, /* TFT FPFRAME Start Position Register*/
429 {S1DREG_TFT_FPFRAME_PWIDTH, 0x02}, /* TFT FPFRAME Pulse Width Register*/
430 {S1DREG_LCD_DISP_MODE, 0x05}, /* LCD Display Mode Register*/
431 {S1DREG_LCD_MISC, 0x01}, /* LCD Miscellaneous Register*/
432 {S1DREG_LCD_DISP_START0, 0x00}, /* LCD Display Start Address Register 0*/
433 {S1DREG_LCD_DISP_START1, 0x00}, /* LCD Display Start Address Register 1*/
434 {S1DREG_LCD_DISP_START2, 0x00}, /* LCD Display Start Address Register 2*/
435 {S1DREG_LCD_MEM_OFF0, 0x80}, /* LCD Memory Address Offset Register 0*/
436 {S1DREG_LCD_MEM_OFF1, 0x02}, /* LCD Memory Address Offset Register 1*/
437 {S1DREG_LCD_PIX_PAN, 0x03}, /* LCD Pixel Panning Register*/
438 {S1DREG_LCD_DISP_FIFO_HTC, 0x00}, /* LCD Display FIFO High Threshold Control Register*/
439 {S1DREG_LCD_DISP_FIFO_LTC, 0x00}, /* LCD Display FIFO Low Threshold Control Register*/
440 {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* CRT/TV Horizontal Display Width Register*/
441 {S1DREG_CRT_NDISP_HPER, 0x13}, /* CRT/TV Horizontal Non-Display Period Register*/
442 {S1DREG_CRT_HRTC_START, 0x01}, /* CRT/TV HRTC Start Position Register*/
443 {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* CRT/TV HRTC Pulse Width Register*/
444 {S1DREG_CRT_DISP_VHEIGHT0, 0xDF}, /* CRT/TV Vertical Display Height Register 0*/
445 {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* CRT/TV Vertical Display Height Register 1*/
446 {S1DREG_CRT_NDISP_VPER, 0x2B}, /* CRT/TV Vertical Non-Display Period Register*/
447 {S1DREG_CRT_VRTC_START, 0x09}, /* CRT/TV VRTC Start Position Register*/
448 {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* CRT/TV VRTC Pulse Width Register*/
449 {S1DREG_TV_OUT_CTL, 0x18}, /* TV Output Control Register */
450 {S1DREG_CRT_DISP_MODE, 0x05}, /* CRT/TV Display Mode Register, 16BPP*/
451 {S1DREG_CRT_DISP_START0, 0x00}, /* CRT/TV Display Start Address Register 0*/
452 {S1DREG_CRT_DISP_START1, 0x00}, /* CRT/TV Display Start Address Register 1*/
453 {S1DREG_CRT_DISP_START2, 0x00}, /* CRT/TV Display Start Address Register 2*/
454 {S1DREG_CRT_MEM_OFF0, 0x80}, /* CRT/TV Memory Address Offset Register 0*/
455 {S1DREG_CRT_MEM_OFF1, 0x02}, /* CRT/TV Memory Address Offset Register 1*/
456 {S1DREG_CRT_PIX_PAN, 0x00}, /* CRT/TV Pixel Panning Register*/
457 {S1DREG_CRT_DISP_FIFO_HTC, 0x00}, /* CRT/TV Display FIFO High Threshold Control Register*/
458 {S1DREG_CRT_DISP_FIFO_LTC, 0x00}, /* CRT/TV Display FIFO Low Threshold Control Register*/
459 {S1DREG_LCD_CUR_CTL, 0x00}, /* LCD Ink/Cursor Control Register*/
460 {S1DREG_LCD_CUR_START, 0x01}, /* LCD Ink/Cursor Start Address Register*/
461 {S1DREG_LCD_CUR_XPOS0, 0x00}, /* LCD Cursor X Position Register 0*/
462 {S1DREG_LCD_CUR_XPOS1, 0x00}, /* LCD Cursor X Position Register 1*/
463 {S1DREG_LCD_CUR_YPOS0, 0x00}, /* LCD Cursor Y Position Register 0*/
464 {S1DREG_LCD_CUR_YPOS1, 0x00}, /* LCD Cursor Y Position Register 1*/
465 {S1DREG_LCD_CUR_BCTL0, 0x00}, /* LCD Ink/Cursor Blue Color 0 Register*/
466 {S1DREG_LCD_CUR_GCTL0, 0x00}, /* LCD Ink/Cursor Green Color 0 Register*/
467 {S1DREG_LCD_CUR_RCTL0, 0x00}, /* LCD Ink/Cursor Red Color 0 Register*/
468 {S1DREG_LCD_CUR_BCTL1, 0x1F}, /* LCD Ink/Cursor Blue Color 1 Register*/
469 {S1DREG_LCD_CUR_GCTL1, 0x3F}, /* LCD Ink/Cursor Green Color 1 Register*/
470 {S1DREG_LCD_CUR_RCTL1, 0x1F}, /* LCD Ink/Cursor Red Color 1 Register*/
471 {S1DREG_LCD_CUR_FIFO_HTC, 0x00}, /* LCD Ink/Cursor FIFO Threshold Register*/
472 {S1DREG_CRT_CUR_CTL, 0x00}, /* CRT/TV Ink/Cursor Control Register*/
473 {S1DREG_CRT_CUR_START, 0x01}, /* CRT/TV Ink/Cursor Start Address Register*/
474 {S1DREG_CRT_CUR_XPOS0, 0x00}, /* CRT/TV Cursor X Position Register 0*/
475 {S1DREG_CRT_CUR_XPOS1, 0x00}, /* CRT/TV Cursor X Position Register 1*/
476 {S1DREG_CRT_CUR_YPOS0, 0x00}, /* CRT/TV Cursor Y Position Register 0*/
477 {S1DREG_CRT_CUR_YPOS1, 0x00}, /* CRT/TV Cursor Y Position Register 1*/
478 {S1DREG_CRT_CUR_BCTL0, 0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register*/
479 {S1DREG_CRT_CUR_GCTL0, 0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register*/
480 {S1DREG_CRT_CUR_RCTL0, 0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register*/
481 {S1DREG_CRT_CUR_BCTL1, 0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register*/
482 {S1DREG_CRT_CUR_GCTL1, 0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register*/
483 {S1DREG_CRT_CUR_RCTL1, 0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register*/
484 {S1DREG_CRT_CUR_FIFO_HTC, 0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register*/
485 {S1DREG_BBLT_CTL0, 0x00}, /* BitBlt Control Register 0*/
486 {S1DREG_BBLT_CTL1, 0x01}, /* BitBlt Control Register 1*/
487 {S1DREG_BBLT_CC_EXP, 0x00}, /* BitBlt ROP Code/Color Expansion Register*/
488 {S1DREG_BBLT_OP, 0x00}, /* BitBlt Operation Register*/
489 {S1DREG_BBLT_SRC_START0, 0x00}, /* BitBlt Source Start Address Register 0*/
490 {S1DREG_BBLT_SRC_START1, 0x00}, /* BitBlt Source Start Address Register 1*/
491 {S1DREG_BBLT_SRC_START2, 0x00}, /* BitBlt Source Start Address Register 2*/
492 {S1DREG_BBLT_DST_START0, 0x00}, /* BitBlt Destination Start Address Register 0*/
493 {S1DREG_BBLT_DST_START1, 0x00}, /* BitBlt Destination Start Address Register 1*/
494 {S1DREG_BBLT_DST_START2, 0x00}, /* BitBlt Destination Start Address Register 2*/
495 {S1DREG_BBLT_MEM_OFF0, 0x00}, /* BitBlt Memory Address Offset Register 0*/
496 {S1DREG_BBLT_MEM_OFF1, 0x00}, /* BitBlt Memory Address Offset Register 1*/
497 {S1DREG_BBLT_WIDTH0, 0x00}, /* BitBlt Width Register 0*/
498 {S1DREG_BBLT_WIDTH1, 0x00}, /* BitBlt Width Register 1*/
499 {S1DREG_BBLT_HEIGHT0, 0x00}, /* BitBlt Height Register 0*/
500 {S1DREG_BBLT_HEIGHT1, 0x00}, /* BitBlt Height Register 1*/
501 {S1DREG_BBLT_BGC0, 0x00}, /* BitBlt Background Color Register 0*/
502 {S1DREG_BBLT_BGC1, 0x00}, /* BitBlt Background Color Register 1*/
503 {S1DREG_BBLT_FGC0, 0x00}, /* BitBlt Foreground Color Register 0*/
504 {S1DREG_BBLT_FGC1, 0x00}, /* BitBlt Foreground Color Register 1*/
505 {S1DREG_LKUP_MODE, 0x00}, /* Look-Up Table Mode Register*/
506 {S1DREG_LKUP_ADDR, 0x00}, /* Look-Up Table Address Register*/
507 {S1DREG_PS_CNF, 0x00}, /* Power Save Configuration Register*/
508 {S1DREG_PS_STATUS, 0x00}, /* Power Save Status Register*/
509 {S1DREG_CPU2MEM_WDOGT, 0x00}, /* CPU-to-Memory Access Watchdog Timer Register*/
510 {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
Steve Birtles3ad09202008-02-09 04:49:55 +0100511};
512
Andrew Victore3ba22d2008-05-24 17:06:45 +0100513static struct s1d13xxxfb_pdata yl9200_s1dfb_pdata = {
514 .initregs = yl9200_s1dfb_initregs,
515 .initregssize = ARRAY_SIZE(yl9200_s1dfb_initregs),
516 .platform_init_video = yl9200_init_video,
Steve Birtles3ad09202008-02-09 04:49:55 +0100517};
518
Andrew Victore5052402008-09-21 21:30:02 +0100519#define YL9200_FB_REG_BASE AT91_CHIPSELECT_7
520#define YL9200_FB_VMEM_BASE YL9200_FB_REG_BASE + SZ_2M
521#define YL9200_FB_VMEM_SIZE SZ_2M
522
Andrew Victore3ba22d2008-05-24 17:06:45 +0100523static struct resource yl9200_s1dfb_resource[] = {
Steve Birtles3ad09202008-02-09 04:49:55 +0100524 [0] = { /* video mem */
Andrew Victore3ba22d2008-05-24 17:06:45 +0100525 .name = "s1d13xxxfb memory",
Andrew Victore5052402008-09-21 21:30:02 +0100526 .start = YL9200_FB_VMEM_BASE,
527 .end = YL9200_FB_VMEM_BASE + YL9200_FB_VMEM_SIZE -1,
Andrew Victore3ba22d2008-05-24 17:06:45 +0100528 .flags = IORESOURCE_MEM,
Steve Birtles3ad09202008-02-09 04:49:55 +0100529 },
530 [1] = { /* video registers */
Andrew Victore3ba22d2008-05-24 17:06:45 +0100531 .name = "s1d13xxxfb registers",
Andrew Victore5052402008-09-21 21:30:02 +0100532 .start = YL9200_FB_REG_BASE,
533 .end = YL9200_FB_REG_BASE + SZ_512 -1,
Andrew Victore3ba22d2008-05-24 17:06:45 +0100534 .flags = IORESOURCE_MEM,
Steve Birtles3ad09202008-02-09 04:49:55 +0100535 },
536};
537
Andrew Victore5052402008-09-21 21:30:02 +0100538static u64 s1dfb_dmamask = DMA_BIT_MASK(32);
539
Andrew Victore3ba22d2008-05-24 17:06:45 +0100540static struct platform_device yl9200_s1dfb_device = {
541 .name = "s1d13806fb",
542 .id = -1,
543 .dev = {
Steve Birtles3ad09202008-02-09 04:49:55 +0100544 .dma_mask = &s1dfb_dmamask,
Andrew Victore3ba22d2008-05-24 17:06:45 +0100545 .coherent_dma_mask = DMA_BIT_MASK(32),
546 .platform_data = &yl9200_s1dfb_pdata,
Steve Birtles3ad09202008-02-09 04:49:55 +0100547 },
Andrew Victore3ba22d2008-05-24 17:06:45 +0100548 .resource = yl9200_s1dfb_resource,
549 .num_resources = ARRAY_SIZE(yl9200_s1dfb_resource),
Steve Birtles3ad09202008-02-09 04:49:55 +0100550};
551
Andrew Victore3ba22d2008-05-24 17:06:45 +0100552void __init yl9200_add_device_video(void)
Steve Birtles3ad09202008-02-09 04:49:55 +0100553{
Andrew Victore3ba22d2008-05-24 17:06:45 +0100554 platform_device_register(&yl9200_s1dfb_device);
Steve Birtles3ad09202008-02-09 04:49:55 +0100555}
556#else
Andrew Victore3ba22d2008-05-24 17:06:45 +0100557void __init yl9200_add_device_video(void) {}
Steve Birtles3ad09202008-02-09 04:49:55 +0100558#endif
559
Andrew Victore3ba22d2008-05-24 17:06:45 +0100560
561static void __init yl9200_board_init(void)
Steve Birtles3ad09202008-02-09 04:49:55 +0100562{
563 /* Serial */
564 at91_add_device_serial();
565 /* Ethernet */
Andrew Victore3ba22d2008-05-24 17:06:45 +0100566 at91_add_device_eth(&yl9200_eth_data);
Steve Birtles3ad09202008-02-09 04:49:55 +0100567 /* USB Host */
Andrew Victore3ba22d2008-05-24 17:06:45 +0100568 at91_add_device_usbh(&yl9200_usbh_data);
Steve Birtles3ad09202008-02-09 04:49:55 +0100569 /* USB Device */
Andrew Victore3ba22d2008-05-24 17:06:45 +0100570 at91_add_device_udc(&yl9200_udc_data);
Steve Birtles3ad09202008-02-09 04:49:55 +0100571 /* I2C */
Andrew Victore3ba22d2008-05-24 17:06:45 +0100572 at91_add_device_i2c(yl9200_i2c_devices, ARRAY_SIZE(yl9200_i2c_devices));
573 /* MMC */
574 at91_add_device_mmc(0, &yl9200_mmc_data);
Steve Birtles3ad09202008-02-09 04:49:55 +0100575 /* NAND */
Andrew Victore3ba22d2008-05-24 17:06:45 +0100576 at91_add_device_nand(&yl9200_nand_data);
Steve Birtles3ad09202008-02-09 04:49:55 +0100577 /* NOR Flash */
Andrew Victore3ba22d2008-05-24 17:06:45 +0100578 platform_device_register(&yl9200_flash);
579#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
580 /* SPI */
581 at91_add_device_spi(yl9200_spi_devices, ARRAY_SIZE(yl9200_spi_devices));
582 /* Touchscreen */
583 yl9200_add_device_ts();
584#endif
585 /* LEDs. */
586 at91_gpio_leds(yl9200_leds, ARRAY_SIZE(yl9200_leds));
Steve Birtles3ad09202008-02-09 04:49:55 +0100587 /* Push Buttons */
Andrew Victore3ba22d2008-05-24 17:06:45 +0100588 yl9200_add_device_buttons();
589 /* VGA */
590 yl9200_add_device_video();
Steve Birtles3ad09202008-02-09 04:49:55 +0100591}
592
593MACHINE_START(YL9200, "uCdragon YL-9200")
Andrew Victore3ba22d2008-05-24 17:06:45 +0100594 /* Maintainer: S.Birtles */
Andrew Victore3ba22d2008-05-24 17:06:45 +0100595 .timer = &at91rm9200_timer,
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +0800596 .map_io = at91_map_io,
Jean-Christophe PLAGNIOL-VILLARD1b021a32011-04-28 20:19:32 +0800597 .init_early = yl9200_init_early,
Jean-Christophe PLAGNIOL-VILLARD92100c12011-04-23 15:28:34 +0800598 .init_irq = at91_init_irq_default,
Andrew Victore3ba22d2008-05-24 17:06:45 +0100599 .init_machine = yl9200_board_init,
Steve Birtles3ad09202008-02-09 04:49:55 +0100600MACHINE_END