blob: 02dbbb300929e35458fd3a60a42e04e98a3ab6d6 [file] [log] [blame]
Divy Le Ray4d22de32007-01-18 22:04:14 -05001#define A_SG_CONTROL 0x0
2
Divy Le Rayb8819552007-12-17 18:47:31 -08003#define S_CONGMODE 29
4#define V_CONGMODE(x) ((x) << S_CONGMODE)
5#define F_CONGMODE V_CONGMODE(1U)
6
7#define S_TNLFLMODE 28
8#define V_TNLFLMODE(x) ((x) << S_TNLFLMODE)
9#define F_TNLFLMODE V_TNLFLMODE(1U)
10
11#define S_FATLPERREN 27
12#define V_FATLPERREN(x) ((x) << S_FATLPERREN)
13#define F_FATLPERREN V_FATLPERREN(1U)
14
Divy Le Ray4d22de32007-01-18 22:04:14 -050015#define S_DROPPKT 20
16#define V_DROPPKT(x) ((x) << S_DROPPKT)
17#define F_DROPPKT V_DROPPKT(1U)
18
19#define S_EGRGENCTRL 19
20#define V_EGRGENCTRL(x) ((x) << S_EGRGENCTRL)
21#define F_EGRGENCTRL V_EGRGENCTRL(1U)
22
23#define S_USERSPACESIZE 14
24#define M_USERSPACESIZE 0x1f
25#define V_USERSPACESIZE(x) ((x) << S_USERSPACESIZE)
26
27#define S_HOSTPAGESIZE 11
28#define M_HOSTPAGESIZE 0x7
29#define V_HOSTPAGESIZE(x) ((x) << S_HOSTPAGESIZE)
30
31#define S_FLMODE 9
32#define V_FLMODE(x) ((x) << S_FLMODE)
33#define F_FLMODE V_FLMODE(1U)
34
35#define S_PKTSHIFT 6
36#define M_PKTSHIFT 0x7
37#define V_PKTSHIFT(x) ((x) << S_PKTSHIFT)
38
39#define S_ONEINTMULTQ 5
40#define V_ONEINTMULTQ(x) ((x) << S_ONEINTMULTQ)
41#define F_ONEINTMULTQ V_ONEINTMULTQ(1U)
42
43#define S_BIGENDIANINGRESS 2
44#define V_BIGENDIANINGRESS(x) ((x) << S_BIGENDIANINGRESS)
45#define F_BIGENDIANINGRESS V_BIGENDIANINGRESS(1U)
46
47#define S_ISCSICOALESCING 1
48#define V_ISCSICOALESCING(x) ((x) << S_ISCSICOALESCING)
49#define F_ISCSICOALESCING V_ISCSICOALESCING(1U)
50
51#define S_GLOBALENABLE 0
52#define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE)
53#define F_GLOBALENABLE V_GLOBALENABLE(1U)
54
55#define S_AVOIDCQOVFL 24
56#define V_AVOIDCQOVFL(x) ((x) << S_AVOIDCQOVFL)
57#define F_AVOIDCQOVFL V_AVOIDCQOVFL(1U)
58
59#define S_OPTONEINTMULTQ 23
60#define V_OPTONEINTMULTQ(x) ((x) << S_OPTONEINTMULTQ)
61#define F_OPTONEINTMULTQ V_OPTONEINTMULTQ(1U)
62
63#define S_CQCRDTCTRL 22
64#define V_CQCRDTCTRL(x) ((x) << S_CQCRDTCTRL)
65#define F_CQCRDTCTRL V_CQCRDTCTRL(1U)
66
67#define A_SG_KDOORBELL 0x4
68
69#define S_SELEGRCNTX 31
70#define V_SELEGRCNTX(x) ((x) << S_SELEGRCNTX)
71#define F_SELEGRCNTX V_SELEGRCNTX(1U)
72
73#define S_EGRCNTX 0
74#define M_EGRCNTX 0xffff
75#define V_EGRCNTX(x) ((x) << S_EGRCNTX)
76
77#define A_SG_GTS 0x8
78
79#define S_RSPQ 29
80#define M_RSPQ 0x7
81#define V_RSPQ(x) ((x) << S_RSPQ)
82#define G_RSPQ(x) (((x) >> S_RSPQ) & M_RSPQ)
83
84#define S_NEWTIMER 16
85#define M_NEWTIMER 0x1fff
86#define V_NEWTIMER(x) ((x) << S_NEWTIMER)
87
88#define S_NEWINDEX 0
89#define M_NEWINDEX 0xffff
90#define V_NEWINDEX(x) ((x) << S_NEWINDEX)
91
92#define A_SG_CONTEXT_CMD 0xc
93
94#define S_CONTEXT_CMD_OPCODE 28
95#define M_CONTEXT_CMD_OPCODE 0xf
96#define V_CONTEXT_CMD_OPCODE(x) ((x) << S_CONTEXT_CMD_OPCODE)
97
98#define S_CONTEXT_CMD_BUSY 27
99#define V_CONTEXT_CMD_BUSY(x) ((x) << S_CONTEXT_CMD_BUSY)
100#define F_CONTEXT_CMD_BUSY V_CONTEXT_CMD_BUSY(1U)
101
102#define S_CQ_CREDIT 20
103
104#define M_CQ_CREDIT 0x7f
105
106#define V_CQ_CREDIT(x) ((x) << S_CQ_CREDIT)
107
108#define G_CQ_CREDIT(x) (((x) >> S_CQ_CREDIT) & M_CQ_CREDIT)
109
110#define S_CQ 19
111
112#define V_CQ(x) ((x) << S_CQ)
113#define F_CQ V_CQ(1U)
114
115#define S_RESPONSEQ 18
116#define V_RESPONSEQ(x) ((x) << S_RESPONSEQ)
117#define F_RESPONSEQ V_RESPONSEQ(1U)
118
119#define S_EGRESS 17
120#define V_EGRESS(x) ((x) << S_EGRESS)
121#define F_EGRESS V_EGRESS(1U)
122
123#define S_FREELIST 16
124#define V_FREELIST(x) ((x) << S_FREELIST)
125#define F_FREELIST V_FREELIST(1U)
126
127#define S_CONTEXT 0
128#define M_CONTEXT 0xffff
129#define V_CONTEXT(x) ((x) << S_CONTEXT)
130
131#define G_CONTEXT(x) (((x) >> S_CONTEXT) & M_CONTEXT)
132
133#define A_SG_CONTEXT_DATA0 0x10
134
135#define A_SG_CONTEXT_DATA1 0x14
136
137#define A_SG_CONTEXT_DATA2 0x18
138
139#define A_SG_CONTEXT_DATA3 0x1c
140
141#define A_SG_CONTEXT_MASK0 0x20
142
143#define A_SG_CONTEXT_MASK1 0x24
144
145#define A_SG_CONTEXT_MASK2 0x28
146
147#define A_SG_CONTEXT_MASK3 0x2c
148
149#define A_SG_RSPQ_CREDIT_RETURN 0x30
150
151#define S_CREDITS 0
152#define M_CREDITS 0xffff
153#define V_CREDITS(x) ((x) << S_CREDITS)
154
155#define A_SG_DATA_INTR 0x34
156
157#define S_ERRINTR 31
158#define V_ERRINTR(x) ((x) << S_ERRINTR)
159#define F_ERRINTR V_ERRINTR(1U)
160
161#define A_SG_HI_DRB_HI_THRSH 0x38
162
163#define A_SG_HI_DRB_LO_THRSH 0x3c
164
165#define A_SG_LO_DRB_HI_THRSH 0x40
166
167#define A_SG_LO_DRB_LO_THRSH 0x44
168
169#define A_SG_RSPQ_FL_STATUS 0x4c
170
171#define S_RSPQ0DISABLED 8
172
173#define A_SG_EGR_RCQ_DRB_THRSH 0x54
174
175#define S_HIRCQDRBTHRSH 16
176#define M_HIRCQDRBTHRSH 0x7ff
177#define V_HIRCQDRBTHRSH(x) ((x) << S_HIRCQDRBTHRSH)
178
179#define S_LORCQDRBTHRSH 0
180#define M_LORCQDRBTHRSH 0x7ff
181#define V_LORCQDRBTHRSH(x) ((x) << S_LORCQDRBTHRSH)
182
183#define A_SG_EGR_CNTX_BADDR 0x58
184
185#define A_SG_INT_CAUSE 0x5c
186
Divy Le Rayb8819552007-12-17 18:47:31 -0800187#define S_HIRCQPARITYERROR 31
188#define V_HIRCQPARITYERROR(x) ((x) << S_HIRCQPARITYERROR)
189#define F_HIRCQPARITYERROR V_HIRCQPARITYERROR(1U)
190
191#define S_LORCQPARITYERROR 30
192#define V_LORCQPARITYERROR(x) ((x) << S_LORCQPARITYERROR)
193#define F_LORCQPARITYERROR V_LORCQPARITYERROR(1U)
194
195#define S_HIDRBPARITYERROR 29
196#define V_HIDRBPARITYERROR(x) ((x) << S_HIDRBPARITYERROR)
197#define F_HIDRBPARITYERROR V_HIDRBPARITYERROR(1U)
198
199#define S_LODRBPARITYERROR 28
200#define V_LODRBPARITYERROR(x) ((x) << S_LODRBPARITYERROR)
201#define F_LODRBPARITYERROR V_LODRBPARITYERROR(1U)
202
203#define S_FLPARITYERROR 22
204#define M_FLPARITYERROR 0x3f
205#define V_FLPARITYERROR(x) ((x) << S_FLPARITYERROR)
206#define G_FLPARITYERROR(x) (((x) >> S_FLPARITYERROR) & M_FLPARITYERROR)
207
208#define S_ITPARITYERROR 20
209#define M_ITPARITYERROR 0x3
210#define V_ITPARITYERROR(x) ((x) << S_ITPARITYERROR)
211#define G_ITPARITYERROR(x) (((x) >> S_ITPARITYERROR) & M_ITPARITYERROR)
212
213#define S_IRPARITYERROR 19
214#define V_IRPARITYERROR(x) ((x) << S_IRPARITYERROR)
215#define F_IRPARITYERROR V_IRPARITYERROR(1U)
216
217#define S_RCPARITYERROR 18
218#define V_RCPARITYERROR(x) ((x) << S_RCPARITYERROR)
219#define F_RCPARITYERROR V_RCPARITYERROR(1U)
220
221#define S_OCPARITYERROR 17
222#define V_OCPARITYERROR(x) ((x) << S_OCPARITYERROR)
223#define F_OCPARITYERROR V_OCPARITYERROR(1U)
224
225#define S_CPPARITYERROR 16
226#define V_CPPARITYERROR(x) ((x) << S_CPPARITYERROR)
227#define F_CPPARITYERROR V_CPPARITYERROR(1U)
228
229#define S_R_REQ_FRAMINGERROR 15
230#define V_R_REQ_FRAMINGERROR(x) ((x) << S_R_REQ_FRAMINGERROR)
231#define F_R_REQ_FRAMINGERROR V_R_REQ_FRAMINGERROR(1U)
232
233#define S_UC_REQ_FRAMINGERROR 14
234#define V_UC_REQ_FRAMINGERROR(x) ((x) << S_UC_REQ_FRAMINGERROR)
235#define F_UC_REQ_FRAMINGERROR V_UC_REQ_FRAMINGERROR(1U)
236
237#define S_HICTLDRBDROPERR 13
238#define V_HICTLDRBDROPERR(x) ((x) << S_HICTLDRBDROPERR)
239#define F_HICTLDRBDROPERR V_HICTLDRBDROPERR(1U)
240
241#define S_LOCTLDRBDROPERR 12
242#define V_LOCTLDRBDROPERR(x) ((x) << S_LOCTLDRBDROPERR)
243#define F_LOCTLDRBDROPERR V_LOCTLDRBDROPERR(1U)
244
Divy Le Ray6e3f03b2007-08-21 20:49:10 -0700245#define S_HIPIODRBDROPERR 11
246#define V_HIPIODRBDROPERR(x) ((x) << S_HIPIODRBDROPERR)
247#define F_HIPIODRBDROPERR V_HIPIODRBDROPERR(1U)
248
249#define S_LOPIODRBDROPERR 10
250#define V_LOPIODRBDROPERR(x) ((x) << S_LOPIODRBDROPERR)
251#define F_LOPIODRBDROPERR V_LOPIODRBDROPERR(1U)
252
Divy Le Ray4d22de32007-01-18 22:04:14 -0500253#define S_RSPQDISABLED 3
254#define V_RSPQDISABLED(x) ((x) << S_RSPQDISABLED)
255#define F_RSPQDISABLED V_RSPQDISABLED(1U)
256
257#define S_RSPQCREDITOVERFOW 2
258#define V_RSPQCREDITOVERFOW(x) ((x) << S_RSPQCREDITOVERFOW)
259#define F_RSPQCREDITOVERFOW V_RSPQCREDITOVERFOW(1U)
260
261#define A_SG_INT_ENABLE 0x60
262
263#define A_SG_CMDQ_CREDIT_TH 0x64
264
265#define S_TIMEOUT 8
266#define M_TIMEOUT 0xffffff
267#define V_TIMEOUT(x) ((x) << S_TIMEOUT)
268
269#define S_THRESHOLD 0
270#define M_THRESHOLD 0xff
271#define V_THRESHOLD(x) ((x) << S_THRESHOLD)
272
273#define A_SG_TIMER_TICK 0x68
274
275#define A_SG_CQ_CONTEXT_BADDR 0x6c
276
277#define A_SG_OCO_BASE 0x70
278
279#define S_BASE1 16
280#define M_BASE1 0xffff
281#define V_BASE1(x) ((x) << S_BASE1)
282
283#define A_SG_DRB_PRI_THRESH 0x74
284
285#define A_PCIX_INT_ENABLE 0x80
286
287#define S_MSIXPARERR 22
288#define M_MSIXPARERR 0x7
289
290#define V_MSIXPARERR(x) ((x) << S_MSIXPARERR)
291
292#define S_CFPARERR 18
293#define M_CFPARERR 0xf
294
295#define V_CFPARERR(x) ((x) << S_CFPARERR)
296
297#define S_RFPARERR 14
298#define M_RFPARERR 0xf
299
300#define V_RFPARERR(x) ((x) << S_RFPARERR)
301
302#define S_WFPARERR 12
303#define M_WFPARERR 0x3
304
305#define V_WFPARERR(x) ((x) << S_WFPARERR)
306
307#define S_PIOPARERR 11
308#define V_PIOPARERR(x) ((x) << S_PIOPARERR)
309#define F_PIOPARERR V_PIOPARERR(1U)
310
311#define S_DETUNCECCERR 10
312#define V_DETUNCECCERR(x) ((x) << S_DETUNCECCERR)
313#define F_DETUNCECCERR V_DETUNCECCERR(1U)
314
315#define S_DETCORECCERR 9
316#define V_DETCORECCERR(x) ((x) << S_DETCORECCERR)
317#define F_DETCORECCERR V_DETCORECCERR(1U)
318
319#define S_RCVSPLCMPERR 8
320#define V_RCVSPLCMPERR(x) ((x) << S_RCVSPLCMPERR)
321#define F_RCVSPLCMPERR V_RCVSPLCMPERR(1U)
322
323#define S_UNXSPLCMP 7
324#define V_UNXSPLCMP(x) ((x) << S_UNXSPLCMP)
325#define F_UNXSPLCMP V_UNXSPLCMP(1U)
326
327#define S_SPLCMPDIS 6
328#define V_SPLCMPDIS(x) ((x) << S_SPLCMPDIS)
329#define F_SPLCMPDIS V_SPLCMPDIS(1U)
330
331#define S_DETPARERR 5
332#define V_DETPARERR(x) ((x) << S_DETPARERR)
333#define F_DETPARERR V_DETPARERR(1U)
334
335#define S_SIGSYSERR 4
336#define V_SIGSYSERR(x) ((x) << S_SIGSYSERR)
337#define F_SIGSYSERR V_SIGSYSERR(1U)
338
339#define S_RCVMSTABT 3
340#define V_RCVMSTABT(x) ((x) << S_RCVMSTABT)
341#define F_RCVMSTABT V_RCVMSTABT(1U)
342
343#define S_RCVTARABT 2
344#define V_RCVTARABT(x) ((x) << S_RCVTARABT)
345#define F_RCVTARABT V_RCVTARABT(1U)
346
347#define S_SIGTARABT 1
348#define V_SIGTARABT(x) ((x) << S_SIGTARABT)
349#define F_SIGTARABT V_SIGTARABT(1U)
350
351#define S_MSTDETPARERR 0
352#define V_MSTDETPARERR(x) ((x) << S_MSTDETPARERR)
353#define F_MSTDETPARERR V_MSTDETPARERR(1U)
354
355#define A_PCIX_INT_CAUSE 0x84
356
357#define A_PCIX_CFG 0x88
358
Divy Le Rayb8819552007-12-17 18:47:31 -0800359#define S_DMASTOPEN 19
360#define V_DMASTOPEN(x) ((x) << S_DMASTOPEN)
361#define F_DMASTOPEN V_DMASTOPEN(1U)
362
Divy Le Ray4d22de32007-01-18 22:04:14 -0500363#define S_CLIDECEN 18
364#define V_CLIDECEN(x) ((x) << S_CLIDECEN)
365#define F_CLIDECEN V_CLIDECEN(1U)
366
367#define A_PCIX_MODE 0x8c
368
369#define S_PCLKRANGE 6
370#define M_PCLKRANGE 0x3
371#define V_PCLKRANGE(x) ((x) << S_PCLKRANGE)
372#define G_PCLKRANGE(x) (((x) >> S_PCLKRANGE) & M_PCLKRANGE)
373
374#define S_PCIXINITPAT 2
375#define M_PCIXINITPAT 0xf
376#define V_PCIXINITPAT(x) ((x) << S_PCIXINITPAT)
377#define G_PCIXINITPAT(x) (((x) >> S_PCIXINITPAT) & M_PCIXINITPAT)
378
379#define S_64BIT 0
380#define V_64BIT(x) ((x) << S_64BIT)
381#define F_64BIT V_64BIT(1U)
382
383#define A_PCIE_INT_ENABLE 0x80
384
385#define S_BISTERR 15
386#define M_BISTERR 0xff
387
388#define V_BISTERR(x) ((x) << S_BISTERR)
389
Divy Le Rayb8819552007-12-17 18:47:31 -0800390#define S_TXPARERR 18
391#define V_TXPARERR(x) ((x) << S_TXPARERR)
392#define F_TXPARERR V_TXPARERR(1U)
393
394#define S_RXPARERR 17
395#define V_RXPARERR(x) ((x) << S_RXPARERR)
396#define F_RXPARERR V_RXPARERR(1U)
397
398#define S_RETRYLUTPARERR 16
399#define V_RETRYLUTPARERR(x) ((x) << S_RETRYLUTPARERR)
400#define F_RETRYLUTPARERR V_RETRYLUTPARERR(1U)
401
402#define S_RETRYBUFPARERR 15
403#define V_RETRYBUFPARERR(x) ((x) << S_RETRYBUFPARERR)
404#define F_RETRYBUFPARERR V_RETRYBUFPARERR(1U)
405
Divy Le Ray4d22de32007-01-18 22:04:14 -0500406#define S_PCIE_MSIXPARERR 12
407#define M_PCIE_MSIXPARERR 0x7
408
409#define V_PCIE_MSIXPARERR(x) ((x) << S_PCIE_MSIXPARERR)
410
411#define S_PCIE_CFPARERR 11
412#define V_PCIE_CFPARERR(x) ((x) << S_PCIE_CFPARERR)
413#define F_PCIE_CFPARERR V_PCIE_CFPARERR(1U)
414
415#define S_PCIE_RFPARERR 10
416#define V_PCIE_RFPARERR(x) ((x) << S_PCIE_RFPARERR)
417#define F_PCIE_RFPARERR V_PCIE_RFPARERR(1U)
418
419#define S_PCIE_WFPARERR 9
420#define V_PCIE_WFPARERR(x) ((x) << S_PCIE_WFPARERR)
421#define F_PCIE_WFPARERR V_PCIE_WFPARERR(1U)
422
423#define S_PCIE_PIOPARERR 8
424#define V_PCIE_PIOPARERR(x) ((x) << S_PCIE_PIOPARERR)
425#define F_PCIE_PIOPARERR V_PCIE_PIOPARERR(1U)
426
427#define S_UNXSPLCPLERRC 7
428#define V_UNXSPLCPLERRC(x) ((x) << S_UNXSPLCPLERRC)
429#define F_UNXSPLCPLERRC V_UNXSPLCPLERRC(1U)
430
431#define S_UNXSPLCPLERRR 6
432#define V_UNXSPLCPLERRR(x) ((x) << S_UNXSPLCPLERRR)
433#define F_UNXSPLCPLERRR V_UNXSPLCPLERRR(1U)
434
435#define S_PEXERR 0
436#define V_PEXERR(x) ((x) << S_PEXERR)
437#define F_PEXERR V_PEXERR(1U)
438
439#define A_PCIE_INT_CAUSE 0x84
440
Divy Le Rayb8819552007-12-17 18:47:31 -0800441#define S_PCIE_DMASTOPEN 24
442#define V_PCIE_DMASTOPEN(x) ((x) << S_PCIE_DMASTOPEN)
443#define F_PCIE_DMASTOPEN V_PCIE_DMASTOPEN(1U)
444
Divy Le Ray4d22de32007-01-18 22:04:14 -0500445#define A_PCIE_CFG 0x88
446
447#define S_PCIE_CLIDECEN 16
448#define V_PCIE_CLIDECEN(x) ((x) << S_PCIE_CLIDECEN)
449#define F_PCIE_CLIDECEN V_PCIE_CLIDECEN(1U)
450
451#define S_CRSTWRMMODE 0
452#define V_CRSTWRMMODE(x) ((x) << S_CRSTWRMMODE)
453#define F_CRSTWRMMODE V_CRSTWRMMODE(1U)
454
455#define A_PCIE_MODE 0x8c
456
457#define S_NUMFSTTRNSEQRX 10
458#define M_NUMFSTTRNSEQRX 0xff
459#define V_NUMFSTTRNSEQRX(x) ((x) << S_NUMFSTTRNSEQRX)
460#define G_NUMFSTTRNSEQRX(x) (((x) >> S_NUMFSTTRNSEQRX) & M_NUMFSTTRNSEQRX)
461
462#define A_PCIE_PEX_CTRL0 0x98
463
464#define S_NUMFSTTRNSEQ 22
465#define M_NUMFSTTRNSEQ 0xff
466#define V_NUMFSTTRNSEQ(x) ((x) << S_NUMFSTTRNSEQ)
467#define G_NUMFSTTRNSEQ(x) (((x) >> S_NUMFSTTRNSEQ) & M_NUMFSTTRNSEQ)
468
469#define S_REPLAYLMT 2
470#define M_REPLAYLMT 0xfffff
471
472#define V_REPLAYLMT(x) ((x) << S_REPLAYLMT)
473
474#define A_PCIE_PEX_CTRL1 0x9c
475
476#define S_T3A_ACKLAT 0
477#define M_T3A_ACKLAT 0x7ff
478
479#define V_T3A_ACKLAT(x) ((x) << S_T3A_ACKLAT)
480
481#define S_ACKLAT 0
482#define M_ACKLAT 0x1fff
483
484#define V_ACKLAT(x) ((x) << S_ACKLAT)
485
486#define A_PCIE_PEX_ERR 0xa4
487
488#define A_T3DBG_GPIO_EN 0xd0
489
490#define S_GPIO11_OEN 27
491#define V_GPIO11_OEN(x) ((x) << S_GPIO11_OEN)
492#define F_GPIO11_OEN V_GPIO11_OEN(1U)
493
494#define S_GPIO10_OEN 26
495#define V_GPIO10_OEN(x) ((x) << S_GPIO10_OEN)
496#define F_GPIO10_OEN V_GPIO10_OEN(1U)
497
498#define S_GPIO7_OEN 23
499#define V_GPIO7_OEN(x) ((x) << S_GPIO7_OEN)
500#define F_GPIO7_OEN V_GPIO7_OEN(1U)
501
502#define S_GPIO6_OEN 22
503#define V_GPIO6_OEN(x) ((x) << S_GPIO6_OEN)
504#define F_GPIO6_OEN V_GPIO6_OEN(1U)
505
506#define S_GPIO5_OEN 21
507#define V_GPIO5_OEN(x) ((x) << S_GPIO5_OEN)
508#define F_GPIO5_OEN V_GPIO5_OEN(1U)
509
510#define S_GPIO4_OEN 20
511#define V_GPIO4_OEN(x) ((x) << S_GPIO4_OEN)
512#define F_GPIO4_OEN V_GPIO4_OEN(1U)
513
514#define S_GPIO2_OEN 18
515#define V_GPIO2_OEN(x) ((x) << S_GPIO2_OEN)
516#define F_GPIO2_OEN V_GPIO2_OEN(1U)
517
518#define S_GPIO1_OEN 17
519#define V_GPIO1_OEN(x) ((x) << S_GPIO1_OEN)
520#define F_GPIO1_OEN V_GPIO1_OEN(1U)
521
522#define S_GPIO0_OEN 16
523#define V_GPIO0_OEN(x) ((x) << S_GPIO0_OEN)
524#define F_GPIO0_OEN V_GPIO0_OEN(1U)
525
526#define S_GPIO10_OUT_VAL 10
527#define V_GPIO10_OUT_VAL(x) ((x) << S_GPIO10_OUT_VAL)
528#define F_GPIO10_OUT_VAL V_GPIO10_OUT_VAL(1U)
529
530#define S_GPIO7_OUT_VAL 7
531#define V_GPIO7_OUT_VAL(x) ((x) << S_GPIO7_OUT_VAL)
532#define F_GPIO7_OUT_VAL V_GPIO7_OUT_VAL(1U)
533
534#define S_GPIO6_OUT_VAL 6
535#define V_GPIO6_OUT_VAL(x) ((x) << S_GPIO6_OUT_VAL)
536#define F_GPIO6_OUT_VAL V_GPIO6_OUT_VAL(1U)
537
538#define S_GPIO5_OUT_VAL 5
539#define V_GPIO5_OUT_VAL(x) ((x) << S_GPIO5_OUT_VAL)
540#define F_GPIO5_OUT_VAL V_GPIO5_OUT_VAL(1U)
541
542#define S_GPIO4_OUT_VAL 4
543#define V_GPIO4_OUT_VAL(x) ((x) << S_GPIO4_OUT_VAL)
544#define F_GPIO4_OUT_VAL V_GPIO4_OUT_VAL(1U)
545
546#define S_GPIO2_OUT_VAL 2
547#define V_GPIO2_OUT_VAL(x) ((x) << S_GPIO2_OUT_VAL)
548#define F_GPIO2_OUT_VAL V_GPIO2_OUT_VAL(1U)
549
550#define S_GPIO1_OUT_VAL 1
551#define V_GPIO1_OUT_VAL(x) ((x) << S_GPIO1_OUT_VAL)
552#define F_GPIO1_OUT_VAL V_GPIO1_OUT_VAL(1U)
553
554#define S_GPIO0_OUT_VAL 0
555#define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL)
556#define F_GPIO0_OUT_VAL V_GPIO0_OUT_VAL(1U)
557
558#define A_T3DBG_INT_ENABLE 0xd8
559
560#define S_GPIO11 11
561#define V_GPIO11(x) ((x) << S_GPIO11)
562#define F_GPIO11 V_GPIO11(1U)
563
564#define S_GPIO10 10
565#define V_GPIO10(x) ((x) << S_GPIO10)
566#define F_GPIO10 V_GPIO10(1U)
567
568#define S_GPIO7 7
569#define V_GPIO7(x) ((x) << S_GPIO7)
570#define F_GPIO7 V_GPIO7(1U)
571
572#define S_GPIO6 6
573#define V_GPIO6(x) ((x) << S_GPIO6)
574#define F_GPIO6 V_GPIO6(1U)
575
576#define S_GPIO5 5
577#define V_GPIO5(x) ((x) << S_GPIO5)
578#define F_GPIO5 V_GPIO5(1U)
579
580#define S_GPIO4 4
581#define V_GPIO4(x) ((x) << S_GPIO4)
582#define F_GPIO4 V_GPIO4(1U)
583
584#define S_GPIO3 3
585#define V_GPIO3(x) ((x) << S_GPIO3)
586#define F_GPIO3 V_GPIO3(1U)
587
588#define S_GPIO2 2
589#define V_GPIO2(x) ((x) << S_GPIO2)
590#define F_GPIO2 V_GPIO2(1U)
591
592#define S_GPIO1 1
593#define V_GPIO1(x) ((x) << S_GPIO1)
594#define F_GPIO1 V_GPIO1(1U)
595
596#define S_GPIO0 0
597#define V_GPIO0(x) ((x) << S_GPIO0)
598#define F_GPIO0 V_GPIO0(1U)
599
600#define A_T3DBG_INT_CAUSE 0xdc
601
602#define A_T3DBG_GPIO_ACT_LOW 0xf0
603
604#define MC7_PMRX_BASE_ADDR 0x100
605
606#define A_MC7_CFG 0x100
607
608#define S_IFEN 13
609#define V_IFEN(x) ((x) << S_IFEN)
610#define F_IFEN V_IFEN(1U)
611
612#define S_TERM150 11
613#define V_TERM150(x) ((x) << S_TERM150)
614#define F_TERM150 V_TERM150(1U)
615
616#define S_SLOW 10
617#define V_SLOW(x) ((x) << S_SLOW)
618#define F_SLOW V_SLOW(1U)
619
620#define S_WIDTH 8
621#define M_WIDTH 0x3
622#define V_WIDTH(x) ((x) << S_WIDTH)
623#define G_WIDTH(x) (((x) >> S_WIDTH) & M_WIDTH)
624
625#define S_BKS 6
626#define V_BKS(x) ((x) << S_BKS)
627#define F_BKS V_BKS(1U)
628
629#define S_ORG 5
630#define V_ORG(x) ((x) << S_ORG)
631#define F_ORG V_ORG(1U)
632
633#define S_DEN 2
634#define M_DEN 0x7
635#define V_DEN(x) ((x) << S_DEN)
636#define G_DEN(x) (((x) >> S_DEN) & M_DEN)
637
638#define S_RDY 1
639#define V_RDY(x) ((x) << S_RDY)
640#define F_RDY V_RDY(1U)
641
642#define S_CLKEN 0
643#define V_CLKEN(x) ((x) << S_CLKEN)
644#define F_CLKEN V_CLKEN(1U)
645
646#define A_MC7_MODE 0x104
647
648#define S_BUSY 31
649#define V_BUSY(x) ((x) << S_BUSY)
650#define F_BUSY V_BUSY(1U)
651
652#define S_BUSY 31
653#define V_BUSY(x) ((x) << S_BUSY)
654#define F_BUSY V_BUSY(1U)
655
656#define A_MC7_EXT_MODE1 0x108
657
658#define A_MC7_EXT_MODE2 0x10c
659
660#define A_MC7_EXT_MODE3 0x110
661
662#define A_MC7_PRE 0x114
663
664#define A_MC7_REF 0x118
665
666#define S_PREREFDIV 1
667#define M_PREREFDIV 0x3fff
668#define V_PREREFDIV(x) ((x) << S_PREREFDIV)
669
670#define S_PERREFEN 0
671#define V_PERREFEN(x) ((x) << S_PERREFEN)
672#define F_PERREFEN V_PERREFEN(1U)
673
674#define A_MC7_DLL 0x11c
675
676#define S_DLLENB 1
677#define V_DLLENB(x) ((x) << S_DLLENB)
678#define F_DLLENB V_DLLENB(1U)
679
680#define S_DLLRST 0
681#define V_DLLRST(x) ((x) << S_DLLRST)
682#define F_DLLRST V_DLLRST(1U)
683
684#define A_MC7_PARM 0x120
685
686#define S_ACTTOPREDLY 26
687#define M_ACTTOPREDLY 0xf
688#define V_ACTTOPREDLY(x) ((x) << S_ACTTOPREDLY)
689
690#define S_ACTTORDWRDLY 23
691#define M_ACTTORDWRDLY 0x7
692#define V_ACTTORDWRDLY(x) ((x) << S_ACTTORDWRDLY)
693
694#define S_PRECYC 20
695#define M_PRECYC 0x7
696#define V_PRECYC(x) ((x) << S_PRECYC)
697
698#define S_REFCYC 13
699#define M_REFCYC 0x7f
700#define V_REFCYC(x) ((x) << S_REFCYC)
701
702#define S_BKCYC 8
703#define M_BKCYC 0x1f
704#define V_BKCYC(x) ((x) << S_BKCYC)
705
706#define S_WRTORDDLY 4
707#define M_WRTORDDLY 0xf
708#define V_WRTORDDLY(x) ((x) << S_WRTORDDLY)
709
710#define S_RDTOWRDLY 0
711#define M_RDTOWRDLY 0xf
712#define V_RDTOWRDLY(x) ((x) << S_RDTOWRDLY)
713
714#define A_MC7_CAL 0x128
715
716#define S_BUSY 31
717#define V_BUSY(x) ((x) << S_BUSY)
718#define F_BUSY V_BUSY(1U)
719
720#define S_BUSY 31
721#define V_BUSY(x) ((x) << S_BUSY)
722#define F_BUSY V_BUSY(1U)
723
724#define S_CAL_FAULT 30
725#define V_CAL_FAULT(x) ((x) << S_CAL_FAULT)
726#define F_CAL_FAULT V_CAL_FAULT(1U)
727
728#define S_SGL_CAL_EN 20
729#define V_SGL_CAL_EN(x) ((x) << S_SGL_CAL_EN)
730#define F_SGL_CAL_EN V_SGL_CAL_EN(1U)
731
732#define A_MC7_ERR_ADDR 0x12c
733
734#define A_MC7_ECC 0x130
735
736#define S_ECCCHKEN 1
737#define V_ECCCHKEN(x) ((x) << S_ECCCHKEN)
738#define F_ECCCHKEN V_ECCCHKEN(1U)
739
740#define S_ECCGENEN 0
741#define V_ECCGENEN(x) ((x) << S_ECCGENEN)
742#define F_ECCGENEN V_ECCGENEN(1U)
743
744#define A_MC7_CE_ADDR 0x134
745
746#define A_MC7_CE_DATA0 0x138
747
748#define A_MC7_CE_DATA1 0x13c
749
750#define A_MC7_CE_DATA2 0x140
751
752#define S_DATA 0
753#define M_DATA 0xff
754
755#define G_DATA(x) (((x) >> S_DATA) & M_DATA)
756
757#define A_MC7_UE_ADDR 0x144
758
759#define A_MC7_UE_DATA0 0x148
760
761#define A_MC7_UE_DATA1 0x14c
762
763#define A_MC7_UE_DATA2 0x150
764
765#define A_MC7_BD_ADDR 0x154
766
767#define S_ADDR 3
768
769#define M_ADDR 0x1fffffff
770
771#define A_MC7_BD_DATA0 0x158
772
773#define A_MC7_BD_DATA1 0x15c
774
775#define A_MC7_BD_OP 0x164
776
777#define S_OP 0
778
779#define V_OP(x) ((x) << S_OP)
780#define F_OP V_OP(1U)
781
782#define F_OP V_OP(1U)
783#define A_SF_OP 0x6dc
784
785#define A_MC7_BIST_ADDR_BEG 0x168
786
787#define A_MC7_BIST_ADDR_END 0x16c
788
789#define A_MC7_BIST_DATA 0x170
790
791#define A_MC7_BIST_OP 0x174
792
793#define S_CONT 3
794#define V_CONT(x) ((x) << S_CONT)
795#define F_CONT V_CONT(1U)
796
797#define F_CONT V_CONT(1U)
798
799#define A_MC7_INT_ENABLE 0x178
800
801#define S_AE 17
802#define V_AE(x) ((x) << S_AE)
803#define F_AE V_AE(1U)
804
805#define S_PE 2
806#define M_PE 0x7fff
807
808#define V_PE(x) ((x) << S_PE)
809
810#define G_PE(x) (((x) >> S_PE) & M_PE)
811
812#define S_UE 1
813#define V_UE(x) ((x) << S_UE)
814#define F_UE V_UE(1U)
815
816#define S_CE 0
817#define V_CE(x) ((x) << S_CE)
818#define F_CE V_CE(1U)
819
820#define A_MC7_INT_CAUSE 0x17c
821
822#define MC7_PMTX_BASE_ADDR 0x180
823
824#define MC7_CM_BASE_ADDR 0x200
825
826#define A_CIM_BOOT_CFG 0x280
827
828#define S_BOOTADDR 2
829#define M_BOOTADDR 0x3fffffff
830#define V_BOOTADDR(x) ((x) << S_BOOTADDR)
831
832#define A_CIM_SDRAM_BASE_ADDR 0x28c
833
834#define A_CIM_SDRAM_ADDR_SIZE 0x290
835
836#define A_CIM_HOST_INT_ENABLE 0x298
837
Divy Le Rayb8819552007-12-17 18:47:31 -0800838#define S_DTAGPARERR 28
839#define V_DTAGPARERR(x) ((x) << S_DTAGPARERR)
840#define F_DTAGPARERR V_DTAGPARERR(1U)
841
842#define S_ITAGPARERR 27
843#define V_ITAGPARERR(x) ((x) << S_ITAGPARERR)
844#define F_ITAGPARERR V_ITAGPARERR(1U)
845
846#define S_IBQTPPARERR 26
847#define V_IBQTPPARERR(x) ((x) << S_IBQTPPARERR)
848#define F_IBQTPPARERR V_IBQTPPARERR(1U)
849
850#define S_IBQULPPARERR 25
851#define V_IBQULPPARERR(x) ((x) << S_IBQULPPARERR)
852#define F_IBQULPPARERR V_IBQULPPARERR(1U)
853
854#define S_IBQSGEHIPARERR 24
855#define V_IBQSGEHIPARERR(x) ((x) << S_IBQSGEHIPARERR)
856#define F_IBQSGEHIPARERR V_IBQSGEHIPARERR(1U)
857
858#define S_IBQSGELOPARERR 23
859#define V_IBQSGELOPARERR(x) ((x) << S_IBQSGELOPARERR)
860#define F_IBQSGELOPARERR V_IBQSGELOPARERR(1U)
861
862#define S_OBQULPLOPARERR 22
863#define V_OBQULPLOPARERR(x) ((x) << S_OBQULPLOPARERR)
864#define F_OBQULPLOPARERR V_OBQULPLOPARERR(1U)
865
866#define S_OBQULPHIPARERR 21
867#define V_OBQULPHIPARERR(x) ((x) << S_OBQULPHIPARERR)
868#define F_OBQULPHIPARERR V_OBQULPHIPARERR(1U)
869
870#define S_OBQSGEPARERR 20
871#define V_OBQSGEPARERR(x) ((x) << S_OBQSGEPARERR)
872#define F_OBQSGEPARERR V_OBQSGEPARERR(1U)
873
874#define S_DCACHEPARERR 19
875#define V_DCACHEPARERR(x) ((x) << S_DCACHEPARERR)
876#define F_DCACHEPARERR V_DCACHEPARERR(1U)
877
878#define S_ICACHEPARERR 18
879#define V_ICACHEPARERR(x) ((x) << S_ICACHEPARERR)
880#define F_ICACHEPARERR V_ICACHEPARERR(1U)
881
882#define S_DRAMPARERR 17
883#define V_DRAMPARERR(x) ((x) << S_DRAMPARERR)
884#define F_DRAMPARERR V_DRAMPARERR(1U)
885
Divy Le Ray4d22de32007-01-18 22:04:14 -0500886#define A_CIM_HOST_INT_CAUSE 0x29c
887
888#define S_BLKWRPLINT 12
889#define V_BLKWRPLINT(x) ((x) << S_BLKWRPLINT)
890#define F_BLKWRPLINT V_BLKWRPLINT(1U)
891
892#define S_BLKRDPLINT 11
893#define V_BLKRDPLINT(x) ((x) << S_BLKRDPLINT)
894#define F_BLKRDPLINT V_BLKRDPLINT(1U)
895
896#define S_BLKWRCTLINT 10
897#define V_BLKWRCTLINT(x) ((x) << S_BLKWRCTLINT)
898#define F_BLKWRCTLINT V_BLKWRCTLINT(1U)
899
900#define S_BLKRDCTLINT 9
901#define V_BLKRDCTLINT(x) ((x) << S_BLKRDCTLINT)
902#define F_BLKRDCTLINT V_BLKRDCTLINT(1U)
903
904#define S_BLKWRFLASHINT 8
905#define V_BLKWRFLASHINT(x) ((x) << S_BLKWRFLASHINT)
906#define F_BLKWRFLASHINT V_BLKWRFLASHINT(1U)
907
908#define S_BLKRDFLASHINT 7
909#define V_BLKRDFLASHINT(x) ((x) << S_BLKRDFLASHINT)
910#define F_BLKRDFLASHINT V_BLKRDFLASHINT(1U)
911
912#define S_SGLWRFLASHINT 6
913#define V_SGLWRFLASHINT(x) ((x) << S_SGLWRFLASHINT)
914#define F_SGLWRFLASHINT V_SGLWRFLASHINT(1U)
915
916#define S_WRBLKFLASHINT 5
917#define V_WRBLKFLASHINT(x) ((x) << S_WRBLKFLASHINT)
918#define F_WRBLKFLASHINT V_WRBLKFLASHINT(1U)
919
920#define S_BLKWRBOOTINT 4
921#define V_BLKWRBOOTINT(x) ((x) << S_BLKWRBOOTINT)
922#define F_BLKWRBOOTINT V_BLKWRBOOTINT(1U)
923
924#define S_FLASHRANGEINT 2
925#define V_FLASHRANGEINT(x) ((x) << S_FLASHRANGEINT)
926#define F_FLASHRANGEINT V_FLASHRANGEINT(1U)
927
928#define S_SDRAMRANGEINT 1
929#define V_SDRAMRANGEINT(x) ((x) << S_SDRAMRANGEINT)
930#define F_SDRAMRANGEINT V_SDRAMRANGEINT(1U)
931
932#define S_RSVDSPACEINT 0
933#define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT)
934#define F_RSVDSPACEINT V_RSVDSPACEINT(1U)
935
936#define A_CIM_HOST_ACC_CTRL 0x2b0
937
938#define S_HOSTBUSY 17
939#define V_HOSTBUSY(x) ((x) << S_HOSTBUSY)
940#define F_HOSTBUSY V_HOSTBUSY(1U)
941
942#define A_CIM_HOST_ACC_DATA 0x2b4
943
Divy Le Rayb8819552007-12-17 18:47:31 -0800944#define A_CIM_IBQ_DBG_CFG 0x2c0
945
946#define S_IBQDBGADDR 16
947#define M_IBQDBGADDR 0x1ff
948#define V_IBQDBGADDR(x) ((x) << S_IBQDBGADDR)
949#define G_IBQDBGADDR(x) (((x) >> S_IBQDBGADDR) & M_IBQDBGADDR)
950
951#define S_IBQDBGQID 3
952#define M_IBQDBGQID 0x3
953#define V_IBQDBGQID(x) ((x) << S_IBQDBGQID)
954#define G_IBQDBGQID(x) (((x) >> S_IBQDBGQID) & M_IBQDBGQID)
955
956#define S_IBQDBGWR 2
957#define V_IBQDBGWR(x) ((x) << S_IBQDBGWR)
958#define F_IBQDBGWR V_IBQDBGWR(1U)
959
960#define S_IBQDBGBUSY 1
961#define V_IBQDBGBUSY(x) ((x) << S_IBQDBGBUSY)
962#define F_IBQDBGBUSY V_IBQDBGBUSY(1U)
963
964#define S_IBQDBGEN 0
965#define V_IBQDBGEN(x) ((x) << S_IBQDBGEN)
966#define F_IBQDBGEN V_IBQDBGEN(1U)
967
968#define A_CIM_IBQ_DBG_DATA 0x2c8
969
Divy Le Ray4d22de32007-01-18 22:04:14 -0500970#define A_TP_IN_CONFIG 0x300
971
Divy Le Rayb8819552007-12-17 18:47:31 -0800972#define S_RXFBARBPRIO 25
973#define V_RXFBARBPRIO(x) ((x) << S_RXFBARBPRIO)
974#define F_RXFBARBPRIO V_RXFBARBPRIO(1U)
975
976#define S_TXFBARBPRIO 24
977#define V_TXFBARBPRIO(x) ((x) << S_TXFBARBPRIO)
978#define F_TXFBARBPRIO V_TXFBARBPRIO(1U)
979
Divy Le Ray4d22de32007-01-18 22:04:14 -0500980#define S_NICMODE 14
981#define V_NICMODE(x) ((x) << S_NICMODE)
982#define F_NICMODE V_NICMODE(1U)
983
984#define F_NICMODE V_NICMODE(1U)
985
986#define S_IPV6ENABLE 15
987#define V_IPV6ENABLE(x) ((x) << S_IPV6ENABLE)
988#define F_IPV6ENABLE V_IPV6ENABLE(1U)
989
990#define A_TP_OUT_CONFIG 0x304
991
992#define S_VLANEXTRACTIONENABLE 12
993
994#define A_TP_GLOBAL_CONFIG 0x308
995
996#define S_TXPACINGENABLE 24
997#define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE)
998#define F_TXPACINGENABLE V_TXPACINGENABLE(1U)
999
1000#define S_PATHMTU 15
1001#define V_PATHMTU(x) ((x) << S_PATHMTU)
1002#define F_PATHMTU V_PATHMTU(1U)
1003
1004#define S_IPCHECKSUMOFFLOAD 13
1005#define V_IPCHECKSUMOFFLOAD(x) ((x) << S_IPCHECKSUMOFFLOAD)
1006#define F_IPCHECKSUMOFFLOAD V_IPCHECKSUMOFFLOAD(1U)
1007
1008#define S_UDPCHECKSUMOFFLOAD 12
1009#define V_UDPCHECKSUMOFFLOAD(x) ((x) << S_UDPCHECKSUMOFFLOAD)
1010#define F_UDPCHECKSUMOFFLOAD V_UDPCHECKSUMOFFLOAD(1U)
1011
1012#define S_TCPCHECKSUMOFFLOAD 11
1013#define V_TCPCHECKSUMOFFLOAD(x) ((x) << S_TCPCHECKSUMOFFLOAD)
1014#define F_TCPCHECKSUMOFFLOAD V_TCPCHECKSUMOFFLOAD(1U)
1015
1016#define S_IPTTL 0
1017#define M_IPTTL 0xff
1018#define V_IPTTL(x) ((x) << S_IPTTL)
1019
1020#define A_TP_CMM_MM_BASE 0x314
1021
1022#define A_TP_CMM_TIMER_BASE 0x318
1023
1024#define S_CMTIMERMAXNUM 28
1025#define M_CMTIMERMAXNUM 0x3
1026#define V_CMTIMERMAXNUM(x) ((x) << S_CMTIMERMAXNUM)
1027
1028#define A_TP_PMM_SIZE 0x31c
1029
1030#define A_TP_PMM_TX_BASE 0x320
1031
1032#define A_TP_PMM_RX_BASE 0x328
1033
1034#define A_TP_PMM_RX_PAGE_SIZE 0x32c
1035
1036#define A_TP_PMM_RX_MAX_PAGE 0x330
1037
1038#define A_TP_PMM_TX_PAGE_SIZE 0x334
1039
1040#define A_TP_PMM_TX_MAX_PAGE 0x338
1041
1042#define A_TP_TCP_OPTIONS 0x340
1043
1044#define S_MTUDEFAULT 16
1045#define M_MTUDEFAULT 0xffff
1046#define V_MTUDEFAULT(x) ((x) << S_MTUDEFAULT)
1047
1048#define S_MTUENABLE 10
1049#define V_MTUENABLE(x) ((x) << S_MTUENABLE)
1050#define F_MTUENABLE V_MTUENABLE(1U)
1051
1052#define S_SACKRX 8
1053#define V_SACKRX(x) ((x) << S_SACKRX)
1054#define F_SACKRX V_SACKRX(1U)
1055
1056#define S_SACKMODE 4
1057
1058#define M_SACKMODE 0x3
1059
1060#define V_SACKMODE(x) ((x) << S_SACKMODE)
1061
1062#define S_WINDOWSCALEMODE 2
1063#define M_WINDOWSCALEMODE 0x3
1064#define V_WINDOWSCALEMODE(x) ((x) << S_WINDOWSCALEMODE)
1065
1066#define S_TIMESTAMPSMODE 0
1067
1068#define M_TIMESTAMPSMODE 0x3
1069
1070#define V_TIMESTAMPSMODE(x) ((x) << S_TIMESTAMPSMODE)
1071
1072#define A_TP_DACK_CONFIG 0x344
1073
1074#define S_AUTOSTATE3 30
1075#define M_AUTOSTATE3 0x3
1076#define V_AUTOSTATE3(x) ((x) << S_AUTOSTATE3)
1077
1078#define S_AUTOSTATE2 28
1079#define M_AUTOSTATE2 0x3
1080#define V_AUTOSTATE2(x) ((x) << S_AUTOSTATE2)
1081
1082#define S_AUTOSTATE1 26
1083#define M_AUTOSTATE1 0x3
1084#define V_AUTOSTATE1(x) ((x) << S_AUTOSTATE1)
1085
1086#define S_BYTETHRESHOLD 5
1087#define M_BYTETHRESHOLD 0xfffff
1088#define V_BYTETHRESHOLD(x) ((x) << S_BYTETHRESHOLD)
1089
1090#define S_MSSTHRESHOLD 3
1091#define M_MSSTHRESHOLD 0x3
1092#define V_MSSTHRESHOLD(x) ((x) << S_MSSTHRESHOLD)
1093
1094#define S_AUTOCAREFUL 2
1095#define V_AUTOCAREFUL(x) ((x) << S_AUTOCAREFUL)
1096#define F_AUTOCAREFUL V_AUTOCAREFUL(1U)
1097
1098#define S_AUTOENABLE 1
1099#define V_AUTOENABLE(x) ((x) << S_AUTOENABLE)
1100#define F_AUTOENABLE V_AUTOENABLE(1U)
1101
1102#define S_DACK_MODE 0
1103#define V_DACK_MODE(x) ((x) << S_DACK_MODE)
1104#define F_DACK_MODE V_DACK_MODE(1U)
1105
1106#define A_TP_PC_CONFIG 0x348
1107
1108#define S_TXTOSQUEUEMAPMODE 26
1109#define V_TXTOSQUEUEMAPMODE(x) ((x) << S_TXTOSQUEUEMAPMODE)
1110#define F_TXTOSQUEUEMAPMODE V_TXTOSQUEUEMAPMODE(1U)
1111
1112#define S_ENABLEEPCMDAFULL 23
1113#define V_ENABLEEPCMDAFULL(x) ((x) << S_ENABLEEPCMDAFULL)
1114#define F_ENABLEEPCMDAFULL V_ENABLEEPCMDAFULL(1U)
1115
1116#define S_MODULATEUNIONMODE 22
1117#define V_MODULATEUNIONMODE(x) ((x) << S_MODULATEUNIONMODE)
1118#define F_MODULATEUNIONMODE V_MODULATEUNIONMODE(1U)
1119
1120#define S_TXDEFERENABLE 20
1121#define V_TXDEFERENABLE(x) ((x) << S_TXDEFERENABLE)
1122#define F_TXDEFERENABLE V_TXDEFERENABLE(1U)
1123
1124#define S_RXCONGESTIONMODE 19
1125#define V_RXCONGESTIONMODE(x) ((x) << S_RXCONGESTIONMODE)
1126#define F_RXCONGESTIONMODE V_RXCONGESTIONMODE(1U)
1127
1128#define S_HEARBEATDACK 16
1129#define V_HEARBEATDACK(x) ((x) << S_HEARBEATDACK)
1130#define F_HEARBEATDACK V_HEARBEATDACK(1U)
1131
1132#define S_TXCONGESTIONMODE 15
1133#define V_TXCONGESTIONMODE(x) ((x) << S_TXCONGESTIONMODE)
1134#define F_TXCONGESTIONMODE V_TXCONGESTIONMODE(1U)
1135
1136#define S_ENABLEOCSPIFULL 30
1137#define V_ENABLEOCSPIFULL(x) ((x) << S_ENABLEOCSPIFULL)
1138#define F_ENABLEOCSPIFULL V_ENABLEOCSPIFULL(1U)
1139
1140#define S_LOCKTID 28
1141#define V_LOCKTID(x) ((x) << S_LOCKTID)
1142#define F_LOCKTID V_LOCKTID(1U)
1143
Divy Le Raya2604be2007-11-16 11:22:16 -08001144#define S_TABLELATENCYDELTA 0
1145#define M_TABLELATENCYDELTA 0xf
1146#define V_TABLELATENCYDELTA(x) ((x) << S_TABLELATENCYDELTA)
1147#define G_TABLELATENCYDELTA(x) \
1148 (((x) >> S_TABLELATENCYDELTA) & M_TABLELATENCYDELTA)
1149
Divy Le Ray4d22de32007-01-18 22:04:14 -05001150#define A_TP_PC_CONFIG2 0x34c
1151
Divy Le Rayb8819552007-12-17 18:47:31 -08001152#define S_DISBLEDAPARBIT0 15
1153#define V_DISBLEDAPARBIT0(x) ((x) << S_DISBLEDAPARBIT0)
1154#define F_DISBLEDAPARBIT0 V_DISBLEDAPARBIT0(1U)
1155
1156#define S_ENABLEARPMISS 13
1157#define V_ENABLEARPMISS(x) ((x) << S_ENABLEARPMISS)
1158#define F_ENABLEARPMISS V_ENABLEARPMISS(1U)
1159
1160#define S_ENABLENONOFDTNLSYN 12
1161#define V_ENABLENONOFDTNLSYN(x) ((x) << S_ENABLENONOFDTNLSYN)
1162#define F_ENABLENONOFDTNLSYN V_ENABLENONOFDTNLSYN(1U)
1163
1164#define S_ENABLEIPV6RSS 11
1165#define V_ENABLEIPV6RSS(x) ((x) << S_ENABLEIPV6RSS)
1166#define F_ENABLEIPV6RSS V_ENABLEIPV6RSS(1U)
1167
Divy Le Ray4d22de32007-01-18 22:04:14 -05001168#define S_CHDRAFULL 4
1169#define V_CHDRAFULL(x) ((x) << S_CHDRAFULL)
1170#define F_CHDRAFULL V_CHDRAFULL(1U)
1171
1172#define A_TP_TCP_BACKOFF_REG0 0x350
1173
1174#define A_TP_TCP_BACKOFF_REG1 0x354
1175
1176#define A_TP_TCP_BACKOFF_REG2 0x358
1177
1178#define A_TP_TCP_BACKOFF_REG3 0x35c
1179
1180#define A_TP_PARA_REG2 0x368
1181
1182#define S_MAXRXDATA 16
1183#define M_MAXRXDATA 0xffff
1184#define V_MAXRXDATA(x) ((x) << S_MAXRXDATA)
1185
1186#define S_RXCOALESCESIZE 0
1187#define M_RXCOALESCESIZE 0xffff
1188#define V_RXCOALESCESIZE(x) ((x) << S_RXCOALESCESIZE)
1189
1190#define A_TP_PARA_REG3 0x36c
1191
1192#define S_TXDATAACKIDX 16
1193#define M_TXDATAACKIDX 0xf
1194
1195#define V_TXDATAACKIDX(x) ((x) << S_TXDATAACKIDX)
1196
1197#define S_TXPACEAUTOSTRICT 10
1198#define V_TXPACEAUTOSTRICT(x) ((x) << S_TXPACEAUTOSTRICT)
1199#define F_TXPACEAUTOSTRICT V_TXPACEAUTOSTRICT(1U)
1200
1201#define S_TXPACEFIXED 9
1202#define V_TXPACEFIXED(x) ((x) << S_TXPACEFIXED)
1203#define F_TXPACEFIXED V_TXPACEFIXED(1U)
1204
1205#define S_TXPACEAUTO 8
1206#define V_TXPACEAUTO(x) ((x) << S_TXPACEAUTO)
1207#define F_TXPACEAUTO V_TXPACEAUTO(1U)
1208
1209#define S_RXCOALESCEENABLE 1
1210#define V_RXCOALESCEENABLE(x) ((x) << S_RXCOALESCEENABLE)
1211#define F_RXCOALESCEENABLE V_RXCOALESCEENABLE(1U)
1212
1213#define S_RXCOALESCEPSHEN 0
1214#define V_RXCOALESCEPSHEN(x) ((x) << S_RXCOALESCEPSHEN)
1215#define F_RXCOALESCEPSHEN V_RXCOALESCEPSHEN(1U)
1216
1217#define A_TP_PARA_REG4 0x370
1218
Divy Le Rayb8819552007-12-17 18:47:31 -08001219#define A_TP_PARA_REG5 0x374
1220
1221#define S_RXDDPOFFINIT 3
1222#define V_RXDDPOFFINIT(x) ((x) << S_RXDDPOFFINIT)
1223#define F_RXDDPOFFINIT V_RXDDPOFFINIT(1U)
1224
Divy Le Ray4d22de32007-01-18 22:04:14 -05001225#define A_TP_PARA_REG6 0x378
1226
1227#define S_T3A_ENABLEESND 13
1228#define V_T3A_ENABLEESND(x) ((x) << S_T3A_ENABLEESND)
1229#define F_T3A_ENABLEESND V_T3A_ENABLEESND(1U)
1230
1231#define S_ENABLEESND 11
1232#define V_ENABLEESND(x) ((x) << S_ENABLEESND)
1233#define F_ENABLEESND V_ENABLEESND(1U)
1234
1235#define A_TP_PARA_REG7 0x37c
1236
1237#define S_PMMAXXFERLEN1 16
1238#define M_PMMAXXFERLEN1 0xffff
1239#define V_PMMAXXFERLEN1(x) ((x) << S_PMMAXXFERLEN1)
1240
1241#define S_PMMAXXFERLEN0 0
1242#define M_PMMAXXFERLEN0 0xffff
1243#define V_PMMAXXFERLEN0(x) ((x) << S_PMMAXXFERLEN0)
1244
1245#define A_TP_TIMER_RESOLUTION 0x390
1246
1247#define S_TIMERRESOLUTION 16
1248#define M_TIMERRESOLUTION 0xff
1249#define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION)
1250
1251#define S_TIMESTAMPRESOLUTION 8
1252#define M_TIMESTAMPRESOLUTION 0xff
1253#define V_TIMESTAMPRESOLUTION(x) ((x) << S_TIMESTAMPRESOLUTION)
1254
1255#define S_DELAYEDACKRESOLUTION 0
1256#define M_DELAYEDACKRESOLUTION 0xff
1257#define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION)
1258
1259#define A_TP_MSL 0x394
1260
1261#define A_TP_RXT_MIN 0x398
1262
1263#define A_TP_RXT_MAX 0x39c
1264
1265#define A_TP_PERS_MIN 0x3a0
1266
1267#define A_TP_PERS_MAX 0x3a4
1268
1269#define A_TP_KEEP_IDLE 0x3a8
1270
1271#define A_TP_KEEP_INTVL 0x3ac
1272
1273#define A_TP_INIT_SRTT 0x3b0
1274
1275#define A_TP_DACK_TIMER 0x3b4
1276
1277#define A_TP_FINWAIT2_TIMER 0x3b8
1278
1279#define A_TP_SHIFT_CNT 0x3c0
1280
1281#define S_SYNSHIFTMAX 24
1282
1283#define M_SYNSHIFTMAX 0xff
1284
1285#define V_SYNSHIFTMAX(x) ((x) << S_SYNSHIFTMAX)
1286
1287#define S_RXTSHIFTMAXR1 20
1288
1289#define M_RXTSHIFTMAXR1 0xf
1290
1291#define V_RXTSHIFTMAXR1(x) ((x) << S_RXTSHIFTMAXR1)
1292
1293#define S_RXTSHIFTMAXR2 16
1294
1295#define M_RXTSHIFTMAXR2 0xf
1296
1297#define V_RXTSHIFTMAXR2(x) ((x) << S_RXTSHIFTMAXR2)
1298
1299#define S_PERSHIFTBACKOFFMAX 12
1300#define M_PERSHIFTBACKOFFMAX 0xf
1301#define V_PERSHIFTBACKOFFMAX(x) ((x) << S_PERSHIFTBACKOFFMAX)
1302
1303#define S_PERSHIFTMAX 8
1304#define M_PERSHIFTMAX 0xf
1305#define V_PERSHIFTMAX(x) ((x) << S_PERSHIFTMAX)
1306
1307#define S_KEEPALIVEMAX 0
1308
1309#define M_KEEPALIVEMAX 0xff
1310
1311#define V_KEEPALIVEMAX(x) ((x) << S_KEEPALIVEMAX)
1312
1313#define A_TP_MTU_PORT_TABLE 0x3d0
1314
1315#define A_TP_CCTRL_TABLE 0x3dc
1316
1317#define A_TP_MTU_TABLE 0x3e4
1318
1319#define A_TP_RSS_MAP_TABLE 0x3e8
1320
1321#define A_TP_RSS_LKP_TABLE 0x3ec
1322
1323#define A_TP_RSS_CONFIG 0x3f0
1324
1325#define S_TNL4TUPEN 29
1326#define V_TNL4TUPEN(x) ((x) << S_TNL4TUPEN)
1327#define F_TNL4TUPEN V_TNL4TUPEN(1U)
1328
1329#define S_TNL2TUPEN 28
1330#define V_TNL2TUPEN(x) ((x) << S_TNL2TUPEN)
1331#define F_TNL2TUPEN V_TNL2TUPEN(1U)
1332
1333#define S_TNLPRTEN 26
1334#define V_TNLPRTEN(x) ((x) << S_TNLPRTEN)
1335#define F_TNLPRTEN V_TNLPRTEN(1U)
1336
1337#define S_TNLMAPEN 25
1338#define V_TNLMAPEN(x) ((x) << S_TNLMAPEN)
1339#define F_TNLMAPEN V_TNLMAPEN(1U)
1340
1341#define S_TNLLKPEN 24
1342#define V_TNLLKPEN(x) ((x) << S_TNLLKPEN)
1343#define F_TNLLKPEN V_TNLLKPEN(1U)
1344
Divy Le Rayb8819552007-12-17 18:47:31 -08001345#define S_RRCPLMAPEN 7
1346#define V_RRCPLMAPEN(x) ((x) << S_RRCPLMAPEN)
1347#define F_RRCPLMAPEN V_RRCPLMAPEN(1U)
1348
Divy Le Ray4d22de32007-01-18 22:04:14 -05001349#define S_RRCPLCPUSIZE 4
1350#define M_RRCPLCPUSIZE 0x7
1351#define V_RRCPLCPUSIZE(x) ((x) << S_RRCPLCPUSIZE)
1352
1353#define S_RQFEEDBACKENABLE 3
1354#define V_RQFEEDBACKENABLE(x) ((x) << S_RQFEEDBACKENABLE)
1355#define F_RQFEEDBACKENABLE V_RQFEEDBACKENABLE(1U)
1356
Divy Le Raya2604be2007-11-16 11:22:16 -08001357#define S_HASHTOEPLITZ 2
1358#define V_HASHTOEPLITZ(x) ((x) << S_HASHTOEPLITZ)
1359#define F_HASHTOEPLITZ V_HASHTOEPLITZ(1U)
1360
Divy Le Ray4d22de32007-01-18 22:04:14 -05001361#define S_DISABLE 0
1362
1363#define A_TP_TM_PIO_ADDR 0x418
1364
1365#define A_TP_TM_PIO_DATA 0x41c
1366
1367#define A_TP_TX_MOD_QUE_TABLE 0x420
1368
1369#define A_TP_TX_RESOURCE_LIMIT 0x424
1370
1371#define A_TP_TX_MOD_QUEUE_REQ_MAP 0x428
1372
1373#define S_TX_MOD_QUEUE_REQ_MAP 0
1374#define M_TX_MOD_QUEUE_REQ_MAP 0xff
1375#define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP)
1376
1377#define A_TP_TX_MOD_QUEUE_WEIGHT1 0x42c
1378
1379#define A_TP_TX_MOD_QUEUE_WEIGHT0 0x430
1380
1381#define A_TP_MOD_CHANNEL_WEIGHT 0x434
1382
Divy Le Ray8a9fab22007-05-30 21:10:52 -07001383#define A_TP_MOD_RATE_LIMIT 0x438
1384
Divy Le Ray4d22de32007-01-18 22:04:14 -05001385#define A_TP_PIO_ADDR 0x440
1386
1387#define A_TP_PIO_DATA 0x444
1388
1389#define A_TP_RESET 0x44c
1390
1391#define S_FLSTINITENABLE 1
1392#define V_FLSTINITENABLE(x) ((x) << S_FLSTINITENABLE)
1393#define F_FLSTINITENABLE V_FLSTINITENABLE(1U)
1394
1395#define S_TPRESET 0
1396#define V_TPRESET(x) ((x) << S_TPRESET)
1397#define F_TPRESET V_TPRESET(1U)
1398
1399#define A_TP_CMM_MM_RX_FLST_BASE 0x460
1400
1401#define A_TP_CMM_MM_TX_FLST_BASE 0x464
1402
1403#define A_TP_CMM_MM_PS_FLST_BASE 0x468
1404
1405#define A_TP_MIB_INDEX 0x450
1406
1407#define A_TP_MIB_RDATA 0x454
1408
1409#define A_TP_CMM_MM_MAX_PSTRUCT 0x46c
1410
1411#define A_TP_INT_ENABLE 0x470
1412
Divy Le Raya2604be2007-11-16 11:22:16 -08001413#define S_FLMTXFLSTEMPTY 30
1414#define V_FLMTXFLSTEMPTY(x) ((x) << S_FLMTXFLSTEMPTY)
1415#define F_FLMTXFLSTEMPTY V_FLMTXFLSTEMPTY(1U)
1416
1417#define S_FLMRXFLSTEMPTY 29
1418#define V_FLMRXFLSTEMPTY(x) ((x) << S_FLMRXFLSTEMPTY)
1419#define F_FLMRXFLSTEMPTY V_FLMRXFLSTEMPTY(1U)
1420
Divy Le Rayb8819552007-12-17 18:47:31 -08001421#define S_ARPLUTPERR 26
1422#define V_ARPLUTPERR(x) ((x) << S_ARPLUTPERR)
1423#define F_ARPLUTPERR V_ARPLUTPERR(1U)
1424
1425#define S_CMCACHEPERR 24
1426#define V_CMCACHEPERR(x) ((x) << S_CMCACHEPERR)
1427#define F_CMCACHEPERR V_CMCACHEPERR(1U)
1428
Divy Le Ray4d22de32007-01-18 22:04:14 -05001429#define A_TP_INT_CAUSE 0x474
1430
1431#define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8
1432
1433#define A_TP_TX_DROP_CFG_CH0 0x12b
1434
1435#define A_TP_TX_DROP_MODE 0x12f
1436
1437#define A_TP_EGRESS_CONFIG 0x145
1438
1439#define S_REWRITEFORCETOSIZE 0
1440#define V_REWRITEFORCETOSIZE(x) ((x) << S_REWRITEFORCETOSIZE)
1441#define F_REWRITEFORCETOSIZE V_REWRITEFORCETOSIZE(1U)
1442
1443#define A_TP_TX_TRC_KEY0 0x20
1444
1445#define A_TP_RX_TRC_KEY0 0x120
1446
Divy Le Rayfc906642007-03-18 13:10:12 -07001447#define A_TP_TX_DROP_CNT_CH0 0x12d
1448
1449#define S_TXDROPCNTCH0RCVD 0
1450#define M_TXDROPCNTCH0RCVD 0xffff
1451#define V_TXDROPCNTCH0RCVD(x) ((x) << S_TXDROPCNTCH0RCVD)
1452#define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & \
1453 M_TXDROPCNTCH0RCVD)
1454
Divy Le Ray8a9fab22007-05-30 21:10:52 -07001455#define A_TP_PROXY_FLOW_CNTL 0x4b0
1456
Divy Le Ray480fe1a2007-05-30 21:10:58 -07001457#define A_TP_EMBED_OP_FIELD0 0x4e8
1458#define A_TP_EMBED_OP_FIELD1 0x4ec
1459#define A_TP_EMBED_OP_FIELD2 0x4f0
1460#define A_TP_EMBED_OP_FIELD3 0x4f4
1461#define A_TP_EMBED_OP_FIELD4 0x4f8
1462#define A_TP_EMBED_OP_FIELD5 0x4fc
1463
Divy Le Ray4d22de32007-01-18 22:04:14 -05001464#define A_ULPRX_CTL 0x500
1465
1466#define S_ROUND_ROBIN 4
1467#define V_ROUND_ROBIN(x) ((x) << S_ROUND_ROBIN)
1468#define F_ROUND_ROBIN V_ROUND_ROBIN(1U)
1469
1470#define A_ULPRX_INT_ENABLE 0x504
1471
Divy Le Rayb8819552007-12-17 18:47:31 -08001472#define S_DATASELFRAMEERR0 7
1473#define V_DATASELFRAMEERR0(x) ((x) << S_DATASELFRAMEERR0)
1474#define F_DATASELFRAMEERR0 V_DATASELFRAMEERR0(1U)
1475
1476#define S_DATASELFRAMEERR1 6
1477#define V_DATASELFRAMEERR1(x) ((x) << S_DATASELFRAMEERR1)
1478#define F_DATASELFRAMEERR1 V_DATASELFRAMEERR1(1U)
1479
1480#define S_PCMDMUXPERR 5
1481#define V_PCMDMUXPERR(x) ((x) << S_PCMDMUXPERR)
1482#define F_PCMDMUXPERR V_PCMDMUXPERR(1U)
1483
1484#define S_ARBFPERR 4
1485#define V_ARBFPERR(x) ((x) << S_ARBFPERR)
1486#define F_ARBFPERR V_ARBFPERR(1U)
1487
1488#define S_ARBPF0PERR 3
1489#define V_ARBPF0PERR(x) ((x) << S_ARBPF0PERR)
1490#define F_ARBPF0PERR V_ARBPF0PERR(1U)
1491
1492#define S_ARBPF1PERR 2
1493#define V_ARBPF1PERR(x) ((x) << S_ARBPF1PERR)
1494#define F_ARBPF1PERR V_ARBPF1PERR(1U)
1495
1496#define S_PARERRPCMD 1
1497#define V_PARERRPCMD(x) ((x) << S_PARERRPCMD)
1498#define F_PARERRPCMD V_PARERRPCMD(1U)
1499
1500#define S_PARERRDATA 0
1501#define V_PARERRDATA(x) ((x) << S_PARERRDATA)
1502#define F_PARERRDATA V_PARERRDATA(1U)
Divy Le Ray4d22de32007-01-18 22:04:14 -05001503
1504#define A_ULPRX_INT_CAUSE 0x508
1505
1506#define A_ULPRX_ISCSI_LLIMIT 0x50c
1507
1508#define A_ULPRX_ISCSI_ULIMIT 0x510
1509
1510#define A_ULPRX_ISCSI_TAGMASK 0x514
1511
Divy Le Ray6cdbd772007-04-09 20:10:33 -07001512#define S_HPZ0 0
1513#define M_HPZ0 0xf
1514#define V_HPZ0(x) ((x) << S_HPZ0)
1515#define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)
1516
Divy Le Ray4d22de32007-01-18 22:04:14 -05001517#define A_ULPRX_TDDP_LLIMIT 0x51c
1518
1519#define A_ULPRX_TDDP_ULIMIT 0x520
Divy Le Ray6cdbd772007-04-09 20:10:33 -07001520#define A_ULPRX_TDDP_PSZ 0x528
Divy Le Ray4d22de32007-01-18 22:04:14 -05001521
1522#define A_ULPRX_STAG_LLIMIT 0x52c
1523
1524#define A_ULPRX_STAG_ULIMIT 0x530
1525
1526#define A_ULPRX_RQ_LLIMIT 0x534
1527#define A_ULPRX_RQ_LLIMIT 0x534
1528
1529#define A_ULPRX_RQ_ULIMIT 0x538
1530#define A_ULPRX_RQ_ULIMIT 0x538
1531
1532#define A_ULPRX_PBL_LLIMIT 0x53c
1533
1534#define A_ULPRX_PBL_ULIMIT 0x540
1535#define A_ULPRX_PBL_ULIMIT 0x540
1536
1537#define A_ULPRX_TDDP_TAGMASK 0x524
1538
1539#define A_ULPRX_RQ_LLIMIT 0x534
1540#define A_ULPRX_RQ_LLIMIT 0x534
1541
1542#define A_ULPRX_RQ_ULIMIT 0x538
1543#define A_ULPRX_RQ_ULIMIT 0x538
1544
1545#define A_ULPRX_PBL_ULIMIT 0x540
1546#define A_ULPRX_PBL_ULIMIT 0x540
1547
1548#define A_ULPTX_CONFIG 0x580
1549
Divy Le Raya2604be2007-11-16 11:22:16 -08001550#define S_CFG_CQE_SOP_MASK 1
1551#define V_CFG_CQE_SOP_MASK(x) ((x) << S_CFG_CQE_SOP_MASK)
1552#define F_CFG_CQE_SOP_MASK V_CFG_CQE_SOP_MASK(1U)
1553
Divy Le Ray4d22de32007-01-18 22:04:14 -05001554#define S_CFG_RR_ARB 0
1555#define V_CFG_RR_ARB(x) ((x) << S_CFG_RR_ARB)
1556#define F_CFG_RR_ARB V_CFG_RR_ARB(1U)
1557
1558#define A_ULPTX_INT_ENABLE 0x584
1559
1560#define S_PBL_BOUND_ERR_CH1 1
1561#define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1)
1562#define F_PBL_BOUND_ERR_CH1 V_PBL_BOUND_ERR_CH1(1U)
1563
1564#define S_PBL_BOUND_ERR_CH0 0
1565#define V_PBL_BOUND_ERR_CH0(x) ((x) << S_PBL_BOUND_ERR_CH0)
1566#define F_PBL_BOUND_ERR_CH0 V_PBL_BOUND_ERR_CH0(1U)
1567
1568#define A_ULPTX_INT_CAUSE 0x588
1569
1570#define A_ULPTX_TPT_LLIMIT 0x58c
1571
1572#define A_ULPTX_TPT_ULIMIT 0x590
1573
1574#define A_ULPTX_PBL_LLIMIT 0x594
1575
1576#define A_ULPTX_PBL_ULIMIT 0x598
1577
1578#define A_ULPTX_DMA_WEIGHT 0x5ac
1579
1580#define S_D1_WEIGHT 16
1581#define M_D1_WEIGHT 0xffff
1582#define V_D1_WEIGHT(x) ((x) << S_D1_WEIGHT)
1583
1584#define S_D0_WEIGHT 0
1585#define M_D0_WEIGHT 0xffff
1586#define V_D0_WEIGHT(x) ((x) << S_D0_WEIGHT)
1587
1588#define A_PM1_RX_CFG 0x5c0
Divy Le Ray3f61e422007-08-21 20:49:41 -07001589#define A_PM1_RX_MODE 0x5c4
Divy Le Ray4d22de32007-01-18 22:04:14 -05001590
1591#define A_PM1_RX_INT_ENABLE 0x5d8
1592
1593#define S_ZERO_E_CMD_ERROR 18
1594#define V_ZERO_E_CMD_ERROR(x) ((x) << S_ZERO_E_CMD_ERROR)
1595#define F_ZERO_E_CMD_ERROR V_ZERO_E_CMD_ERROR(1U)
1596
1597#define S_IESPI0_FIFO2X_RX_FRAMING_ERROR 17
1598#define V_IESPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_FIFO2X_RX_FRAMING_ERROR)
1599#define F_IESPI0_FIFO2X_RX_FRAMING_ERROR V_IESPI0_FIFO2X_RX_FRAMING_ERROR(1U)
1600
1601#define S_IESPI1_FIFO2X_RX_FRAMING_ERROR 16
1602#define V_IESPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_FIFO2X_RX_FRAMING_ERROR)
1603#define F_IESPI1_FIFO2X_RX_FRAMING_ERROR V_IESPI1_FIFO2X_RX_FRAMING_ERROR(1U)
1604
1605#define S_IESPI0_RX_FRAMING_ERROR 15
1606#define V_IESPI0_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_RX_FRAMING_ERROR)
1607#define F_IESPI0_RX_FRAMING_ERROR V_IESPI0_RX_FRAMING_ERROR(1U)
1608
1609#define S_IESPI1_RX_FRAMING_ERROR 14
1610#define V_IESPI1_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_RX_FRAMING_ERROR)
1611#define F_IESPI1_RX_FRAMING_ERROR V_IESPI1_RX_FRAMING_ERROR(1U)
1612
1613#define S_IESPI0_TX_FRAMING_ERROR 13
1614#define V_IESPI0_TX_FRAMING_ERROR(x) ((x) << S_IESPI0_TX_FRAMING_ERROR)
1615#define F_IESPI0_TX_FRAMING_ERROR V_IESPI0_TX_FRAMING_ERROR(1U)
1616
1617#define S_IESPI1_TX_FRAMING_ERROR 12
1618#define V_IESPI1_TX_FRAMING_ERROR(x) ((x) << S_IESPI1_TX_FRAMING_ERROR)
1619#define F_IESPI1_TX_FRAMING_ERROR V_IESPI1_TX_FRAMING_ERROR(1U)
1620
1621#define S_OCSPI0_RX_FRAMING_ERROR 11
1622#define V_OCSPI0_RX_FRAMING_ERROR(x) ((x) << S_OCSPI0_RX_FRAMING_ERROR)
1623#define F_OCSPI0_RX_FRAMING_ERROR V_OCSPI0_RX_FRAMING_ERROR(1U)
1624
1625#define S_OCSPI1_RX_FRAMING_ERROR 10
1626#define V_OCSPI1_RX_FRAMING_ERROR(x) ((x) << S_OCSPI1_RX_FRAMING_ERROR)
1627#define F_OCSPI1_RX_FRAMING_ERROR V_OCSPI1_RX_FRAMING_ERROR(1U)
1628
1629#define S_OCSPI0_TX_FRAMING_ERROR 9
1630#define V_OCSPI0_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_TX_FRAMING_ERROR)
1631#define F_OCSPI0_TX_FRAMING_ERROR V_OCSPI0_TX_FRAMING_ERROR(1U)
1632
1633#define S_OCSPI1_TX_FRAMING_ERROR 8
1634#define V_OCSPI1_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_TX_FRAMING_ERROR)
1635#define F_OCSPI1_TX_FRAMING_ERROR V_OCSPI1_TX_FRAMING_ERROR(1U)
1636
1637#define S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR 7
1638#define V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR)
1639#define F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
1640
1641#define S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR 6
1642#define V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR)
1643#define F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
1644
1645#define S_IESPI_PAR_ERROR 3
1646#define M_IESPI_PAR_ERROR 0x7
1647
1648#define V_IESPI_PAR_ERROR(x) ((x) << S_IESPI_PAR_ERROR)
1649
1650#define S_OCSPI_PAR_ERROR 0
1651#define M_OCSPI_PAR_ERROR 0x7
1652
1653#define V_OCSPI_PAR_ERROR(x) ((x) << S_OCSPI_PAR_ERROR)
1654
1655#define A_PM1_RX_INT_CAUSE 0x5dc
1656
1657#define A_PM1_TX_CFG 0x5e0
Divy Le Ray3f61e422007-08-21 20:49:41 -07001658#define A_PM1_TX_MODE 0x5e4
Divy Le Ray4d22de32007-01-18 22:04:14 -05001659
1660#define A_PM1_TX_INT_ENABLE 0x5f8
1661
1662#define S_ZERO_C_CMD_ERROR 18
1663#define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR)
1664#define F_ZERO_C_CMD_ERROR V_ZERO_C_CMD_ERROR(1U)
1665
1666#define S_ICSPI0_FIFO2X_RX_FRAMING_ERROR 17
1667#define V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_FIFO2X_RX_FRAMING_ERROR)
1668#define F_ICSPI0_FIFO2X_RX_FRAMING_ERROR V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U)
1669
1670#define S_ICSPI1_FIFO2X_RX_FRAMING_ERROR 16
1671#define V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_FIFO2X_RX_FRAMING_ERROR)
1672#define F_ICSPI1_FIFO2X_RX_FRAMING_ERROR V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U)
1673
1674#define S_ICSPI0_RX_FRAMING_ERROR 15
1675#define V_ICSPI0_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_RX_FRAMING_ERROR)
1676#define F_ICSPI0_RX_FRAMING_ERROR V_ICSPI0_RX_FRAMING_ERROR(1U)
1677
1678#define S_ICSPI1_RX_FRAMING_ERROR 14
1679#define V_ICSPI1_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_RX_FRAMING_ERROR)
1680#define F_ICSPI1_RX_FRAMING_ERROR V_ICSPI1_RX_FRAMING_ERROR(1U)
1681
1682#define S_ICSPI0_TX_FRAMING_ERROR 13
1683#define V_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_ICSPI0_TX_FRAMING_ERROR)
1684#define F_ICSPI0_TX_FRAMING_ERROR V_ICSPI0_TX_FRAMING_ERROR(1U)
1685
1686#define S_ICSPI1_TX_FRAMING_ERROR 12
1687#define V_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_ICSPI1_TX_FRAMING_ERROR)
1688#define F_ICSPI1_TX_FRAMING_ERROR V_ICSPI1_TX_FRAMING_ERROR(1U)
1689
1690#define S_OESPI0_RX_FRAMING_ERROR 11
1691#define V_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_OESPI0_RX_FRAMING_ERROR)
1692#define F_OESPI0_RX_FRAMING_ERROR V_OESPI0_RX_FRAMING_ERROR(1U)
1693
1694#define S_OESPI1_RX_FRAMING_ERROR 10
1695#define V_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_OESPI1_RX_FRAMING_ERROR)
1696#define F_OESPI1_RX_FRAMING_ERROR V_OESPI1_RX_FRAMING_ERROR(1U)
1697
1698#define S_OESPI0_TX_FRAMING_ERROR 9
1699#define V_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_TX_FRAMING_ERROR)
1700#define F_OESPI0_TX_FRAMING_ERROR V_OESPI0_TX_FRAMING_ERROR(1U)
1701
1702#define S_OESPI1_TX_FRAMING_ERROR 8
1703#define V_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_TX_FRAMING_ERROR)
1704#define F_OESPI1_TX_FRAMING_ERROR V_OESPI1_TX_FRAMING_ERROR(1U)
1705
1706#define S_OESPI0_OFIFO2X_TX_FRAMING_ERROR 7
1707#define V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_OFIFO2X_TX_FRAMING_ERROR)
1708#define F_OESPI0_OFIFO2X_TX_FRAMING_ERROR V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
1709
1710#define S_OESPI1_OFIFO2X_TX_FRAMING_ERROR 6
1711#define V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_OFIFO2X_TX_FRAMING_ERROR)
1712#define F_OESPI1_OFIFO2X_TX_FRAMING_ERROR V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
1713
1714#define S_ICSPI_PAR_ERROR 3
1715#define M_ICSPI_PAR_ERROR 0x7
1716
1717#define V_ICSPI_PAR_ERROR(x) ((x) << S_ICSPI_PAR_ERROR)
1718
1719#define S_OESPI_PAR_ERROR 0
1720#define M_OESPI_PAR_ERROR 0x7
1721
1722#define V_OESPI_PAR_ERROR(x) ((x) << S_OESPI_PAR_ERROR)
1723
1724#define A_PM1_TX_INT_CAUSE 0x5fc
1725
1726#define A_MPS_CFG 0x600
1727
1728#define S_TPRXPORTEN 4
1729#define V_TPRXPORTEN(x) ((x) << S_TPRXPORTEN)
1730#define F_TPRXPORTEN V_TPRXPORTEN(1U)
1731
1732#define S_TPTXPORT1EN 3
1733#define V_TPTXPORT1EN(x) ((x) << S_TPTXPORT1EN)
1734#define F_TPTXPORT1EN V_TPTXPORT1EN(1U)
1735
1736#define S_TPTXPORT0EN 2
1737#define V_TPTXPORT0EN(x) ((x) << S_TPTXPORT0EN)
1738#define F_TPTXPORT0EN V_TPTXPORT0EN(1U)
1739
1740#define S_PORT1ACTIVE 1
1741#define V_PORT1ACTIVE(x) ((x) << S_PORT1ACTIVE)
1742#define F_PORT1ACTIVE V_PORT1ACTIVE(1U)
1743
1744#define S_PORT0ACTIVE 0
1745#define V_PORT0ACTIVE(x) ((x) << S_PORT0ACTIVE)
1746#define F_PORT0ACTIVE V_PORT0ACTIVE(1U)
1747
1748#define S_ENFORCEPKT 11
1749#define V_ENFORCEPKT(x) ((x) << S_ENFORCEPKT)
1750#define F_ENFORCEPKT V_ENFORCEPKT(1U)
1751
1752#define A_MPS_INT_ENABLE 0x61c
1753
1754#define S_MCAPARERRENB 6
1755#define M_MCAPARERRENB 0x7
1756
1757#define V_MCAPARERRENB(x) ((x) << S_MCAPARERRENB)
1758
1759#define S_RXTPPARERRENB 4
1760#define M_RXTPPARERRENB 0x3
1761
1762#define V_RXTPPARERRENB(x) ((x) << S_RXTPPARERRENB)
1763
1764#define S_TX1TPPARERRENB 2
1765#define M_TX1TPPARERRENB 0x3
1766
1767#define V_TX1TPPARERRENB(x) ((x) << S_TX1TPPARERRENB)
1768
1769#define S_TX0TPPARERRENB 0
1770#define M_TX0TPPARERRENB 0x3
1771
1772#define V_TX0TPPARERRENB(x) ((x) << S_TX0TPPARERRENB)
1773
1774#define A_MPS_INT_CAUSE 0x620
1775
1776#define S_MCAPARERR 6
1777#define M_MCAPARERR 0x7
1778
1779#define V_MCAPARERR(x) ((x) << S_MCAPARERR)
1780
1781#define S_RXTPPARERR 4
1782#define M_RXTPPARERR 0x3
1783
1784#define V_RXTPPARERR(x) ((x) << S_RXTPPARERR)
1785
1786#define S_TX1TPPARERR 2
1787#define M_TX1TPPARERR 0x3
1788
1789#define V_TX1TPPARERR(x) ((x) << S_TX1TPPARERR)
1790
1791#define S_TX0TPPARERR 0
1792#define M_TX0TPPARERR 0x3
1793
1794#define V_TX0TPPARERR(x) ((x) << S_TX0TPPARERR)
1795
1796#define A_CPL_SWITCH_CNTRL 0x640
1797
1798#define A_CPL_INTR_ENABLE 0x650
1799
Divy Le Rayb8819552007-12-17 18:47:31 -08001800#define S_CIM_OP_MAP_PERR 5
1801#define V_CIM_OP_MAP_PERR(x) ((x) << S_CIM_OP_MAP_PERR)
1802#define F_CIM_OP_MAP_PERR V_CIM_OP_MAP_PERR(1U)
1803
Divy Le Ray4d22de32007-01-18 22:04:14 -05001804#define S_CIM_OVFL_ERROR 4
1805#define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR)
1806#define F_CIM_OVFL_ERROR V_CIM_OVFL_ERROR(1U)
1807
1808#define S_TP_FRAMING_ERROR 3
1809#define V_TP_FRAMING_ERROR(x) ((x) << S_TP_FRAMING_ERROR)
1810#define F_TP_FRAMING_ERROR V_TP_FRAMING_ERROR(1U)
1811
1812#define S_SGE_FRAMING_ERROR 2
1813#define V_SGE_FRAMING_ERROR(x) ((x) << S_SGE_FRAMING_ERROR)
1814#define F_SGE_FRAMING_ERROR V_SGE_FRAMING_ERROR(1U)
1815
1816#define S_CIM_FRAMING_ERROR 1
1817#define V_CIM_FRAMING_ERROR(x) ((x) << S_CIM_FRAMING_ERROR)
1818#define F_CIM_FRAMING_ERROR V_CIM_FRAMING_ERROR(1U)
1819
1820#define S_ZERO_SWITCH_ERROR 0
1821#define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR)
1822#define F_ZERO_SWITCH_ERROR V_ZERO_SWITCH_ERROR(1U)
1823
1824#define A_CPL_INTR_CAUSE 0x654
1825
1826#define A_CPL_MAP_TBL_DATA 0x65c
1827
1828#define A_SMB_GLOBAL_TIME_CFG 0x660
1829
1830#define A_I2C_CFG 0x6a0
1831
1832#define S_I2C_CLKDIV 0
1833#define M_I2C_CLKDIV 0xfff
1834#define V_I2C_CLKDIV(x) ((x) << S_I2C_CLKDIV)
1835
1836#define A_MI1_CFG 0x6b0
1837
1838#define S_CLKDIV 5
1839#define M_CLKDIV 0xff
1840#define V_CLKDIV(x) ((x) << S_CLKDIV)
1841
1842#define S_ST 3
1843
1844#define M_ST 0x3
1845
1846#define V_ST(x) ((x) << S_ST)
1847
1848#define G_ST(x) (((x) >> S_ST) & M_ST)
1849
1850#define S_PREEN 2
1851#define V_PREEN(x) ((x) << S_PREEN)
1852#define F_PREEN V_PREEN(1U)
1853
1854#define S_MDIINV 1
1855#define V_MDIINV(x) ((x) << S_MDIINV)
1856#define F_MDIINV V_MDIINV(1U)
1857
1858#define S_MDIEN 0
1859#define V_MDIEN(x) ((x) << S_MDIEN)
1860#define F_MDIEN V_MDIEN(1U)
1861
1862#define A_MI1_ADDR 0x6b4
1863
1864#define S_PHYADDR 5
1865#define M_PHYADDR 0x1f
1866#define V_PHYADDR(x) ((x) << S_PHYADDR)
1867
1868#define S_REGADDR 0
1869#define M_REGADDR 0x1f
1870#define V_REGADDR(x) ((x) << S_REGADDR)
1871
1872#define A_MI1_DATA 0x6b8
1873
1874#define A_MI1_OP 0x6bc
1875
1876#define S_MDI_OP 0
1877#define M_MDI_OP 0x3
1878#define V_MDI_OP(x) ((x) << S_MDI_OP)
1879
1880#define A_SF_DATA 0x6d8
1881
1882#define A_SF_OP 0x6dc
1883
1884#define S_BYTECNT 1
1885#define M_BYTECNT 0x3
1886#define V_BYTECNT(x) ((x) << S_BYTECNT)
1887
1888#define A_PL_INT_ENABLE0 0x6e0
1889
1890#define S_T3DBG 23
1891#define V_T3DBG(x) ((x) << S_T3DBG)
1892#define F_T3DBG V_T3DBG(1U)
1893
1894#define S_XGMAC0_1 20
1895#define V_XGMAC0_1(x) ((x) << S_XGMAC0_1)
1896#define F_XGMAC0_1 V_XGMAC0_1(1U)
1897
1898#define S_XGMAC0_0 19
1899#define V_XGMAC0_0(x) ((x) << S_XGMAC0_0)
1900#define F_XGMAC0_0 V_XGMAC0_0(1U)
1901
1902#define S_MC5A 18
1903#define V_MC5A(x) ((x) << S_MC5A)
1904#define F_MC5A V_MC5A(1U)
1905
1906#define S_CPL_SWITCH 12
1907#define V_CPL_SWITCH(x) ((x) << S_CPL_SWITCH)
1908#define F_CPL_SWITCH V_CPL_SWITCH(1U)
1909
1910#define S_MPS0 11
1911#define V_MPS0(x) ((x) << S_MPS0)
1912#define F_MPS0 V_MPS0(1U)
1913
1914#define S_PM1_TX 10
1915#define V_PM1_TX(x) ((x) << S_PM1_TX)
1916#define F_PM1_TX V_PM1_TX(1U)
1917
1918#define S_PM1_RX 9
1919#define V_PM1_RX(x) ((x) << S_PM1_RX)
1920#define F_PM1_RX V_PM1_RX(1U)
1921
1922#define S_ULP2_TX 8
1923#define V_ULP2_TX(x) ((x) << S_ULP2_TX)
1924#define F_ULP2_TX V_ULP2_TX(1U)
1925
1926#define S_ULP2_RX 7
1927#define V_ULP2_RX(x) ((x) << S_ULP2_RX)
1928#define F_ULP2_RX V_ULP2_RX(1U)
1929
1930#define S_TP1 6
1931#define V_TP1(x) ((x) << S_TP1)
1932#define F_TP1 V_TP1(1U)
1933
1934#define S_CIM 5
1935#define V_CIM(x) ((x) << S_CIM)
1936#define F_CIM V_CIM(1U)
1937
1938#define S_MC7_CM 4
1939#define V_MC7_CM(x) ((x) << S_MC7_CM)
1940#define F_MC7_CM V_MC7_CM(1U)
1941
1942#define S_MC7_PMTX 3
1943#define V_MC7_PMTX(x) ((x) << S_MC7_PMTX)
1944#define F_MC7_PMTX V_MC7_PMTX(1U)
1945
1946#define S_MC7_PMRX 2
1947#define V_MC7_PMRX(x) ((x) << S_MC7_PMRX)
1948#define F_MC7_PMRX V_MC7_PMRX(1U)
1949
1950#define S_PCIM0 1
1951#define V_PCIM0(x) ((x) << S_PCIM0)
1952#define F_PCIM0 V_PCIM0(1U)
1953
1954#define S_SGE3 0
1955#define V_SGE3(x) ((x) << S_SGE3)
1956#define F_SGE3 V_SGE3(1U)
1957
1958#define A_PL_INT_CAUSE0 0x6e4
1959
1960#define A_PL_RST 0x6f0
1961
1962#define S_CRSTWRM 1
1963#define V_CRSTWRM(x) ((x) << S_CRSTWRM)
1964#define F_CRSTWRM V_CRSTWRM(1U)
1965
1966#define A_PL_REV 0x6f4
1967
1968#define A_PL_CLI 0x6f8
1969
1970#define A_MC5_DB_CONFIG 0x704
1971
1972#define S_TMTYPEHI 30
1973#define V_TMTYPEHI(x) ((x) << S_TMTYPEHI)
1974#define F_TMTYPEHI V_TMTYPEHI(1U)
1975
1976#define S_TMPARTSIZE 28
1977#define M_TMPARTSIZE 0x3
1978#define V_TMPARTSIZE(x) ((x) << S_TMPARTSIZE)
1979#define G_TMPARTSIZE(x) (((x) >> S_TMPARTSIZE) & M_TMPARTSIZE)
1980
1981#define S_TMTYPE 26
1982#define M_TMTYPE 0x3
1983#define V_TMTYPE(x) ((x) << S_TMTYPE)
1984#define G_TMTYPE(x) (((x) >> S_TMTYPE) & M_TMTYPE)
1985
1986#define S_COMPEN 17
1987#define V_COMPEN(x) ((x) << S_COMPEN)
1988#define F_COMPEN V_COMPEN(1U)
1989
1990#define S_PRTYEN 6
1991#define V_PRTYEN(x) ((x) << S_PRTYEN)
1992#define F_PRTYEN V_PRTYEN(1U)
1993
1994#define S_MBUSEN 5
1995#define V_MBUSEN(x) ((x) << S_MBUSEN)
1996#define F_MBUSEN V_MBUSEN(1U)
1997
1998#define S_DBGIEN 4
1999#define V_DBGIEN(x) ((x) << S_DBGIEN)
2000#define F_DBGIEN V_DBGIEN(1U)
2001
2002#define S_TMRDY 2
2003#define V_TMRDY(x) ((x) << S_TMRDY)
2004#define F_TMRDY V_TMRDY(1U)
2005
2006#define S_TMRST 1
2007#define V_TMRST(x) ((x) << S_TMRST)
2008#define F_TMRST V_TMRST(1U)
2009
2010#define S_TMMODE 0
2011#define V_TMMODE(x) ((x) << S_TMMODE)
2012#define F_TMMODE V_TMMODE(1U)
2013
2014#define F_TMMODE V_TMMODE(1U)
2015
2016#define A_MC5_DB_ROUTING_TABLE_INDEX 0x70c
2017
2018#define A_MC5_DB_FILTER_TABLE 0x710
2019
2020#define A_MC5_DB_SERVER_INDEX 0x714
2021
2022#define A_MC5_DB_RSP_LATENCY 0x720
2023
2024#define S_RDLAT 16
2025#define M_RDLAT 0x1f
2026#define V_RDLAT(x) ((x) << S_RDLAT)
2027
2028#define S_LRNLAT 8
2029#define M_LRNLAT 0x1f
2030#define V_LRNLAT(x) ((x) << S_LRNLAT)
2031
2032#define S_SRCHLAT 0
2033#define M_SRCHLAT 0x1f
2034#define V_SRCHLAT(x) ((x) << S_SRCHLAT)
2035
2036#define A_MC5_DB_PART_ID_INDEX 0x72c
2037
2038#define A_MC5_DB_INT_ENABLE 0x740
2039
2040#define S_DELACTEMPTY 18
2041#define V_DELACTEMPTY(x) ((x) << S_DELACTEMPTY)
2042#define F_DELACTEMPTY V_DELACTEMPTY(1U)
2043
2044#define S_DISPQPARERR 17
2045#define V_DISPQPARERR(x) ((x) << S_DISPQPARERR)
2046#define F_DISPQPARERR V_DISPQPARERR(1U)
2047
2048#define S_REQQPARERR 16
2049#define V_REQQPARERR(x) ((x) << S_REQQPARERR)
2050#define F_REQQPARERR V_REQQPARERR(1U)
2051
2052#define S_UNKNOWNCMD 15
2053#define V_UNKNOWNCMD(x) ((x) << S_UNKNOWNCMD)
2054#define F_UNKNOWNCMD V_UNKNOWNCMD(1U)
2055
2056#define S_NFASRCHFAIL 8
2057#define V_NFASRCHFAIL(x) ((x) << S_NFASRCHFAIL)
2058#define F_NFASRCHFAIL V_NFASRCHFAIL(1U)
2059
2060#define S_ACTRGNFULL 7
2061#define V_ACTRGNFULL(x) ((x) << S_ACTRGNFULL)
2062#define F_ACTRGNFULL V_ACTRGNFULL(1U)
2063
2064#define S_PARITYERR 6
2065#define V_PARITYERR(x) ((x) << S_PARITYERR)
2066#define F_PARITYERR V_PARITYERR(1U)
2067
2068#define A_MC5_DB_INT_CAUSE 0x744
2069
2070#define A_MC5_DB_DBGI_CONFIG 0x774
2071
2072#define A_MC5_DB_DBGI_REQ_CMD 0x778
2073
2074#define A_MC5_DB_DBGI_REQ_ADDR0 0x77c
2075
2076#define A_MC5_DB_DBGI_REQ_ADDR1 0x780
2077
2078#define A_MC5_DB_DBGI_REQ_ADDR2 0x784
2079
2080#define A_MC5_DB_DBGI_REQ_DATA0 0x788
2081
2082#define A_MC5_DB_DBGI_REQ_DATA1 0x78c
2083
2084#define A_MC5_DB_DBGI_REQ_DATA2 0x790
2085
2086#define A_MC5_DB_DBGI_RSP_STATUS 0x7b0
2087
2088#define S_DBGIRSPVALID 0
2089#define V_DBGIRSPVALID(x) ((x) << S_DBGIRSPVALID)
2090#define F_DBGIRSPVALID V_DBGIRSPVALID(1U)
2091
2092#define A_MC5_DB_DBGI_RSP_DATA0 0x7b4
2093
2094#define A_MC5_DB_DBGI_RSP_DATA1 0x7b8
2095
2096#define A_MC5_DB_DBGI_RSP_DATA2 0x7bc
2097
2098#define A_MC5_DB_POPEN_DATA_WR_CMD 0x7cc
2099
2100#define A_MC5_DB_POPEN_MASK_WR_CMD 0x7d0
2101
2102#define A_MC5_DB_AOPEN_SRCH_CMD 0x7d4
2103
2104#define A_MC5_DB_AOPEN_LRN_CMD 0x7d8
2105
2106#define A_MC5_DB_SYN_SRCH_CMD 0x7dc
2107
2108#define A_MC5_DB_SYN_LRN_CMD 0x7e0
2109
2110#define A_MC5_DB_ACK_SRCH_CMD 0x7e4
2111
2112#define A_MC5_DB_ACK_LRN_CMD 0x7e8
2113
2114#define A_MC5_DB_ILOOKUP_CMD 0x7ec
2115
2116#define A_MC5_DB_ELOOKUP_CMD 0x7f0
2117
2118#define A_MC5_DB_DATA_WRITE_CMD 0x7f4
2119
2120#define A_MC5_DB_DATA_READ_CMD 0x7f8
2121
2122#define XGMAC0_0_BASE_ADDR 0x800
2123
2124#define A_XGM_TX_CTRL 0x800
2125
2126#define S_TXEN 0
2127#define V_TXEN(x) ((x) << S_TXEN)
2128#define F_TXEN V_TXEN(1U)
2129
2130#define A_XGM_TX_CFG 0x804
2131
2132#define S_TXPAUSEEN 0
2133#define V_TXPAUSEEN(x) ((x) << S_TXPAUSEEN)
2134#define F_TXPAUSEEN V_TXPAUSEEN(1U)
2135
Divy Le Rayfc906642007-03-18 13:10:12 -07002136#define A_XGM_TX_PAUSE_QUANTA 0x808
2137
Divy Le Ray4d22de32007-01-18 22:04:14 -05002138#define A_XGM_RX_CTRL 0x80c
2139
2140#define S_RXEN 0
2141#define V_RXEN(x) ((x) << S_RXEN)
2142#define F_RXEN V_RXEN(1U)
2143
2144#define A_XGM_RX_CFG 0x810
2145
2146#define S_DISPAUSEFRAMES 9
2147#define V_DISPAUSEFRAMES(x) ((x) << S_DISPAUSEFRAMES)
2148#define F_DISPAUSEFRAMES V_DISPAUSEFRAMES(1U)
2149
2150#define S_EN1536BFRAMES 8
2151#define V_EN1536BFRAMES(x) ((x) << S_EN1536BFRAMES)
2152#define F_EN1536BFRAMES V_EN1536BFRAMES(1U)
2153
2154#define S_ENJUMBO 7
2155#define V_ENJUMBO(x) ((x) << S_ENJUMBO)
2156#define F_ENJUMBO V_ENJUMBO(1U)
2157
2158#define S_RMFCS 6
2159#define V_RMFCS(x) ((x) << S_RMFCS)
2160#define F_RMFCS V_RMFCS(1U)
2161
2162#define S_ENHASHMCAST 2
2163#define V_ENHASHMCAST(x) ((x) << S_ENHASHMCAST)
2164#define F_ENHASHMCAST V_ENHASHMCAST(1U)
2165
2166#define S_COPYALLFRAMES 0
2167#define V_COPYALLFRAMES(x) ((x) << S_COPYALLFRAMES)
2168#define F_COPYALLFRAMES V_COPYALLFRAMES(1U)
2169
Divy Le Ray7b581a02007-05-30 10:01:44 -07002170#define S_DISBCAST 1
2171#define V_DISBCAST(x) ((x) << S_DISBCAST)
2172#define F_DISBCAST V_DISBCAST(1U)
2173
Divy Le Ray4d22de32007-01-18 22:04:14 -05002174#define A_XGM_RX_HASH_LOW 0x814
2175
2176#define A_XGM_RX_HASH_HIGH 0x818
2177
2178#define A_XGM_RX_EXACT_MATCH_LOW_1 0x81c
2179
2180#define A_XGM_RX_EXACT_MATCH_HIGH_1 0x820
2181
2182#define A_XGM_RX_EXACT_MATCH_LOW_2 0x824
2183
2184#define A_XGM_RX_EXACT_MATCH_LOW_3 0x82c
2185
2186#define A_XGM_RX_EXACT_MATCH_LOW_4 0x834
2187
2188#define A_XGM_RX_EXACT_MATCH_LOW_5 0x83c
2189
2190#define A_XGM_RX_EXACT_MATCH_LOW_6 0x844
2191
2192#define A_XGM_RX_EXACT_MATCH_LOW_7 0x84c
2193
2194#define A_XGM_RX_EXACT_MATCH_LOW_8 0x854
2195
2196#define A_XGM_STAT_CTRL 0x880
2197
2198#define S_CLRSTATS 2
2199#define V_CLRSTATS(x) ((x) << S_CLRSTATS)
2200#define F_CLRSTATS V_CLRSTATS(1U)
2201
2202#define A_XGM_RXFIFO_CFG 0x884
2203
Divy Le Ray75758e82007-12-05 10:15:01 -08002204#define S_RXFIFO_EMPTY 31
2205#define V_RXFIFO_EMPTY(x) ((x) << S_RXFIFO_EMPTY)
2206#define F_RXFIFO_EMPTY V_RXFIFO_EMPTY(1U)
2207
Divy Le Ray4d22de32007-01-18 22:04:14 -05002208#define S_RXFIFOPAUSEHWM 17
2209#define M_RXFIFOPAUSEHWM 0xfff
2210
2211#define V_RXFIFOPAUSEHWM(x) ((x) << S_RXFIFOPAUSEHWM)
2212
2213#define G_RXFIFOPAUSEHWM(x) (((x) >> S_RXFIFOPAUSEHWM) & M_RXFIFOPAUSEHWM)
2214
2215#define S_RXFIFOPAUSELWM 5
2216#define M_RXFIFOPAUSELWM 0xfff
2217
2218#define V_RXFIFOPAUSELWM(x) ((x) << S_RXFIFOPAUSELWM)
2219
2220#define G_RXFIFOPAUSELWM(x) (((x) >> S_RXFIFOPAUSELWM) & M_RXFIFOPAUSELWM)
2221
2222#define S_RXSTRFRWRD 1
2223#define V_RXSTRFRWRD(x) ((x) << S_RXSTRFRWRD)
2224#define F_RXSTRFRWRD V_RXSTRFRWRD(1U)
2225
2226#define S_DISERRFRAMES 0
2227#define V_DISERRFRAMES(x) ((x) << S_DISERRFRAMES)
2228#define F_DISERRFRAMES V_DISERRFRAMES(1U)
2229
2230#define A_XGM_TXFIFO_CFG 0x888
2231
Divy Le Ray75758e82007-12-05 10:15:01 -08002232#define S_UNDERUNFIX 22
2233#define V_UNDERUNFIX(x) ((x) << S_UNDERUNFIX)
2234#define F_UNDERUNFIX V_UNDERUNFIX(1U)
2235
Divy Le Rayfc906642007-03-18 13:10:12 -07002236#define S_TXIPG 13
2237#define M_TXIPG 0xff
2238#define V_TXIPG(x) ((x) << S_TXIPG)
2239#define G_TXIPG(x) (((x) >> S_TXIPG) & M_TXIPG)
2240
Divy Le Ray4d22de32007-01-18 22:04:14 -05002241#define S_TXFIFOTHRESH 4
2242#define M_TXFIFOTHRESH 0x1ff
2243
2244#define V_TXFIFOTHRESH(x) ((x) << S_TXFIFOTHRESH)
2245
Divy Le Ray6d6daba2007-03-31 00:23:24 -07002246#define S_ENDROPPKT 21
2247#define V_ENDROPPKT(x) ((x) << S_ENDROPPKT)
2248#define F_ENDROPPKT V_ENDROPPKT(1U)
2249
Divy Le Ray4d22de32007-01-18 22:04:14 -05002250#define A_XGM_SERDES_CTRL 0x890
2251#define A_XGM_SERDES_CTRL0 0x8e0
2252
2253#define S_SERDESRESET_ 24
2254#define V_SERDESRESET_(x) ((x) << S_SERDESRESET_)
2255#define F_SERDESRESET_ V_SERDESRESET_(1U)
2256
2257#define S_RXENABLE 4
2258#define V_RXENABLE(x) ((x) << S_RXENABLE)
2259#define F_RXENABLE V_RXENABLE(1U)
2260
2261#define S_TXENABLE 3
2262#define V_TXENABLE(x) ((x) << S_TXENABLE)
2263#define F_TXENABLE V_TXENABLE(1U)
2264
2265#define A_XGM_PAUSE_TIMER 0x890
2266
2267#define A_XGM_RGMII_IMP 0x89c
2268
2269#define S_XGM_IMPSETUPDATE 6
2270#define V_XGM_IMPSETUPDATE(x) ((x) << S_XGM_IMPSETUPDATE)
2271#define F_XGM_IMPSETUPDATE V_XGM_IMPSETUPDATE(1U)
2272
2273#define S_RGMIIIMPPD 3
2274#define M_RGMIIIMPPD 0x7
2275#define V_RGMIIIMPPD(x) ((x) << S_RGMIIIMPPD)
2276
2277#define S_RGMIIIMPPU 0
2278#define M_RGMIIIMPPU 0x7
2279#define V_RGMIIIMPPU(x) ((x) << S_RGMIIIMPPU)
2280
2281#define S_CALRESET 8
2282#define V_CALRESET(x) ((x) << S_CALRESET)
2283#define F_CALRESET V_CALRESET(1U)
2284
2285#define S_CALUPDATE 7
2286#define V_CALUPDATE(x) ((x) << S_CALUPDATE)
2287#define F_CALUPDATE V_CALUPDATE(1U)
2288
2289#define A_XGM_XAUI_IMP 0x8a0
2290
2291#define S_CALBUSY 31
2292#define V_CALBUSY(x) ((x) << S_CALBUSY)
2293#define F_CALBUSY V_CALBUSY(1U)
2294
2295#define S_XGM_CALFAULT 29
2296#define V_XGM_CALFAULT(x) ((x) << S_XGM_CALFAULT)
2297#define F_XGM_CALFAULT V_XGM_CALFAULT(1U)
2298
2299#define S_CALIMP 24
2300#define M_CALIMP 0x1f
2301#define V_CALIMP(x) ((x) << S_CALIMP)
2302#define G_CALIMP(x) (((x) >> S_CALIMP) & M_CALIMP)
2303
2304#define S_XAUIIMP 0
2305#define M_XAUIIMP 0x7
2306#define V_XAUIIMP(x) ((x) << S_XAUIIMP)
2307
2308#define A_XGM_RX_MAX_PKT_SIZE 0x8a8
Divy Le Ray75758e82007-12-05 10:15:01 -08002309
2310#define S_RXMAXFRAMERSIZE 17
2311#define M_RXMAXFRAMERSIZE 0x3fff
2312#define V_RXMAXFRAMERSIZE(x) ((x) << S_RXMAXFRAMERSIZE)
2313#define G_RXMAXFRAMERSIZE(x) (((x) >> S_RXMAXFRAMERSIZE) & M_RXMAXFRAMERSIZE)
2314
2315#define S_RXENFRAMER 14
2316#define V_RXENFRAMER(x) ((x) << S_RXENFRAMER)
2317#define F_RXENFRAMER V_RXENFRAMER(1U)
2318
2319#define S_RXMAXPKTSIZE 0
2320#define M_RXMAXPKTSIZE 0x3fff
2321#define V_RXMAXPKTSIZE(x) ((x) << S_RXMAXPKTSIZE)
2322#define G_RXMAXPKTSIZE(x) (((x) >> S_RXMAXPKTSIZE) & M_RXMAXPKTSIZE)
Divy Le Ray4d22de32007-01-18 22:04:14 -05002323
2324#define A_XGM_RESET_CTRL 0x8ac
2325
Divy Le Ray75758e82007-12-05 10:15:01 -08002326#define S_XGMAC_STOP_EN 4
2327#define V_XGMAC_STOP_EN(x) ((x) << S_XGMAC_STOP_EN)
2328#define F_XGMAC_STOP_EN V_XGMAC_STOP_EN(1U)
2329
Divy Le Ray4d22de32007-01-18 22:04:14 -05002330#define S_XG2G_RESET_ 3
2331#define V_XG2G_RESET_(x) ((x) << S_XG2G_RESET_)
2332#define F_XG2G_RESET_ V_XG2G_RESET_(1U)
2333
2334#define S_RGMII_RESET_ 2
2335#define V_RGMII_RESET_(x) ((x) << S_RGMII_RESET_)
2336#define F_RGMII_RESET_ V_RGMII_RESET_(1U)
2337
2338#define S_PCS_RESET_ 1
2339#define V_PCS_RESET_(x) ((x) << S_PCS_RESET_)
2340#define F_PCS_RESET_ V_PCS_RESET_(1U)
2341
2342#define S_MAC_RESET_ 0
2343#define V_MAC_RESET_(x) ((x) << S_MAC_RESET_)
2344#define F_MAC_RESET_ V_MAC_RESET_(1U)
2345
2346#define A_XGM_PORT_CFG 0x8b8
2347
2348#define S_CLKDIVRESET_ 3
2349#define V_CLKDIVRESET_(x) ((x) << S_CLKDIVRESET_)
2350#define F_CLKDIVRESET_ V_CLKDIVRESET_(1U)
2351
2352#define S_PORTSPEED 1
2353#define M_PORTSPEED 0x3
2354
2355#define V_PORTSPEED(x) ((x) << S_PORTSPEED)
2356
2357#define S_ENRGMII 0
2358#define V_ENRGMII(x) ((x) << S_ENRGMII)
2359#define F_ENRGMII V_ENRGMII(1U)
2360
2361#define A_XGM_INT_ENABLE 0x8d4
2362
2363#define S_TXFIFO_PRTY_ERR 17
2364#define M_TXFIFO_PRTY_ERR 0x7
2365
2366#define V_TXFIFO_PRTY_ERR(x) ((x) << S_TXFIFO_PRTY_ERR)
2367
2368#define S_RXFIFO_PRTY_ERR 14
2369#define M_RXFIFO_PRTY_ERR 0x7
2370
2371#define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR)
2372
2373#define S_TXFIFO_UNDERRUN 13
2374#define V_TXFIFO_UNDERRUN(x) ((x) << S_TXFIFO_UNDERRUN)
2375#define F_TXFIFO_UNDERRUN V_TXFIFO_UNDERRUN(1U)
2376
2377#define S_RXFIFO_OVERFLOW 12
2378#define V_RXFIFO_OVERFLOW(x) ((x) << S_RXFIFO_OVERFLOW)
2379#define F_RXFIFO_OVERFLOW V_RXFIFO_OVERFLOW(1U)
2380
2381#define S_SERDES_LOS 4
2382#define M_SERDES_LOS 0xf
2383
2384#define V_SERDES_LOS(x) ((x) << S_SERDES_LOS)
2385
2386#define S_XAUIPCSCTCERR 3
2387#define V_XAUIPCSCTCERR(x) ((x) << S_XAUIPCSCTCERR)
2388#define F_XAUIPCSCTCERR V_XAUIPCSCTCERR(1U)
2389
2390#define S_XAUIPCSALIGNCHANGE 2
2391#define V_XAUIPCSALIGNCHANGE(x) ((x) << S_XAUIPCSALIGNCHANGE)
2392#define F_XAUIPCSALIGNCHANGE V_XAUIPCSALIGNCHANGE(1U)
2393
2394#define A_XGM_INT_CAUSE 0x8d8
2395
2396#define A_XGM_XAUI_ACT_CTRL 0x8dc
2397
2398#define S_TXACTENABLE 1
2399#define V_TXACTENABLE(x) ((x) << S_TXACTENABLE)
2400#define F_TXACTENABLE V_TXACTENABLE(1U)
2401
2402#define A_XGM_SERDES_CTRL0 0x8e0
2403
2404#define S_RESET3 23
2405#define V_RESET3(x) ((x) << S_RESET3)
2406#define F_RESET3 V_RESET3(1U)
2407
2408#define S_RESET2 22
2409#define V_RESET2(x) ((x) << S_RESET2)
2410#define F_RESET2 V_RESET2(1U)
2411
2412#define S_RESET1 21
2413#define V_RESET1(x) ((x) << S_RESET1)
2414#define F_RESET1 V_RESET1(1U)
2415
2416#define S_RESET0 20
2417#define V_RESET0(x) ((x) << S_RESET0)
2418#define F_RESET0 V_RESET0(1U)
2419
2420#define S_PWRDN3 19
2421#define V_PWRDN3(x) ((x) << S_PWRDN3)
2422#define F_PWRDN3 V_PWRDN3(1U)
2423
2424#define S_PWRDN2 18
2425#define V_PWRDN2(x) ((x) << S_PWRDN2)
2426#define F_PWRDN2 V_PWRDN2(1U)
2427
2428#define S_PWRDN1 17
2429#define V_PWRDN1(x) ((x) << S_PWRDN1)
2430#define F_PWRDN1 V_PWRDN1(1U)
2431
2432#define S_PWRDN0 16
2433#define V_PWRDN0(x) ((x) << S_PWRDN0)
2434#define F_PWRDN0 V_PWRDN0(1U)
2435
2436#define S_RESETPLL23 15
2437#define V_RESETPLL23(x) ((x) << S_RESETPLL23)
2438#define F_RESETPLL23 V_RESETPLL23(1U)
2439
2440#define S_RESETPLL01 14
2441#define V_RESETPLL01(x) ((x) << S_RESETPLL01)
2442#define F_RESETPLL01 V_RESETPLL01(1U)
2443
2444#define A_XGM_SERDES_STAT0 0x8f0
Divy Le Rayc706bfb2007-05-30 10:01:39 -07002445#define A_XGM_SERDES_STAT1 0x8f4
2446#define A_XGM_SERDES_STAT2 0x8f8
Divy Le Ray4d22de32007-01-18 22:04:14 -05002447
2448#define S_LOWSIG0 0
2449#define V_LOWSIG0(x) ((x) << S_LOWSIG0)
2450#define F_LOWSIG0 V_LOWSIG0(1U)
2451
2452#define A_XGM_SERDES_STAT3 0x8fc
2453
2454#define A_XGM_STAT_TX_BYTE_LOW 0x900
2455
2456#define A_XGM_STAT_TX_BYTE_HIGH 0x904
2457
2458#define A_XGM_STAT_TX_FRAME_LOW 0x908
2459
2460#define A_XGM_STAT_TX_FRAME_HIGH 0x90c
2461
2462#define A_XGM_STAT_TX_BCAST 0x910
2463
2464#define A_XGM_STAT_TX_MCAST 0x914
2465
2466#define A_XGM_STAT_TX_PAUSE 0x918
2467
2468#define A_XGM_STAT_TX_64B_FRAMES 0x91c
2469
2470#define A_XGM_STAT_TX_65_127B_FRAMES 0x920
2471
2472#define A_XGM_STAT_TX_128_255B_FRAMES 0x924
2473
2474#define A_XGM_STAT_TX_256_511B_FRAMES 0x928
2475
2476#define A_XGM_STAT_TX_512_1023B_FRAMES 0x92c
2477
2478#define A_XGM_STAT_TX_1024_1518B_FRAMES 0x930
2479
2480#define A_XGM_STAT_TX_1519_MAXB_FRAMES 0x934
2481
2482#define A_XGM_STAT_TX_ERR_FRAMES 0x938
2483
2484#define A_XGM_STAT_RX_BYTES_LOW 0x93c
2485
2486#define A_XGM_STAT_RX_BYTES_HIGH 0x940
2487
2488#define A_XGM_STAT_RX_FRAMES_LOW 0x944
2489
2490#define A_XGM_STAT_RX_FRAMES_HIGH 0x948
2491
2492#define A_XGM_STAT_RX_BCAST_FRAMES 0x94c
2493
2494#define A_XGM_STAT_RX_MCAST_FRAMES 0x950
2495
2496#define A_XGM_STAT_RX_PAUSE_FRAMES 0x954
2497
2498#define A_XGM_STAT_RX_64B_FRAMES 0x958
2499
2500#define A_XGM_STAT_RX_65_127B_FRAMES 0x95c
2501
2502#define A_XGM_STAT_RX_128_255B_FRAMES 0x960
2503
2504#define A_XGM_STAT_RX_256_511B_FRAMES 0x964
2505
2506#define A_XGM_STAT_RX_512_1023B_FRAMES 0x968
2507
2508#define A_XGM_STAT_RX_1024_1518B_FRAMES 0x96c
2509
2510#define A_XGM_STAT_RX_1519_MAXB_FRAMES 0x970
2511
2512#define A_XGM_STAT_RX_SHORT_FRAMES 0x974
2513
2514#define A_XGM_STAT_RX_OVERSIZE_FRAMES 0x978
2515
2516#define A_XGM_STAT_RX_JABBER_FRAMES 0x97c
2517
2518#define A_XGM_STAT_RX_CRC_ERR_FRAMES 0x980
2519
2520#define A_XGM_STAT_RX_LENGTH_ERR_FRAMES 0x984
2521
2522#define A_XGM_STAT_RX_SYM_CODE_ERR_FRAMES 0x988
2523
2524#define A_XGM_SERDES_STATUS0 0x98c
2525
2526#define A_XGM_SERDES_STATUS1 0x990
2527
2528#define S_CMULOCK 31
2529#define V_CMULOCK(x) ((x) << S_CMULOCK)
2530#define F_CMULOCK V_CMULOCK(1U)
2531
2532#define A_XGM_RX_MAX_PKT_SIZE_ERR_CNT 0x9a4
2533
Divy Le Rayfc906642007-03-18 13:10:12 -07002534#define A_XGM_TX_SPI4_SOP_EOP_CNT 0x9a8
2535
2536#define S_TXSPI4SOPCNT 16
2537#define M_TXSPI4SOPCNT 0xffff
2538#define V_TXSPI4SOPCNT(x) ((x) << S_TXSPI4SOPCNT)
2539#define G_TXSPI4SOPCNT(x) (((x) >> S_TXSPI4SOPCNT) & M_TXSPI4SOPCNT)
2540
Divy Le Ray4d22de32007-01-18 22:04:14 -05002541#define A_XGM_RX_SPI4_SOP_EOP_CNT 0x9ac
2542
2543#define XGMAC0_1_BASE_ADDR 0xa00