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Ajay Kumar825e90d2012-10-13 05:48:00 +09001The Exynos display port interface should be configured based on
2the type of panel connected to it.
3
4We use two nodes:
5 -dp-controller node
6 -dptx-phy node(defined inside dp-controller node)
7
8For the DP-PHY initialization, we use the dptx-phy node.
Jingoo Han8114fab2013-10-16 21:58:16 +05309Required properties for dptx-phy: deprecated, use phys and phy-names
10 -reg: deprecated
Ajay Kumar825e90d2012-10-13 05:48:00 +090011 Base address of DP PHY register.
Jingoo Han8114fab2013-10-16 21:58:16 +053012 -samsung,enable-mask: deprecated
Ajay Kumar825e90d2012-10-13 05:48:00 +090013 The bit-mask used to enable/disable DP PHY.
14
15For the Panel initialization, we read data from dp-controller node.
16Required properties for dp-controller:
17 -compatible:
18 should be "samsung,exynos5-dp".
19 -reg:
20 physical base address of the controller and length
21 of memory mapped region.
22 -interrupts:
23 interrupt combiner values.
Jingoo Han60e69852013-06-10 17:38:32 +090024 -clocks:
25 from common clock binding: handle to dp clock.
26 -clock-names:
27 from common clock binding: Shall be "dp".
Ajay Kumar825e90d2012-10-13 05:48:00 +090028 -interrupt-parent:
29 phandle to Interrupt combiner node.
Jingoo Han8114fab2013-10-16 21:58:16 +053030 -phys:
31 from general PHY binding: the phandle for the PHY device.
32 -phy-names:
33 from general PHY binding: Should be "dp".
Ajay Kumar825e90d2012-10-13 05:48:00 +090034 -samsung,color-space:
35 input video data format.
36 COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
37 -samsung,dynamic-range:
38 dynamic range for input video data.
39 VESA = 0, CEA = 1
40 -samsung,ycbcr-coeff:
41 YCbCr co-efficients for input video.
42 COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
43 -samsung,color-depth:
44 number of bits per colour component.
45 COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
46 -samsung,link-rate:
47 link rate supported by the panel.
48 LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
49 -samsung,lane-count:
50 number of lanes supported by the panel.
51 LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
Sean Paul1417f102014-01-30 16:19:23 -050052 - display-timings: timings for the connected panel as described by
53 Documentation/devicetree/bindings/video/display-timing.txt
Ajay Kumar825e90d2012-10-13 05:48:00 +090054
55Optional properties for dp-controller:
56 -interlaced:
57 interlace scan mode.
58 Progressive if defined, Interlaced if not defined
59 -vsync-active-high:
60 VSYNC polarity configuration.
61 High if defined, Low if not defined
62 -hsync-active-high:
63 HSYNC polarity configuration.
64 High if defined, Low if not defined
Andrew Brestickerb8b52472014-04-22 04:09:10 +053065 -samsung,hpd-gpio:
66 Hotplug detect GPIO.
67 Indicates which GPIO should be used for hotplug
68 detection
Ajay Kumar825e90d2012-10-13 05:48:00 +090069
70Example:
71
72SOC specific portion:
73 dp-controller {
74 compatible = "samsung,exynos5-dp";
75 reg = <0x145b0000 0x10000>;
76 interrupts = <10 3>;
77 interrupt-parent = <&combiner>;
Jingoo Han60e69852013-06-10 17:38:32 +090078 clocks = <&clock 342>;
79 clock-names = "dp";
Ajay Kumar825e90d2012-10-13 05:48:00 +090080
Jingoo Han8114fab2013-10-16 21:58:16 +053081 phys = <&dp_phy>;
82 phy-names = "dp";
Ajay Kumar825e90d2012-10-13 05:48:00 +090083 };
84
85Board Specific portion:
86 dp-controller {
87 samsung,color-space = <0>;
88 samsung,dynamic-range = <0>;
89 samsung,ycbcr-coeff = <0>;
90 samsung,color-depth = <1>;
91 samsung,link-rate = <0x0a>;
92 samsung,lane-count = <4>;
Sean Paul1417f102014-01-30 16:19:23 -050093
94 display-timings {
95 native-mode = <&lcd_timing>;
96 lcd_timing: 1366x768 {
97 clock-frequency = <70589280>;
98 hactive = <1366>;
99 vactive = <768>;
100 hfront-porch = <40>;
101 hback-porch = <40>;
102 hsync-len = <32>;
103 vback-porch = <10>;
104 vfront-porch = <12>;
105 vsync-len = <6>;
106 };
107 };
Ajay Kumar825e90d2012-10-13 05:48:00 +0900108 };