Patil, Rachna | 01636eb | 2012-10-16 12:55:43 +0530 | [diff] [blame] | 1 | #ifndef __LINUX_TI_AM335X_TSCADC_MFD_H |
| 2 | #define __LINUX_TI_AM335X_TSCADC_MFD_H |
| 3 | |
| 4 | /* |
| 5 | * TI Touch Screen / ADC MFD driver |
| 6 | * |
| 7 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation version 2. |
| 12 | * |
| 13 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
| 14 | * kind, whether express or implied; without even the implied warranty |
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | */ |
| 18 | |
| 19 | #include <linux/mfd/core.h> |
| 20 | |
| 21 | #define REG_RAWIRQSTATUS 0x024 |
| 22 | #define REG_IRQSTATUS 0x028 |
| 23 | #define REG_IRQENABLE 0x02C |
| 24 | #define REG_IRQCLR 0x030 |
| 25 | #define REG_IRQWAKEUP 0x034 |
| 26 | #define REG_CTRL 0x040 |
| 27 | #define REG_ADCFSM 0x044 |
| 28 | #define REG_CLKDIV 0x04C |
| 29 | #define REG_SE 0x054 |
| 30 | #define REG_IDLECONFIG 0x058 |
| 31 | #define REG_CHARGECONFIG 0x05C |
| 32 | #define REG_CHARGEDELAY 0x060 |
| 33 | #define REG_STEPCONFIG(n) (0x64 + ((n - 1) * 8)) |
| 34 | #define REG_STEPDELAY(n) (0x68 + ((n - 1) * 8)) |
| 35 | #define REG_FIFO0CNT 0xE4 |
| 36 | #define REG_FIFO0THR 0xE8 |
| 37 | #define REG_FIFO1CNT 0xF0 |
| 38 | #define REG_FIFO1THR 0xF4 |
| 39 | #define REG_FIFO0 0x100 |
| 40 | #define REG_FIFO1 0x200 |
| 41 | |
| 42 | /* Register Bitfields */ |
| 43 | /* IRQ wakeup enable */ |
| 44 | #define IRQWKUP_ENB BIT(0) |
| 45 | |
| 46 | /* Step Enable */ |
| 47 | #define STEPENB_MASK (0x1FFFF << 0) |
| 48 | #define STEPENB(val) ((val) << 0) |
| 49 | #define STPENB_STEPENB STEPENB(0x1FFFF) |
Patil, Rachna | 2b99baf | 2012-10-16 12:55:44 +0530 | [diff] [blame] | 50 | #define STPENB_STEPENB_TC STEPENB(0x1FFF) |
Patil, Rachna | 01636eb | 2012-10-16 12:55:43 +0530 | [diff] [blame] | 51 | |
| 52 | /* IRQ enable */ |
| 53 | #define IRQENB_HW_PEN BIT(0) |
| 54 | #define IRQENB_FIFO0THRES BIT(2) |
| 55 | #define IRQENB_FIFO1THRES BIT(5) |
| 56 | #define IRQENB_PENUP BIT(9) |
| 57 | |
| 58 | /* Step Configuration */ |
| 59 | #define STEPCONFIG_MODE_MASK (3 << 0) |
| 60 | #define STEPCONFIG_MODE(val) ((val) << 0) |
| 61 | #define STEPCONFIG_MODE_HWSYNC STEPCONFIG_MODE(2) |
| 62 | #define STEPCONFIG_AVG_MASK (7 << 2) |
| 63 | #define STEPCONFIG_AVG(val) ((val) << 2) |
| 64 | #define STEPCONFIG_AVG_16 STEPCONFIG_AVG(4) |
| 65 | #define STEPCONFIG_XPP BIT(5) |
| 66 | #define STEPCONFIG_XNN BIT(6) |
| 67 | #define STEPCONFIG_YPP BIT(7) |
| 68 | #define STEPCONFIG_YNN BIT(8) |
| 69 | #define STEPCONFIG_XNP BIT(9) |
| 70 | #define STEPCONFIG_YPN BIT(10) |
| 71 | #define STEPCONFIG_INM_MASK (0xF << 15) |
| 72 | #define STEPCONFIG_INM(val) ((val) << 15) |
| 73 | #define STEPCONFIG_INM_ADCREFM STEPCONFIG_INM(8) |
| 74 | #define STEPCONFIG_INP_MASK (0xF << 19) |
| 75 | #define STEPCONFIG_INP(val) ((val) << 19) |
| 76 | #define STEPCONFIG_INP_AN2 STEPCONFIG_INP(2) |
| 77 | #define STEPCONFIG_INP_AN3 STEPCONFIG_INP(3) |
| 78 | #define STEPCONFIG_INP_AN4 STEPCONFIG_INP(4) |
| 79 | #define STEPCONFIG_INP_ADCREFM STEPCONFIG_INP(8) |
| 80 | #define STEPCONFIG_FIFO1 BIT(26) |
| 81 | |
| 82 | /* Delay register */ |
| 83 | #define STEPDELAY_OPEN_MASK (0x3FFFF << 0) |
| 84 | #define STEPDELAY_OPEN(val) ((val) << 0) |
| 85 | #define STEPCONFIG_OPENDLY STEPDELAY_OPEN(0x098) |
| 86 | #define STEPDELAY_SAMPLE_MASK (0xFF << 24) |
| 87 | #define STEPDELAY_SAMPLE(val) ((val) << 24) |
| 88 | #define STEPCONFIG_SAMPLEDLY STEPDELAY_SAMPLE(0) |
| 89 | |
| 90 | /* Charge Config */ |
| 91 | #define STEPCHARGE_RFP_MASK (7 << 12) |
| 92 | #define STEPCHARGE_RFP(val) ((val) << 12) |
| 93 | #define STEPCHARGE_RFP_XPUL STEPCHARGE_RFP(1) |
| 94 | #define STEPCHARGE_INM_MASK (0xF << 15) |
| 95 | #define STEPCHARGE_INM(val) ((val) << 15) |
| 96 | #define STEPCHARGE_INM_AN1 STEPCHARGE_INM(1) |
| 97 | #define STEPCHARGE_INP_MASK (0xF << 19) |
| 98 | #define STEPCHARGE_INP(val) ((val) << 19) |
| 99 | #define STEPCHARGE_INP_AN1 STEPCHARGE_INP(1) |
| 100 | #define STEPCHARGE_RFM_MASK (3 << 23) |
| 101 | #define STEPCHARGE_RFM(val) ((val) << 23) |
| 102 | #define STEPCHARGE_RFM_XNUR STEPCHARGE_RFM(1) |
| 103 | |
| 104 | /* Charge delay */ |
| 105 | #define CHARGEDLY_OPEN_MASK (0x3FFFF << 0) |
| 106 | #define CHARGEDLY_OPEN(val) ((val) << 0) |
| 107 | #define CHARGEDLY_OPENDLY CHARGEDLY_OPEN(1) |
| 108 | |
| 109 | /* Control register */ |
| 110 | #define CNTRLREG_TSCSSENB BIT(0) |
| 111 | #define CNTRLREG_STEPID BIT(1) |
| 112 | #define CNTRLREG_STEPCONFIGWRT BIT(2) |
| 113 | #define CNTRLREG_POWERDOWN BIT(4) |
| 114 | #define CNTRLREG_AFE_CTRL_MASK (3 << 5) |
| 115 | #define CNTRLREG_AFE_CTRL(val) ((val) << 5) |
| 116 | #define CNTRLREG_4WIRE CNTRLREG_AFE_CTRL(1) |
| 117 | #define CNTRLREG_5WIRE CNTRLREG_AFE_CTRL(2) |
| 118 | #define CNTRLREG_8WIRE CNTRLREG_AFE_CTRL(3) |
| 119 | #define CNTRLREG_TSCENB BIT(7) |
| 120 | |
| 121 | #define ADC_CLK 3000000 |
| 122 | #define MAX_CLK_DIV 7 |
Patil, Rachna | 5e53a69 | 2012-10-16 12:55:45 +0530 | [diff] [blame] | 123 | #define TOTAL_STEPS 16 |
| 124 | #define TOTAL_CHANNELS 8 |
Patil, Rachna | 01636eb | 2012-10-16 12:55:43 +0530 | [diff] [blame] | 125 | |
Patil, Rachna | 5e53a69 | 2012-10-16 12:55:45 +0530 | [diff] [blame] | 126 | #define TSCADC_CELLS 2 |
Patil, Rachna | 2b99baf | 2012-10-16 12:55:44 +0530 | [diff] [blame] | 127 | |
| 128 | enum tscadc_cells { |
| 129 | TSC_CELL, |
Patil, Rachna | 5e53a69 | 2012-10-16 12:55:45 +0530 | [diff] [blame] | 130 | ADC_CELL, |
Patil, Rachna | 2b99baf | 2012-10-16 12:55:44 +0530 | [diff] [blame] | 131 | }; |
Patil, Rachna | 01636eb | 2012-10-16 12:55:43 +0530 | [diff] [blame] | 132 | |
| 133 | struct mfd_tscadc_board { |
| 134 | struct tsc_data *tsc_init; |
Patil, Rachna | 5e53a69 | 2012-10-16 12:55:45 +0530 | [diff] [blame] | 135 | struct adc_data *adc_init; |
Patil, Rachna | 01636eb | 2012-10-16 12:55:43 +0530 | [diff] [blame] | 136 | }; |
| 137 | |
| 138 | struct ti_tscadc_dev { |
| 139 | struct device *dev; |
| 140 | struct regmap *regmap_tscadc; |
| 141 | void __iomem *tscadc_base; |
| 142 | int irq; |
| 143 | struct mfd_cell cells[TSCADC_CELLS]; |
Patil, Rachna | 2b99baf | 2012-10-16 12:55:44 +0530 | [diff] [blame] | 144 | |
| 145 | /* tsc device */ |
| 146 | struct titsc *tsc; |
Patil, Rachna | 5e53a69 | 2012-10-16 12:55:45 +0530 | [diff] [blame] | 147 | |
| 148 | /* adc device */ |
| 149 | struct adc_device *adc; |
Patil, Rachna | 01636eb | 2012-10-16 12:55:43 +0530 | [diff] [blame] | 150 | }; |
| 151 | |
| 152 | #endif |