Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | #ifndef __RADEON_H__ |
| 29 | #define __RADEON_H__ |
| 30 | |
| 31 | #include "radeon_object.h" |
| 32 | |
| 33 | /* TODO: Here are things that needs to be done : |
| 34 | * - surface allocator & initializer : (bit like scratch reg) should |
| 35 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
| 36 | * related to surface |
| 37 | * - WB : write back stuff (do it bit like scratch reg things) |
| 38 | * - Vblank : look at Jesse's rework and what we should do |
| 39 | * - r600/r700: gart & cp |
| 40 | * - cs : clean cs ioctl use bitmap & things like that. |
| 41 | * - power management stuff |
| 42 | * - Barrier in gart code |
| 43 | * - Unmappabled vram ? |
| 44 | * - TESTING, TESTING, TESTING |
| 45 | */ |
| 46 | |
| 47 | #include <asm/atomic.h> |
| 48 | #include <linux/wait.h> |
| 49 | #include <linux/list.h> |
| 50 | #include <linux/kref.h> |
| 51 | |
| 52 | #include "radeon_mode.h" |
| 53 | #include "radeon_reg.h" |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 54 | #include "r300.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 55 | |
| 56 | /* |
| 57 | * Modules parameters. |
| 58 | */ |
| 59 | extern int radeon_no_wb; |
| 60 | extern int radeon_modeset; |
| 61 | extern int radeon_dynclks; |
| 62 | extern int radeon_r4xx_atom; |
| 63 | extern int radeon_agpmode; |
| 64 | extern int radeon_vram_limit; |
| 65 | extern int radeon_gart_size; |
| 66 | extern int radeon_benchmarking; |
| 67 | extern int radeon_connector_table; |
| 68 | |
| 69 | /* |
| 70 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
| 71 | * symbol; |
| 72 | */ |
| 73 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
| 74 | #define RADEON_IB_POOL_SIZE 16 |
| 75 | #define RADEON_DEBUGFS_MAX_NUM_FILES 32 |
| 76 | #define RADEONFB_CONN_LIMIT 4 |
| 77 | |
| 78 | enum radeon_family { |
| 79 | CHIP_R100, |
| 80 | CHIP_RV100, |
| 81 | CHIP_RS100, |
| 82 | CHIP_RV200, |
| 83 | CHIP_RS200, |
| 84 | CHIP_R200, |
| 85 | CHIP_RV250, |
| 86 | CHIP_RS300, |
| 87 | CHIP_RV280, |
| 88 | CHIP_R300, |
| 89 | CHIP_R350, |
| 90 | CHIP_RV350, |
| 91 | CHIP_RV380, |
| 92 | CHIP_R420, |
| 93 | CHIP_R423, |
| 94 | CHIP_RV410, |
| 95 | CHIP_RS400, |
| 96 | CHIP_RS480, |
| 97 | CHIP_RS600, |
| 98 | CHIP_RS690, |
| 99 | CHIP_RS740, |
| 100 | CHIP_RV515, |
| 101 | CHIP_R520, |
| 102 | CHIP_RV530, |
| 103 | CHIP_RV560, |
| 104 | CHIP_RV570, |
| 105 | CHIP_R580, |
| 106 | CHIP_R600, |
| 107 | CHIP_RV610, |
| 108 | CHIP_RV630, |
| 109 | CHIP_RV620, |
| 110 | CHIP_RV635, |
| 111 | CHIP_RV670, |
| 112 | CHIP_RS780, |
| 113 | CHIP_RV770, |
| 114 | CHIP_RV730, |
| 115 | CHIP_RV710, |
| 116 | CHIP_LAST, |
| 117 | }; |
| 118 | |
| 119 | enum radeon_chip_flags { |
| 120 | RADEON_FAMILY_MASK = 0x0000ffffUL, |
| 121 | RADEON_FLAGS_MASK = 0xffff0000UL, |
| 122 | RADEON_IS_MOBILITY = 0x00010000UL, |
| 123 | RADEON_IS_IGP = 0x00020000UL, |
| 124 | RADEON_SINGLE_CRTC = 0x00040000UL, |
| 125 | RADEON_IS_AGP = 0x00080000UL, |
| 126 | RADEON_HAS_HIERZ = 0x00100000UL, |
| 127 | RADEON_IS_PCIE = 0x00200000UL, |
| 128 | RADEON_NEW_MEMMAP = 0x00400000UL, |
| 129 | RADEON_IS_PCI = 0x00800000UL, |
| 130 | RADEON_IS_IGPGART = 0x01000000UL, |
| 131 | }; |
| 132 | |
| 133 | |
| 134 | /* |
| 135 | * Errata workarounds. |
| 136 | */ |
| 137 | enum radeon_pll_errata { |
| 138 | CHIP_ERRATA_R300_CG = 0x00000001, |
| 139 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
| 140 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
| 141 | }; |
| 142 | |
| 143 | |
| 144 | struct radeon_device; |
| 145 | |
| 146 | |
| 147 | /* |
| 148 | * BIOS. |
| 149 | */ |
| 150 | bool radeon_get_bios(struct radeon_device *rdev); |
| 151 | |
| 152 | /* |
| 153 | * Clocks |
| 154 | */ |
| 155 | |
| 156 | struct radeon_clock { |
| 157 | struct radeon_pll p1pll; |
| 158 | struct radeon_pll p2pll; |
| 159 | struct radeon_pll spll; |
| 160 | struct radeon_pll mpll; |
| 161 | /* 10 Khz units */ |
| 162 | uint32_t default_mclk; |
| 163 | uint32_t default_sclk; |
| 164 | }; |
| 165 | |
| 166 | /* |
| 167 | * Fences. |
| 168 | */ |
| 169 | struct radeon_fence_driver { |
| 170 | uint32_t scratch_reg; |
| 171 | atomic_t seq; |
| 172 | uint32_t last_seq; |
| 173 | unsigned long count_timeout; |
| 174 | wait_queue_head_t queue; |
| 175 | rwlock_t lock; |
| 176 | struct list_head created; |
| 177 | struct list_head emited; |
| 178 | struct list_head signaled; |
| 179 | }; |
| 180 | |
| 181 | struct radeon_fence { |
| 182 | struct radeon_device *rdev; |
| 183 | struct kref kref; |
| 184 | struct list_head list; |
| 185 | /* protected by radeon_fence.lock */ |
| 186 | uint32_t seq; |
| 187 | unsigned long timeout; |
| 188 | bool emited; |
| 189 | bool signaled; |
| 190 | }; |
| 191 | |
| 192 | int radeon_fence_driver_init(struct radeon_device *rdev); |
| 193 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
| 194 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); |
| 195 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); |
| 196 | void radeon_fence_process(struct radeon_device *rdev); |
| 197 | bool radeon_fence_signaled(struct radeon_fence *fence); |
| 198 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
| 199 | int radeon_fence_wait_next(struct radeon_device *rdev); |
| 200 | int radeon_fence_wait_last(struct radeon_device *rdev); |
| 201 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
| 202 | void radeon_fence_unref(struct radeon_fence **fence); |
| 203 | |
| 204 | |
| 205 | /* |
| 206 | * Radeon buffer. |
| 207 | */ |
| 208 | struct radeon_object; |
| 209 | |
| 210 | struct radeon_object_list { |
| 211 | struct list_head list; |
| 212 | struct radeon_object *robj; |
| 213 | uint64_t gpu_offset; |
| 214 | unsigned rdomain; |
| 215 | unsigned wdomain; |
| 216 | }; |
| 217 | |
| 218 | int radeon_object_init(struct radeon_device *rdev); |
| 219 | void radeon_object_fini(struct radeon_device *rdev); |
| 220 | int radeon_object_create(struct radeon_device *rdev, |
| 221 | struct drm_gem_object *gobj, |
| 222 | unsigned long size, |
| 223 | bool kernel, |
| 224 | uint32_t domain, |
| 225 | bool interruptible, |
| 226 | struct radeon_object **robj_ptr); |
| 227 | int radeon_object_kmap(struct radeon_object *robj, void **ptr); |
| 228 | void radeon_object_kunmap(struct radeon_object *robj); |
| 229 | void radeon_object_unref(struct radeon_object **robj); |
| 230 | int radeon_object_pin(struct radeon_object *robj, uint32_t domain, |
| 231 | uint64_t *gpu_addr); |
| 232 | void radeon_object_unpin(struct radeon_object *robj); |
| 233 | int radeon_object_wait(struct radeon_object *robj); |
| 234 | int radeon_object_evict_vram(struct radeon_device *rdev); |
| 235 | int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset); |
| 236 | void radeon_object_force_delete(struct radeon_device *rdev); |
| 237 | void radeon_object_list_add_object(struct radeon_object_list *lobj, |
| 238 | struct list_head *head); |
| 239 | int radeon_object_list_validate(struct list_head *head, void *fence); |
| 240 | void radeon_object_list_unvalidate(struct list_head *head); |
| 241 | void radeon_object_list_clean(struct list_head *head); |
| 242 | int radeon_object_fbdev_mmap(struct radeon_object *robj, |
| 243 | struct vm_area_struct *vma); |
| 244 | unsigned long radeon_object_size(struct radeon_object *robj); |
| 245 | |
| 246 | |
| 247 | /* |
| 248 | * GEM objects. |
| 249 | */ |
| 250 | struct radeon_gem { |
| 251 | struct list_head objects; |
| 252 | }; |
| 253 | |
| 254 | int radeon_gem_init(struct radeon_device *rdev); |
| 255 | void radeon_gem_fini(struct radeon_device *rdev); |
| 256 | int radeon_gem_object_create(struct radeon_device *rdev, int size, |
| 257 | int alignment, int initial_domain, |
| 258 | bool discardable, bool kernel, |
| 259 | bool interruptible, |
| 260 | struct drm_gem_object **obj); |
| 261 | int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, |
| 262 | uint64_t *gpu_addr); |
| 263 | void radeon_gem_object_unpin(struct drm_gem_object *obj); |
| 264 | |
| 265 | |
| 266 | /* |
| 267 | * GART structures, functions & helpers |
| 268 | */ |
| 269 | struct radeon_mc; |
| 270 | |
| 271 | struct radeon_gart_table_ram { |
| 272 | volatile uint32_t *ptr; |
| 273 | }; |
| 274 | |
| 275 | struct radeon_gart_table_vram { |
| 276 | struct radeon_object *robj; |
| 277 | volatile uint32_t *ptr; |
| 278 | }; |
| 279 | |
| 280 | union radeon_gart_table { |
| 281 | struct radeon_gart_table_ram ram; |
| 282 | struct radeon_gart_table_vram vram; |
| 283 | }; |
| 284 | |
| 285 | struct radeon_gart { |
| 286 | dma_addr_t table_addr; |
| 287 | unsigned num_gpu_pages; |
| 288 | unsigned num_cpu_pages; |
| 289 | unsigned table_size; |
| 290 | union radeon_gart_table table; |
| 291 | struct page **pages; |
| 292 | dma_addr_t *pages_addr; |
| 293 | bool ready; |
| 294 | }; |
| 295 | |
| 296 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
| 297 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
| 298 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
| 299 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
| 300 | int radeon_gart_init(struct radeon_device *rdev); |
| 301 | void radeon_gart_fini(struct radeon_device *rdev); |
| 302 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
| 303 | int pages); |
| 304 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
| 305 | int pages, struct page **pagelist); |
| 306 | |
| 307 | |
| 308 | /* |
| 309 | * GPU MC structures, functions & helpers |
| 310 | */ |
| 311 | struct radeon_mc { |
| 312 | resource_size_t aper_size; |
| 313 | resource_size_t aper_base; |
| 314 | resource_size_t agp_base; |
| 315 | unsigned gtt_location; |
| 316 | unsigned gtt_size; |
| 317 | unsigned vram_location; |
| 318 | unsigned vram_size; |
| 319 | unsigned vram_width; |
| 320 | int vram_mtrr; |
| 321 | bool vram_is_ddr; |
| 322 | }; |
| 323 | |
| 324 | int radeon_mc_setup(struct radeon_device *rdev); |
| 325 | |
| 326 | |
| 327 | /* |
| 328 | * GPU scratch registers structures, functions & helpers |
| 329 | */ |
| 330 | struct radeon_scratch { |
| 331 | unsigned num_reg; |
| 332 | bool free[32]; |
| 333 | uint32_t reg[32]; |
| 334 | }; |
| 335 | |
| 336 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
| 337 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
| 338 | |
| 339 | |
| 340 | /* |
| 341 | * IRQS. |
| 342 | */ |
| 343 | struct radeon_irq { |
| 344 | bool installed; |
| 345 | bool sw_int; |
| 346 | /* FIXME: use a define max crtc rather than hardcode it */ |
| 347 | bool crtc_vblank_int[2]; |
| 348 | }; |
| 349 | |
| 350 | int radeon_irq_kms_init(struct radeon_device *rdev); |
| 351 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
| 352 | |
| 353 | |
| 354 | /* |
| 355 | * CP & ring. |
| 356 | */ |
| 357 | struct radeon_ib { |
| 358 | struct list_head list; |
| 359 | unsigned long idx; |
| 360 | uint64_t gpu_addr; |
| 361 | struct radeon_fence *fence; |
| 362 | volatile uint32_t *ptr; |
| 363 | uint32_t length_dw; |
| 364 | }; |
| 365 | |
| 366 | struct radeon_ib_pool { |
| 367 | struct mutex mutex; |
| 368 | struct radeon_object *robj; |
| 369 | struct list_head scheduled_ibs; |
| 370 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; |
| 371 | bool ready; |
| 372 | DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE); |
| 373 | }; |
| 374 | |
| 375 | struct radeon_cp { |
| 376 | struct radeon_object *ring_obj; |
| 377 | volatile uint32_t *ring; |
| 378 | unsigned rptr; |
| 379 | unsigned wptr; |
| 380 | unsigned wptr_old; |
| 381 | unsigned ring_size; |
| 382 | unsigned ring_free_dw; |
| 383 | int count_dw; |
| 384 | uint64_t gpu_addr; |
| 385 | uint32_t align_mask; |
| 386 | uint32_t ptr_mask; |
| 387 | struct mutex mutex; |
| 388 | bool ready; |
| 389 | }; |
| 390 | |
| 391 | int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); |
| 392 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); |
| 393 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); |
| 394 | int radeon_ib_pool_init(struct radeon_device *rdev); |
| 395 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
| 396 | int radeon_ib_test(struct radeon_device *rdev); |
| 397 | /* Ring access between begin & end cannot sleep */ |
| 398 | void radeon_ring_free_size(struct radeon_device *rdev); |
| 399 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); |
| 400 | void radeon_ring_unlock_commit(struct radeon_device *rdev); |
| 401 | void radeon_ring_unlock_undo(struct radeon_device *rdev); |
| 402 | int radeon_ring_test(struct radeon_device *rdev); |
| 403 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); |
| 404 | void radeon_ring_fini(struct radeon_device *rdev); |
| 405 | |
| 406 | |
| 407 | /* |
| 408 | * CS. |
| 409 | */ |
| 410 | struct radeon_cs_reloc { |
| 411 | struct drm_gem_object *gobj; |
| 412 | struct radeon_object *robj; |
| 413 | struct radeon_object_list lobj; |
| 414 | uint32_t handle; |
| 415 | uint32_t flags; |
| 416 | }; |
| 417 | |
| 418 | struct radeon_cs_chunk { |
| 419 | uint32_t chunk_id; |
| 420 | uint32_t length_dw; |
| 421 | uint32_t *kdata; |
| 422 | }; |
| 423 | |
| 424 | struct radeon_cs_parser { |
| 425 | struct radeon_device *rdev; |
| 426 | struct drm_file *filp; |
| 427 | /* chunks */ |
| 428 | unsigned nchunks; |
| 429 | struct radeon_cs_chunk *chunks; |
| 430 | uint64_t *chunks_array; |
| 431 | /* IB */ |
| 432 | unsigned idx; |
| 433 | /* relocations */ |
| 434 | unsigned nrelocs; |
| 435 | struct radeon_cs_reloc *relocs; |
| 436 | struct radeon_cs_reloc **relocs_ptr; |
| 437 | struct list_head validated; |
| 438 | /* indices of various chunks */ |
| 439 | int chunk_ib_idx; |
| 440 | int chunk_relocs_idx; |
| 441 | struct radeon_ib *ib; |
| 442 | void *track; |
| 443 | }; |
| 444 | |
| 445 | struct radeon_cs_packet { |
| 446 | unsigned idx; |
| 447 | unsigned type; |
| 448 | unsigned reg; |
| 449 | unsigned opcode; |
| 450 | int count; |
| 451 | unsigned one_reg_wr; |
| 452 | }; |
| 453 | |
| 454 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
| 455 | struct radeon_cs_packet *pkt, |
| 456 | unsigned idx, unsigned reg); |
| 457 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
| 458 | struct radeon_cs_packet *pkt); |
| 459 | |
| 460 | |
| 461 | /* |
| 462 | * AGP |
| 463 | */ |
| 464 | int radeon_agp_init(struct radeon_device *rdev); |
| 465 | void radeon_agp_fini(struct radeon_device *rdev); |
| 466 | |
| 467 | |
| 468 | /* |
| 469 | * Writeback |
| 470 | */ |
| 471 | struct radeon_wb { |
| 472 | struct radeon_object *wb_obj; |
| 473 | volatile uint32_t *wb; |
| 474 | uint64_t gpu_addr; |
| 475 | }; |
| 476 | |
| 477 | |
| 478 | /* |
| 479 | * Benchmarking |
| 480 | */ |
| 481 | void radeon_benchmark(struct radeon_device *rdev); |
| 482 | |
| 483 | |
| 484 | /* |
| 485 | * Debugfs |
| 486 | */ |
| 487 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
| 488 | struct drm_info_list *files, |
| 489 | unsigned nfiles); |
| 490 | int radeon_debugfs_fence_init(struct radeon_device *rdev); |
| 491 | int r100_debugfs_rbbm_init(struct radeon_device *rdev); |
| 492 | int r100_debugfs_cp_init(struct radeon_device *rdev); |
| 493 | |
| 494 | |
| 495 | /* |
| 496 | * ASIC specific functions. |
| 497 | */ |
| 498 | struct radeon_asic { |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 499 | int (*init)(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 500 | void (*errata)(struct radeon_device *rdev); |
| 501 | void (*vram_info)(struct radeon_device *rdev); |
| 502 | int (*gpu_reset)(struct radeon_device *rdev); |
| 503 | int (*mc_init)(struct radeon_device *rdev); |
| 504 | void (*mc_fini)(struct radeon_device *rdev); |
| 505 | int (*wb_init)(struct radeon_device *rdev); |
| 506 | void (*wb_fini)(struct radeon_device *rdev); |
| 507 | int (*gart_enable)(struct radeon_device *rdev); |
| 508 | void (*gart_disable)(struct radeon_device *rdev); |
| 509 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
| 510 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
| 511 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); |
| 512 | void (*cp_fini)(struct radeon_device *rdev); |
| 513 | void (*cp_disable)(struct radeon_device *rdev); |
| 514 | void (*ring_start)(struct radeon_device *rdev); |
| 515 | int (*irq_set)(struct radeon_device *rdev); |
| 516 | int (*irq_process)(struct radeon_device *rdev); |
| 517 | void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
| 518 | int (*cs_parse)(struct radeon_cs_parser *p); |
| 519 | int (*copy_blit)(struct radeon_device *rdev, |
| 520 | uint64_t src_offset, |
| 521 | uint64_t dst_offset, |
| 522 | unsigned num_pages, |
| 523 | struct radeon_fence *fence); |
| 524 | int (*copy_dma)(struct radeon_device *rdev, |
| 525 | uint64_t src_offset, |
| 526 | uint64_t dst_offset, |
| 527 | unsigned num_pages, |
| 528 | struct radeon_fence *fence); |
| 529 | int (*copy)(struct radeon_device *rdev, |
| 530 | uint64_t src_offset, |
| 531 | uint64_t dst_offset, |
| 532 | unsigned num_pages, |
| 533 | struct radeon_fence *fence); |
| 534 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
| 535 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
| 536 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
| 537 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
| 538 | }; |
| 539 | |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 540 | union radeon_asic_config { |
| 541 | struct r300_asic r300; |
| 542 | }; |
| 543 | |
Dave Airlie | 2a0f891 | 2009-07-11 04:44:47 +1000 | [diff] [blame^] | 544 | /* r100 */ |
| 545 | void r100_vram_init_sizes(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 546 | |
| 547 | /* |
| 548 | * IOCTL. |
| 549 | */ |
| 550 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, |
| 551 | struct drm_file *filp); |
| 552 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, |
| 553 | struct drm_file *filp); |
| 554 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 555 | struct drm_file *file_priv); |
| 556 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 557 | struct drm_file *file_priv); |
| 558 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 559 | struct drm_file *file_priv); |
| 560 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 561 | struct drm_file *file_priv); |
| 562 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 563 | struct drm_file *filp); |
| 564 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 565 | struct drm_file *filp); |
| 566 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 567 | struct drm_file *filp); |
| 568 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, |
| 569 | struct drm_file *filp); |
| 570 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
| 571 | |
| 572 | |
| 573 | /* |
| 574 | * Core structure, functions and helpers. |
| 575 | */ |
| 576 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
| 577 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
| 578 | |
| 579 | struct radeon_device { |
| 580 | struct drm_device *ddev; |
| 581 | struct pci_dev *pdev; |
| 582 | /* ASIC */ |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 583 | union radeon_asic_config config; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 584 | enum radeon_family family; |
| 585 | unsigned long flags; |
| 586 | int usec_timeout; |
| 587 | enum radeon_pll_errata pll_errata; |
| 588 | int num_gb_pipes; |
| 589 | int disp_priority; |
| 590 | /* BIOS */ |
| 591 | uint8_t *bios; |
| 592 | bool is_atom_bios; |
| 593 | uint16_t bios_header_start; |
| 594 | struct radeon_object *stollen_vga_memory; |
| 595 | struct fb_info *fbdev_info; |
| 596 | struct radeon_object *fbdev_robj; |
| 597 | struct radeon_framebuffer *fbdev_rfb; |
| 598 | /* Register mmio */ |
Dave Airlie | 4c9bc75 | 2009-06-29 18:29:12 +1000 | [diff] [blame] | 599 | resource_size_t rmmio_base; |
| 600 | resource_size_t rmmio_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 601 | void *rmmio; |
| 602 | radeon_rreg_t mm_rreg; |
| 603 | radeon_wreg_t mm_wreg; |
| 604 | radeon_rreg_t mc_rreg; |
| 605 | radeon_wreg_t mc_wreg; |
| 606 | radeon_rreg_t pll_rreg; |
| 607 | radeon_wreg_t pll_wreg; |
| 608 | radeon_rreg_t pcie_rreg; |
| 609 | radeon_wreg_t pcie_wreg; |
| 610 | radeon_rreg_t pciep_rreg; |
| 611 | radeon_wreg_t pciep_wreg; |
| 612 | struct radeon_clock clock; |
| 613 | struct radeon_mc mc; |
| 614 | struct radeon_gart gart; |
| 615 | struct radeon_mode_info mode_info; |
| 616 | struct radeon_scratch scratch; |
| 617 | struct radeon_mman mman; |
| 618 | struct radeon_fence_driver fence_drv; |
| 619 | struct radeon_cp cp; |
| 620 | struct radeon_ib_pool ib_pool; |
| 621 | struct radeon_irq irq; |
| 622 | struct radeon_asic *asic; |
| 623 | struct radeon_gem gem; |
| 624 | struct mutex cs_mutex; |
| 625 | struct radeon_wb wb; |
| 626 | bool gpu_lockup; |
| 627 | bool shutdown; |
| 628 | bool suspend; |
Dave Airlie | ad49f50 | 2009-07-10 22:36:26 +1000 | [diff] [blame] | 629 | bool need_dma32; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 630 | }; |
| 631 | |
| 632 | int radeon_device_init(struct radeon_device *rdev, |
| 633 | struct drm_device *ddev, |
| 634 | struct pci_dev *pdev, |
| 635 | uint32_t flags); |
| 636 | void radeon_device_fini(struct radeon_device *rdev); |
| 637 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
| 638 | |
| 639 | |
| 640 | /* |
| 641 | * Registers read & write functions. |
| 642 | */ |
| 643 | #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) |
| 644 | #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) |
| 645 | #define RREG32(reg) rdev->mm_rreg(rdev, (reg)) |
| 646 | #define WREG32(reg, v) rdev->mm_wreg(rdev, (reg), (v)) |
| 647 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
| 648 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
| 649 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
| 650 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
| 651 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
| 652 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
| 653 | #define RREG32_PCIE(reg) rdev->pcie_rreg(rdev, (reg)) |
| 654 | #define WREG32_PCIE(reg, v) rdev->pcie_wreg(rdev, (reg), (v)) |
| 655 | #define WREG32_P(reg, val, mask) \ |
| 656 | do { \ |
| 657 | uint32_t tmp_ = RREG32(reg); \ |
| 658 | tmp_ &= (mask); \ |
| 659 | tmp_ |= ((val) & ~(mask)); \ |
| 660 | WREG32(reg, tmp_); \ |
| 661 | } while (0) |
| 662 | #define WREG32_PLL_P(reg, val, mask) \ |
| 663 | do { \ |
| 664 | uint32_t tmp_ = RREG32_PLL(reg); \ |
| 665 | tmp_ &= (mask); \ |
| 666 | tmp_ |= ((val) & ~(mask)); \ |
| 667 | WREG32_PLL(reg, tmp_); \ |
| 668 | } while (0) |
| 669 | |
| 670 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
| 671 | |
| 672 | |
| 673 | /* |
| 674 | * ASICs helpers. |
| 675 | */ |
| 676 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
| 677 | (rdev->family == CHIP_RV200) || \ |
| 678 | (rdev->family == CHIP_RS100) || \ |
| 679 | (rdev->family == CHIP_RS200) || \ |
| 680 | (rdev->family == CHIP_RV250) || \ |
| 681 | (rdev->family == CHIP_RV280) || \ |
| 682 | (rdev->family == CHIP_RS300)) |
| 683 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
| 684 | (rdev->family == CHIP_RV350) || \ |
| 685 | (rdev->family == CHIP_R350) || \ |
| 686 | (rdev->family == CHIP_RV380) || \ |
| 687 | (rdev->family == CHIP_R420) || \ |
| 688 | (rdev->family == CHIP_R423) || \ |
| 689 | (rdev->family == CHIP_RV410) || \ |
| 690 | (rdev->family == CHIP_RS400) || \ |
| 691 | (rdev->family == CHIP_RS480)) |
| 692 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
| 693 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
| 694 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
| 695 | |
| 696 | |
| 697 | /* |
| 698 | * BIOS helpers. |
| 699 | */ |
| 700 | #define RBIOS8(i) (rdev->bios[i]) |
| 701 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
| 702 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
| 703 | |
| 704 | int radeon_combios_init(struct radeon_device *rdev); |
| 705 | void radeon_combios_fini(struct radeon_device *rdev); |
| 706 | int radeon_atombios_init(struct radeon_device *rdev); |
| 707 | void radeon_atombios_fini(struct radeon_device *rdev); |
| 708 | |
| 709 | |
| 710 | /* |
| 711 | * RING helpers. |
| 712 | */ |
| 713 | #define CP_PACKET0 0x00000000 |
| 714 | #define PACKET0_BASE_INDEX_SHIFT 0 |
| 715 | #define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) |
| 716 | #define PACKET0_COUNT_SHIFT 16 |
| 717 | #define PACKET0_COUNT_MASK (0x3fff << 16) |
| 718 | #define CP_PACKET1 0x40000000 |
| 719 | #define CP_PACKET2 0x80000000 |
| 720 | #define PACKET2_PAD_SHIFT 0 |
| 721 | #define PACKET2_PAD_MASK (0x3fffffff << 0) |
| 722 | #define CP_PACKET3 0xC0000000 |
| 723 | #define PACKET3_IT_OPCODE_SHIFT 8 |
| 724 | #define PACKET3_IT_OPCODE_MASK (0xff << 8) |
| 725 | #define PACKET3_COUNT_SHIFT 16 |
| 726 | #define PACKET3_COUNT_MASK (0x3fff << 16) |
| 727 | /* PACKET3 op code */ |
| 728 | #define PACKET3_NOP 0x10 |
| 729 | #define PACKET3_3D_DRAW_VBUF 0x28 |
| 730 | #define PACKET3_3D_DRAW_IMMD 0x29 |
| 731 | #define PACKET3_3D_DRAW_INDX 0x2A |
| 732 | #define PACKET3_3D_LOAD_VBPNTR 0x2F |
| 733 | #define PACKET3_INDX_BUFFER 0x33 |
| 734 | #define PACKET3_3D_DRAW_VBUF_2 0x34 |
| 735 | #define PACKET3_3D_DRAW_IMMD_2 0x35 |
| 736 | #define PACKET3_3D_DRAW_INDX_2 0x36 |
| 737 | #define PACKET3_BITBLT_MULTI 0x9B |
| 738 | |
| 739 | #define PACKET0(reg, n) (CP_PACKET0 | \ |
| 740 | REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ |
| 741 | REG_SET(PACKET0_COUNT, (n))) |
| 742 | #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) |
| 743 | #define PACKET3(op, n) (CP_PACKET3 | \ |
| 744 | REG_SET(PACKET3_IT_OPCODE, (op)) | \ |
| 745 | REG_SET(PACKET3_COUNT, (n))) |
| 746 | |
| 747 | #define PACKET_TYPE0 0 |
| 748 | #define PACKET_TYPE1 1 |
| 749 | #define PACKET_TYPE2 2 |
| 750 | #define PACKET_TYPE3 3 |
| 751 | |
| 752 | #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) |
| 753 | #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) |
| 754 | #define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) |
| 755 | #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) |
| 756 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) |
| 757 | |
| 758 | static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
| 759 | { |
| 760 | #if DRM_DEBUG_CODE |
| 761 | if (rdev->cp.count_dw <= 0) { |
| 762 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); |
| 763 | } |
| 764 | #endif |
| 765 | rdev->cp.ring[rdev->cp.wptr++] = v; |
| 766 | rdev->cp.wptr &= rdev->cp.ptr_mask; |
| 767 | rdev->cp.count_dw--; |
| 768 | rdev->cp.ring_free_dw--; |
| 769 | } |
| 770 | |
| 771 | |
| 772 | /* |
| 773 | * ASICs macro. |
| 774 | */ |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 775 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 776 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
| 777 | #define radeon_errata(rdev) (rdev)->asic->errata((rdev)) |
| 778 | #define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev)) |
| 779 | #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) |
| 780 | #define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev)) |
| 781 | #define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev)) |
| 782 | #define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev)) |
| 783 | #define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev)) |
| 784 | #define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev)) |
| 785 | #define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev)) |
| 786 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
| 787 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) |
| 788 | #define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize)) |
| 789 | #define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev)) |
| 790 | #define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev)) |
| 791 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
| 792 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
| 793 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) |
| 794 | #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
| 795 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) |
| 796 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) |
| 797 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) |
| 798 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
| 799 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
| 800 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
| 801 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) |
| 802 | |
| 803 | #endif |