Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 1 | /* |
| 2 | * File: arch/blackfin/mach-bf548/head.S |
| 3 | * Based on: arch/blackfin/mach-bf537/head.S |
| 4 | * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne |
| 5 | * |
| 6 | * Created: 1998 |
| 7 | * Description: Startup code for Blackfin BF548 |
| 8 | * |
| 9 | * Modified: |
| 10 | * Copyright 2004-2007 Analog Devices Inc. |
| 11 | * |
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License as published by |
| 16 | * the Free Software Foundation; either version 2 of the License, or |
| 17 | * (at your option) any later version. |
| 18 | * |
| 19 | * This program is distributed in the hope that it will be useful, |
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 22 | * GNU General Public License for more details. |
| 23 | * |
| 24 | * You should have received a copy of the GNU General Public License |
| 25 | * along with this program; if not, see the file COPYING, or write |
| 26 | * to the Free Software Foundation, Inc., |
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 28 | */ |
| 29 | |
| 30 | #include <linux/linkage.h> |
| 31 | #include <asm/blackfin.h> |
Robin Getz | 669b792 | 2007-06-21 16:34:08 +0800 | [diff] [blame] | 32 | #include <asm/trace.h> |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 33 | #if CONFIG_BFIN_KERNEL_CLOCK |
| 34 | #include <asm/mach/mem_init.h> |
| 35 | #endif |
| 36 | |
| 37 | .global __rambase |
| 38 | .global __ramstart |
| 39 | .global __ramend |
| 40 | .extern ___bss_stop |
| 41 | .extern ___bss_start |
| 42 | .extern _bf53x_relocate_l1_mem |
| 43 | |
| 44 | #define INITIAL_STACK 0xFFB01000 |
| 45 | |
| 46 | .text |
| 47 | |
| 48 | ENTRY(__start) |
| 49 | ENTRY(__stext) |
| 50 | /* R0: argument of command line string, passed from uboot, save it */ |
| 51 | R7 = R0; |
| 52 | /* Set the SYSCFG register */ |
| 53 | R0 = 0x36; |
| 54 | SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/ |
| 55 | R0 = 0; |
| 56 | |
| 57 | /* Clear Out All the data and pointer Registers*/ |
| 58 | R1 = R0; |
| 59 | R2 = R0; |
| 60 | R3 = R0; |
| 61 | R4 = R0; |
| 62 | R5 = R0; |
| 63 | R6 = R0; |
| 64 | |
| 65 | P0 = R0; |
| 66 | P1 = R0; |
| 67 | P2 = R0; |
| 68 | P3 = R0; |
| 69 | P4 = R0; |
| 70 | P5 = R0; |
| 71 | |
| 72 | LC0 = r0; |
| 73 | LC1 = r0; |
| 74 | L0 = r0; |
| 75 | L1 = r0; |
| 76 | L2 = r0; |
| 77 | L3 = r0; |
| 78 | |
| 79 | /* Clear Out All the DAG Registers*/ |
| 80 | B0 = r0; |
| 81 | B1 = r0; |
| 82 | B2 = r0; |
| 83 | B3 = r0; |
| 84 | |
| 85 | I0 = r0; |
| 86 | I1 = r0; |
| 87 | I2 = r0; |
| 88 | I3 = r0; |
| 89 | |
| 90 | M0 = r0; |
| 91 | M1 = r0; |
| 92 | M2 = r0; |
| 93 | M3 = r0; |
| 94 | |
Robin Getz | 669b792 | 2007-06-21 16:34:08 +0800 | [diff] [blame] | 95 | trace_buffer_start(p0,r0); |
| 96 | P0 = R1; |
| 97 | R0 = R1; |
| 98 | |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 99 | /* Turn off the icache */ |
Mike Frysinger | e208f83 | 2007-07-25 10:11:42 +0800 | [diff] [blame] | 100 | p0.l = LO(IMEM_CONTROL); |
| 101 | p0.h = HI(IMEM_CONTROL); |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 102 | R1 = [p0]; |
| 103 | R0 = ~ENICPLB; |
| 104 | R0 = R0 & R1; |
| 105 | [p0] = R0; |
| 106 | SSYNC; |
| 107 | |
| 108 | /* Turn off the dcache */ |
Mike Frysinger | e208f83 | 2007-07-25 10:11:42 +0800 | [diff] [blame] | 109 | p0.l = LO(DMEM_CONTROL); |
| 110 | p0.h = HI(DMEM_CONTROL); |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 111 | R1 = [p0]; |
| 112 | R0 = ~ENDCPLB; |
| 113 | R0 = R0 & R1; |
| 114 | [p0] = R0; |
| 115 | SSYNC; |
| 116 | |
| 117 | /* Initialize stack pointer */ |
| 118 | SP.L = LO(INITIAL_STACK); |
| 119 | SP.H = HI(INITIAL_STACK); |
| 120 | FP = SP; |
| 121 | USP = SP; |
| 122 | |
| 123 | /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */ |
| 124 | call _bf53x_relocate_l1_mem; |
| 125 | #if CONFIG_BFIN_KERNEL_CLOCK |
| 126 | call _start_dma_code; |
| 127 | #endif |
| 128 | /* Code for initializing Async memory banks */ |
| 129 | |
| 130 | p2.h = hi(EBIU_AMBCTL1); |
| 131 | p2.l = lo(EBIU_AMBCTL1); |
| 132 | r0.h = hi(AMBCTL1VAL); |
| 133 | r0.l = lo(AMBCTL1VAL); |
| 134 | [p2] = r0; |
| 135 | ssync; |
| 136 | |
| 137 | p2.h = hi(EBIU_AMBCTL0); |
| 138 | p2.l = lo(EBIU_AMBCTL0); |
| 139 | r0.h = hi(AMBCTL0VAL); |
| 140 | r0.l = lo(AMBCTL0VAL); |
| 141 | [p2] = r0; |
| 142 | ssync; |
| 143 | |
| 144 | p2.h = hi(EBIU_AMGCTL); |
| 145 | p2.l = lo(EBIU_AMGCTL); |
| 146 | r0 = AMGCTLVAL; |
| 147 | w[p2] = r0; |
| 148 | ssync; |
| 149 | |
| 150 | /* This section keeps the processor in supervisor mode |
| 151 | * during kernel boot. Switches to user mode at end of boot. |
| 152 | * See page 3-9 of Hardware Reference manual for documentation. |
| 153 | */ |
| 154 | |
| 155 | /* EVT15 = _real_start */ |
| 156 | |
| 157 | p0.l = lo(EVT15); |
| 158 | p0.h = hi(EVT15); |
| 159 | p1.l = _real_start; |
| 160 | p1.h = _real_start; |
| 161 | [p0] = p1; |
| 162 | csync; |
| 163 | |
| 164 | p0.l = lo(IMASK); |
| 165 | p0.h = hi(IMASK); |
| 166 | p1.l = IMASK_IVG15; |
| 167 | p1.h = 0x0; |
| 168 | [p0] = p1; |
| 169 | csync; |
| 170 | |
| 171 | raise 15; |
| 172 | p0.l = .LWAIT_HERE; |
| 173 | p0.h = .LWAIT_HERE; |
| 174 | reti = p0; |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 175 | #if ANOMALY_05000281 |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 176 | nop; |
| 177 | nop; |
| 178 | nop; |
| 179 | #endif |
| 180 | rti; |
| 181 | |
| 182 | .LWAIT_HERE: |
| 183 | jump .LWAIT_HERE; |
| 184 | |
| 185 | ENTRY(_real_start) |
| 186 | [ -- sp ] = reti; |
| 187 | p0.l = lo(WDOG_CTL); |
| 188 | p0.h = hi(WDOG_CTL); |
| 189 | r0 = 0xAD6(z); |
| 190 | w[p0] = r0; /* watchdog off for now */ |
| 191 | ssync; |
| 192 | |
| 193 | /* Code update for BSS size == 0 |
| 194 | * Zero out the bss region. |
| 195 | */ |
| 196 | |
| 197 | p1.l = ___bss_start; |
| 198 | p1.h = ___bss_start; |
| 199 | p2.l = ___bss_stop; |
| 200 | p2.h = ___bss_stop; |
| 201 | r0 = 0; |
| 202 | p2 -= p1; |
| 203 | lsetup (.L_clear_bss, .L_clear_bss ) lc0 = p2; |
| 204 | .L_clear_bss: |
| 205 | B[p1++] = r0; |
| 206 | |
| 207 | /* In case there is a NULL pointer reference |
| 208 | * Zero out region before stext |
| 209 | */ |
| 210 | |
| 211 | p1.l = 0x0; |
| 212 | p1.h = 0x0; |
| 213 | r0.l = __stext; |
| 214 | r0.h = __stext; |
| 215 | r0 = r0 >> 1; |
| 216 | p2 = r0; |
| 217 | r0 = 0; |
| 218 | lsetup (.L_clear_zero, .L_clear_zero ) lc0 = p2; |
| 219 | .L_clear_zero: |
| 220 | W[p1++] = r0; |
| 221 | |
| 222 | /* pass the uboot arguments to the global value command line */ |
| 223 | R0 = R7; |
| 224 | call _cmdline_init; |
| 225 | |
| 226 | p1.l = __rambase; |
| 227 | p1.h = __rambase; |
| 228 | r0.l = __sdata; |
| 229 | r0.h = __sdata; |
| 230 | [p1] = r0; |
| 231 | |
| 232 | p1.l = __ramstart; |
| 233 | p1.h = __ramstart; |
| 234 | p3.l = ___bss_stop; |
| 235 | p3.h = ___bss_stop; |
| 236 | |
| 237 | r1 = p3; |
| 238 | [p1] = r1; |
| 239 | |
| 240 | |
| 241 | /* |
| 242 | * load the current thread pointer and stack |
| 243 | */ |
| 244 | r1.l = _init_thread_union; |
| 245 | r1.h = _init_thread_union; |
| 246 | |
| 247 | r2.l = 0x2000; |
| 248 | r2.h = 0x0000; |
| 249 | r1 = r1 + r2; |
| 250 | sp = r1; |
| 251 | usp = sp; |
| 252 | fp = sp; |
| 253 | call _start_kernel; |
| 254 | .L_exit: |
| 255 | jump.s .L_exit; |
| 256 | |
| 257 | .section .l1.text |
| 258 | #if CONFIG_BFIN_KERNEL_CLOCK |
| 259 | ENTRY(_start_dma_code) |
| 260 | |
| 261 | /* Enable PHY CLK buffer output */ |
| 262 | p0.h = hi(VR_CTL); |
| 263 | p0.l = lo(VR_CTL); |
| 264 | r0.l = w[p0]; |
| 265 | bitset(r0, 14); |
| 266 | w[p0] = r0.l; |
| 267 | ssync; |
| 268 | |
| 269 | p0.h = hi(SIC_IWR); |
| 270 | p0.l = lo(SIC_IWR); |
| 271 | r0.l = 0x1; |
| 272 | r0.h = 0x0; |
| 273 | [p0] = r0; |
| 274 | SSYNC; |
| 275 | |
| 276 | /* |
| 277 | * Set PLL_CTL |
| 278 | * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors |
| 279 | * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK |
| 280 | * - [7] = output delay (add 200ps of delay to mem signals) |
| 281 | * - [6] = input delay (add 200ps of input delay to mem signals) |
| 282 | * - [5] = PDWN : 1=All Clocks off |
| 283 | * - [3] = STOPCK : 1=Core Clock off |
| 284 | * - [1] = PLL_OFF : 1=Disable Power to PLL |
| 285 | * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL |
| 286 | * all other bits set to zero |
| 287 | */ |
| 288 | |
| 289 | p0.h = hi(PLL_LOCKCNT); |
| 290 | p0.l = lo(PLL_LOCKCNT); |
| 291 | r0 = 0x300(Z); |
| 292 | w[p0] = r0.l; |
| 293 | ssync; |
| 294 | |
| 295 | P2.H = hi(EBIU_SDGCTL); |
| 296 | P2.L = lo(EBIU_SDGCTL); |
| 297 | R0 = [P2]; |
| 298 | BITSET (R0, 24); |
| 299 | [P2] = R0; |
| 300 | SSYNC; |
| 301 | |
| 302 | r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ |
| 303 | r0 = r0 << 9; /* Shift it over, */ |
| 304 | r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/ |
| 305 | r0 = r1 | r0; |
| 306 | r1 = PLL_BYPASS; /* Bypass the PLL? */ |
| 307 | r1 = r1 << 8; /* Shift it over */ |
| 308 | r0 = r1 | r0; /* add them all together */ |
| 309 | |
| 310 | p0.h = hi(PLL_CTL); |
| 311 | p0.l = lo(PLL_CTL); /* Load the address */ |
| 312 | cli r2; /* Disable interrupts */ |
| 313 | ssync; |
| 314 | w[p0] = r0.l; /* Set the value */ |
| 315 | idle; /* Wait for the PLL to stablize */ |
| 316 | sti r2; /* Enable interrupts */ |
| 317 | |
| 318 | .Lcheck_again: |
| 319 | p0.h = hi(PLL_STAT); |
| 320 | p0.l = lo(PLL_STAT); |
| 321 | R0 = W[P0](Z); |
| 322 | CC = BITTST(R0,5); |
| 323 | if ! CC jump .Lcheck_again; |
| 324 | |
| 325 | /* Configure SCLK & CCLK Dividers */ |
| 326 | r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); |
| 327 | p0.h = hi(PLL_DIV); |
| 328 | p0.l = lo(PLL_DIV); |
| 329 | w[p0] = r0.l; |
| 330 | ssync; |
| 331 | |
| 332 | p0.l = lo(EBIU_SDRRC); |
| 333 | p0.h = hi(EBIU_SDRRC); |
| 334 | r0 = mem_SDRRC; |
| 335 | w[p0] = r0.l; |
| 336 | ssync; |
| 337 | |
Mike Frysinger | e208f83 | 2007-07-25 10:11:42 +0800 | [diff] [blame] | 338 | p0.l = LO(EBIU_SDBCTL); |
| 339 | p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */ |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 340 | r0 = mem_SDBCTL; |
| 341 | w[p0] = r0.l; |
| 342 | ssync; |
| 343 | |
| 344 | P2.H = hi(EBIU_SDGCTL); |
| 345 | P2.L = lo(EBIU_SDGCTL); |
| 346 | R0 = [P2]; |
| 347 | BITCLR (R0, 24); |
| 348 | p0.h = hi(EBIU_SDSTAT); |
| 349 | p0.l = lo(EBIU_SDSTAT); |
| 350 | r2.l = w[p0]; |
| 351 | cc = bittst(r2,3); |
| 352 | if !cc jump .Lskip; |
| 353 | NOP; |
| 354 | BITSET (R0, 23); |
| 355 | .Lskip: |
| 356 | [P2] = R0; |
| 357 | SSYNC; |
| 358 | |
| 359 | R0.L = lo(mem_SDGCTL); |
| 360 | R0.H = hi(mem_SDGCTL); |
| 361 | R1 = [p2]; |
| 362 | R1 = R1 | R0; |
| 363 | [P2] = R1; |
| 364 | SSYNC; |
| 365 | |
| 366 | p0.h = hi(SIC_IWR); |
| 367 | p0.l = lo(SIC_IWR); |
| 368 | r0.l = lo(IWR_ENABLE_ALL); |
| 369 | r0.h = hi(IWR_ENABLE_ALL); |
| 370 | [p0] = r0; |
| 371 | SSYNC; |
| 372 | |
| 373 | RTS; |
| 374 | #endif /* CONFIG_BFIN_KERNEL_CLOCK */ |
| 375 | |
| 376 | ENTRY(_bfin_reset) |
| 377 | /* No more interrupts to be handled*/ |
| 378 | CLI R6; |
| 379 | SSYNC; |
| 380 | |
| 381 | #if defined(CONFIG_MTD_M25P80) |
| 382 | /* |
| 383 | * The following code fix the SPI flash reboot issue, |
| 384 | * /CS signal of the chip which is using PF10 return to GPIO mode |
| 385 | */ |
| 386 | p0.h = hi(PORTF_FER); |
| 387 | p0.l = lo(PORTF_FER); |
| 388 | r0.l = 0x0000; |
| 389 | w[p0] = r0.l; |
| 390 | SSYNC; |
| 391 | |
| 392 | /* /CS return to high */ |
| 393 | p0.h = hi(PORTFIO); |
| 394 | p0.l = lo(PORTFIO); |
| 395 | r0.l = 0xFFFF; |
| 396 | w[p0] = r0.l; |
| 397 | SSYNC; |
| 398 | |
| 399 | /* Delay some time, This is necessary */ |
| 400 | r1.h = 0; |
| 401 | r1.l = 0x400; |
| 402 | p1 = r1; |
| 403 | lsetup (_delay_lab1,_delay_lab1_end ) lc1 = p1; |
| 404 | _delay_lab1: |
| 405 | r0.h = 0; |
| 406 | r0.l = 0x8000; |
| 407 | p0 = r0; |
| 408 | lsetup (_delay_lab0,_delay_lab0_end ) lc0 = p0; |
| 409 | _delay_lab0: |
| 410 | nop; |
| 411 | _delay_lab0_end: |
| 412 | nop; |
| 413 | _delay_lab1_end: |
| 414 | nop; |
| 415 | #endif |
| 416 | |
| 417 | /* Clear the bits 13-15 in SWRST if they werent cleared */ |
| 418 | p0.h = hi(SWRST); |
| 419 | p0.l = lo(SWRST); |
| 420 | csync; |
| 421 | r0.l = w[p0]; |
| 422 | |
| 423 | /* Clear the IMASK register */ |
| 424 | p0.h = hi(IMASK); |
| 425 | p0.l = lo(IMASK); |
| 426 | r0 = 0x0; |
| 427 | [p0] = r0; |
| 428 | |
| 429 | /* Clear the ILAT register */ |
| 430 | p0.h = hi(ILAT); |
| 431 | p0.l = lo(ILAT); |
| 432 | r0 = [p0]; |
| 433 | [p0] = r0; |
| 434 | SSYNC; |
| 435 | |
| 436 | /* Disable the WDOG TIMER */ |
| 437 | p0.h = hi(WDOG_CTL); |
| 438 | p0.l = lo(WDOG_CTL); |
| 439 | r0.l = 0xAD6; |
| 440 | w[p0] = r0.l; |
| 441 | SSYNC; |
| 442 | |
| 443 | /* Clear the sticky bit incase it is already set */ |
| 444 | p0.h = hi(WDOG_CTL); |
| 445 | p0.l = lo(WDOG_CTL); |
| 446 | r0.l = 0x8AD6; |
| 447 | w[p0] = r0.l; |
| 448 | SSYNC; |
| 449 | |
| 450 | /* Program the count value */ |
| 451 | R0.l = 0x100; |
| 452 | R0.h = 0x0; |
| 453 | P0.h = hi(WDOG_CNT); |
| 454 | P0.l = lo(WDOG_CNT); |
| 455 | [P0] = R0; |
| 456 | SSYNC; |
| 457 | |
| 458 | /* Program WDOG_STAT if necessary */ |
| 459 | P0.h = hi(WDOG_CTL); |
| 460 | P0.l = lo(WDOG_CTL); |
| 461 | R0 = W[P0](Z); |
| 462 | CC = BITTST(R0,1); |
| 463 | if !CC JUMP .LWRITESTAT; |
| 464 | CC = BITTST(R0,2); |
| 465 | if !CC JUMP .LWRITESTAT; |
| 466 | JUMP .LSKIP_WRITE; |
| 467 | |
| 468 | .LWRITESTAT: |
| 469 | /* When watch dog timer is enabled, |
| 470 | * a write to STAT will load the contents of CNT to STAT |
| 471 | */ |
| 472 | R0 = 0x0000(z); |
| 473 | P0.h = hi(WDOG_STAT); |
| 474 | P0.l = lo(WDOG_STAT) |
| 475 | [P0] = R0; |
| 476 | SSYNC; |
| 477 | |
| 478 | .LSKIP_WRITE: |
| 479 | /* Enable the reset event */ |
| 480 | P0.h = hi(WDOG_CTL); |
| 481 | P0.l = lo(WDOG_CTL); |
| 482 | R0 = W[P0](Z); |
| 483 | BITCLR(R0,1); |
| 484 | BITCLR(R0,2); |
| 485 | W[P0] = R0.L; |
| 486 | SSYNC; |
| 487 | NOP; |
| 488 | |
| 489 | /* Enable the wdog counter */ |
| 490 | R0 = W[P0](Z); |
| 491 | BITCLR(R0,4); |
| 492 | W[P0] = R0.L; |
| 493 | SSYNC; |
| 494 | |
| 495 | IDLE; |
| 496 | |
| 497 | RTS; |
| 498 | |
| 499 | .data |
| 500 | |
| 501 | /* |
| 502 | * Set up the usable of RAM stuff. Size of RAM is determined then |
| 503 | * an initial stack set up at the end. |
| 504 | */ |
| 505 | |
| 506 | .align 4 |
| 507 | __rambase: |
| 508 | .long 0 |
| 509 | __ramstart: |
| 510 | .long 0 |
| 511 | __ramend: |
| 512 | .long 0 |