blob: d5a5d4d9c19bb9efc3dd084e2961fd99d1d098f6 [file] [log] [blame]
Sascha Hauer1ec1e822010-09-30 13:56:34 +00001/*
2 * drivers/dma/imx-sdma.c
3 *
4 * This file contains a driver for the Freescale Smart DMA engine
5 *
6 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
7 *
8 * Based on code from Freescale:
9 *
10 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
11 *
12 * The code contained herein is licensed under the GNU General Public
13 * License. You may obtain a copy of the GNU General Public License
14 * Version 2 or later at the following locations:
15 *
16 * http://www.opensource.org/licenses/gpl-license.html
17 * http://www.gnu.org/copyleft/gpl.html
18 */
19
20#include <linux/init.h>
21#include <linux/types.h>
22#include <linux/mm.h>
23#include <linux/interrupt.h>
24#include <linux/clk.h>
25#include <linux/wait.h>
26#include <linux/sched.h>
27#include <linux/semaphore.h>
28#include <linux/spinlock.h>
29#include <linux/device.h>
30#include <linux/dma-mapping.h>
31#include <linux/firmware.h>
32#include <linux/slab.h>
33#include <linux/platform_device.h>
34#include <linux/dmaengine.h>
35
36#include <asm/irq.h>
37#include <mach/sdma.h>
38#include <mach/dma.h>
39#include <mach/hardware.h>
40
41/* SDMA registers */
42#define SDMA_H_C0PTR 0x000
43#define SDMA_H_INTR 0x004
44#define SDMA_H_STATSTOP 0x008
45#define SDMA_H_START 0x00c
46#define SDMA_H_EVTOVR 0x010
47#define SDMA_H_DSPOVR 0x014
48#define SDMA_H_HOSTOVR 0x018
49#define SDMA_H_EVTPEND 0x01c
50#define SDMA_H_DSPENBL 0x020
51#define SDMA_H_RESET 0x024
52#define SDMA_H_EVTERR 0x028
53#define SDMA_H_INTRMSK 0x02c
54#define SDMA_H_PSW 0x030
55#define SDMA_H_EVTERRDBG 0x034
56#define SDMA_H_CONFIG 0x038
57#define SDMA_ONCE_ENB 0x040
58#define SDMA_ONCE_DATA 0x044
59#define SDMA_ONCE_INSTR 0x048
60#define SDMA_ONCE_STAT 0x04c
61#define SDMA_ONCE_CMD 0x050
62#define SDMA_EVT_MIRROR 0x054
63#define SDMA_ILLINSTADDR 0x058
64#define SDMA_CHN0ADDR 0x05c
65#define SDMA_ONCE_RTB 0x060
66#define SDMA_XTRIG_CONF1 0x070
67#define SDMA_XTRIG_CONF2 0x074
68#define SDMA_CHNENBL0_V2 0x200
69#define SDMA_CHNENBL0_V1 0x080
70#define SDMA_CHNPRI_0 0x100
71
72/*
73 * Buffer descriptor status values.
74 */
75#define BD_DONE 0x01
76#define BD_WRAP 0x02
77#define BD_CONT 0x04
78#define BD_INTR 0x08
79#define BD_RROR 0x10
80#define BD_LAST 0x20
81#define BD_EXTD 0x80
82
83/*
84 * Data Node descriptor status values.
85 */
86#define DND_END_OF_FRAME 0x80
87#define DND_END_OF_XFER 0x40
88#define DND_DONE 0x20
89#define DND_UNUSED 0x01
90
91/*
92 * IPCV2 descriptor status values.
93 */
94#define BD_IPCV2_END_OF_FRAME 0x40
95
96#define IPCV2_MAX_NODES 50
97/*
98 * Error bit set in the CCB status field by the SDMA,
99 * in setbd routine, in case of a transfer error
100 */
101#define DATA_ERROR 0x10000000
102
103/*
104 * Buffer descriptor commands.
105 */
106#define C0_ADDR 0x01
107#define C0_LOAD 0x02
108#define C0_DUMP 0x03
109#define C0_SETCTX 0x07
110#define C0_GETCTX 0x03
111#define C0_SETDM 0x01
112#define C0_SETPM 0x04
113#define C0_GETDM 0x02
114#define C0_GETPM 0x08
115/*
116 * Change endianness indicator in the BD command field
117 */
118#define CHANGE_ENDIANNESS 0x80
119
120/*
121 * Mode/Count of data node descriptors - IPCv2
122 */
123struct sdma_mode_count {
124 u32 count : 16; /* size of the buffer pointed by this BD */
125 u32 status : 8; /* E,R,I,C,W,D status bits stored here */
126 u32 command : 8; /* command mostlky used for channel 0 */
127};
128
129/*
130 * Buffer descriptor
131 */
132struct sdma_buffer_descriptor {
133 struct sdma_mode_count mode;
134 u32 buffer_addr; /* address of the buffer described */
135 u32 ext_buffer_addr; /* extended buffer address */
136} __attribute__ ((packed));
137
138/**
139 * struct sdma_channel_control - Channel control Block
140 *
141 * @current_bd_ptr current buffer descriptor processed
142 * @base_bd_ptr first element of buffer descriptor array
143 * @unused padding. The SDMA engine expects an array of 128 byte
144 * control blocks
145 */
146struct sdma_channel_control {
147 u32 current_bd_ptr;
148 u32 base_bd_ptr;
149 u32 unused[2];
150} __attribute__ ((packed));
151
152/**
153 * struct sdma_state_registers - SDMA context for a channel
154 *
155 * @pc: program counter
156 * @t: test bit: status of arithmetic & test instruction
157 * @rpc: return program counter
158 * @sf: source fault while loading data
159 * @spc: loop start program counter
160 * @df: destination fault while storing data
161 * @epc: loop end program counter
162 * @lm: loop mode
163 */
164struct sdma_state_registers {
165 u32 pc :14;
166 u32 unused1: 1;
167 u32 t : 1;
168 u32 rpc :14;
169 u32 unused0: 1;
170 u32 sf : 1;
171 u32 spc :14;
172 u32 unused2: 1;
173 u32 df : 1;
174 u32 epc :14;
175 u32 lm : 2;
176} __attribute__ ((packed));
177
178/**
179 * struct sdma_context_data - sdma context specific to a channel
180 *
181 * @channel_state: channel state bits
182 * @gReg: general registers
183 * @mda: burst dma destination address register
184 * @msa: burst dma source address register
185 * @ms: burst dma status register
186 * @md: burst dma data register
187 * @pda: peripheral dma destination address register
188 * @psa: peripheral dma source address register
189 * @ps: peripheral dma status register
190 * @pd: peripheral dma data register
191 * @ca: CRC polynomial register
192 * @cs: CRC accumulator register
193 * @dda: dedicated core destination address register
194 * @dsa: dedicated core source address register
195 * @ds: dedicated core status register
196 * @dd: dedicated core data register
197 */
198struct sdma_context_data {
199 struct sdma_state_registers channel_state;
200 u32 gReg[8];
201 u32 mda;
202 u32 msa;
203 u32 ms;
204 u32 md;
205 u32 pda;
206 u32 psa;
207 u32 ps;
208 u32 pd;
209 u32 ca;
210 u32 cs;
211 u32 dda;
212 u32 dsa;
213 u32 ds;
214 u32 dd;
215 u32 scratch0;
216 u32 scratch1;
217 u32 scratch2;
218 u32 scratch3;
219 u32 scratch4;
220 u32 scratch5;
221 u32 scratch6;
222 u32 scratch7;
223} __attribute__ ((packed));
224
225#define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
226
227struct sdma_engine;
228
229/**
230 * struct sdma_channel - housekeeping for a SDMA channel
231 *
232 * @sdma pointer to the SDMA engine for this channel
233 * @channel the channel number, matches dmaengine chan_id
234 * @direction transfer type. Needed for setting SDMA script
235 * @peripheral_type Peripheral type. Needed for setting SDMA script
236 * @event_id0 aka dma request line
237 * @event_id1 for channels that use 2 events
238 * @word_size peripheral access size
239 * @buf_tail ID of the buffer that was processed
240 * @done channel completion
241 * @num_bd max NUM_BD. number of descriptors currently handling
242 */
243struct sdma_channel {
244 struct sdma_engine *sdma;
245 unsigned int channel;
246 enum dma_data_direction direction;
247 enum sdma_peripheral_type peripheral_type;
248 unsigned int event_id0;
249 unsigned int event_id1;
250 enum dma_slave_buswidth word_size;
251 unsigned int buf_tail;
252 struct completion done;
253 unsigned int num_bd;
254 struct sdma_buffer_descriptor *bd;
255 dma_addr_t bd_phys;
256 unsigned int pc_from_device, pc_to_device;
257 unsigned long flags;
258 dma_addr_t per_address;
259 u32 event_mask0, event_mask1;
260 u32 watermark_level;
261 u32 shp_addr, per_addr;
262 struct dma_chan chan;
263 spinlock_t lock;
264 struct dma_async_tx_descriptor desc;
265 dma_cookie_t last_completed;
266 enum dma_status status;
267};
268
269#define IMX_DMA_SG_LOOP (1 << 0)
270
271#define MAX_DMA_CHANNELS 32
272#define MXC_SDMA_DEFAULT_PRIORITY 1
273#define MXC_SDMA_MIN_PRIORITY 1
274#define MXC_SDMA_MAX_PRIORITY 7
275
Sascha Hauer1ec1e822010-09-30 13:56:34 +0000276#define SDMA_FIRMWARE_MAGIC 0x414d4453
277
278/**
279 * struct sdma_firmware_header - Layout of the firmware image
280 *
281 * @magic "SDMA"
282 * @version_major increased whenever layout of struct sdma_script_start_addrs
283 * changes.
284 * @version_minor firmware minor version (for binary compatible changes)
285 * @script_addrs_start offset of struct sdma_script_start_addrs in this image
286 * @num_script_addrs Number of script addresses in this image
287 * @ram_code_start offset of SDMA ram image in this firmware image
288 * @ram_code_size size of SDMA ram image
289 * @script_addrs Stores the start address of the SDMA scripts
290 * (in SDMA memory space)
291 */
292struct sdma_firmware_header {
293 u32 magic;
294 u32 version_major;
295 u32 version_minor;
296 u32 script_addrs_start;
297 u32 num_script_addrs;
298 u32 ram_code_start;
299 u32 ram_code_size;
300};
301
302struct sdma_engine {
303 struct device *dev;
304 struct sdma_channel channel[MAX_DMA_CHANNELS];
305 struct sdma_channel_control *channel_control;
306 void __iomem *regs;
307 unsigned int version;
308 unsigned int num_events;
309 struct sdma_context_data *context;
310 dma_addr_t context_phys;
311 struct dma_device dma_device;
312 struct clk *clk;
313 struct sdma_script_start_addrs *script_addrs;
314};
315
316#define SDMA_H_CONFIG_DSPDMA (1 << 12) /* indicates if the DSPDMA is used */
317#define SDMA_H_CONFIG_RTD_PINS (1 << 11) /* indicates if Real-Time Debug pins are enabled */
318#define SDMA_H_CONFIG_ACR (1 << 4) /* indicates if AHB freq /core freq = 2 or 1 */
319#define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
320
321static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
322{
323 u32 chnenbl0 = (sdma->version == 2 ? SDMA_CHNENBL0_V2 : SDMA_CHNENBL0_V1);
324
325 return chnenbl0 + event * 4;
326}
327
328static int sdma_config_ownership(struct sdma_channel *sdmac,
329 bool event_override, bool mcu_override, bool dsp_override)
330{
331 struct sdma_engine *sdma = sdmac->sdma;
332 int channel = sdmac->channel;
333 u32 evt, mcu, dsp;
334
335 if (event_override && mcu_override && dsp_override)
336 return -EINVAL;
337
338 evt = __raw_readl(sdma->regs + SDMA_H_EVTOVR);
339 mcu = __raw_readl(sdma->regs + SDMA_H_HOSTOVR);
340 dsp = __raw_readl(sdma->regs + SDMA_H_DSPOVR);
341
342 if (dsp_override)
343 dsp &= ~(1 << channel);
344 else
345 dsp |= (1 << channel);
346
347 if (event_override)
348 evt &= ~(1 << channel);
349 else
350 evt |= (1 << channel);
351
352 if (mcu_override)
353 mcu &= ~(1 << channel);
354 else
355 mcu |= (1 << channel);
356
357 __raw_writel(evt, sdma->regs + SDMA_H_EVTOVR);
358 __raw_writel(mcu, sdma->regs + SDMA_H_HOSTOVR);
359 __raw_writel(dsp, sdma->regs + SDMA_H_DSPOVR);
360
361 return 0;
362}
363
364/*
365 * sdma_run_channel - run a channel and wait till it's done
366 */
367static int sdma_run_channel(struct sdma_channel *sdmac)
368{
369 struct sdma_engine *sdma = sdmac->sdma;
370 int channel = sdmac->channel;
371 int ret;
372
373 init_completion(&sdmac->done);
374
375 __raw_writel(1 << channel, sdma->regs + SDMA_H_START);
376
377 ret = wait_for_completion_timeout(&sdmac->done, HZ);
378
379 return ret ? 0 : -ETIMEDOUT;
380}
381
382static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
383 u32 address)
384{
385 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
386 void *buf_virt;
387 dma_addr_t buf_phys;
388 int ret;
389
390 buf_virt = dma_alloc_coherent(NULL,
391 size,
392 &buf_phys, GFP_KERNEL);
393 if (!buf_virt)
394 return -ENOMEM;
395
396 bd0->mode.command = C0_SETPM;
397 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
398 bd0->mode.count = size / 2;
399 bd0->buffer_addr = buf_phys;
400 bd0->ext_buffer_addr = address;
401
402 memcpy(buf_virt, buf, size);
403
404 ret = sdma_run_channel(&sdma->channel[0]);
405
406 dma_free_coherent(NULL, size, buf_virt, buf_phys);
407
408 return ret;
409}
410
411static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
412{
413 struct sdma_engine *sdma = sdmac->sdma;
414 int channel = sdmac->channel;
415 u32 val;
416 u32 chnenbl = chnenbl_ofs(sdma, event);
417
418 val = __raw_readl(sdma->regs + chnenbl);
419 val |= (1 << channel);
420 __raw_writel(val, sdma->regs + chnenbl);
421}
422
423static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
424{
425 struct sdma_engine *sdma = sdmac->sdma;
426 int channel = sdmac->channel;
427 u32 chnenbl = chnenbl_ofs(sdma, event);
428 u32 val;
429
430 val = __raw_readl(sdma->regs + chnenbl);
431 val &= ~(1 << channel);
432 __raw_writel(val, sdma->regs + chnenbl);
433}
434
435static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
436{
437 struct sdma_buffer_descriptor *bd;
438
439 /*
440 * loop mode. Iterate over descriptors, re-setup them and
441 * call callback function.
442 */
443 while (1) {
444 bd = &sdmac->bd[sdmac->buf_tail];
445
446 if (bd->mode.status & BD_DONE)
447 break;
448
449 if (bd->mode.status & BD_RROR)
450 sdmac->status = DMA_ERROR;
451 else
452 sdmac->status = DMA_SUCCESS;
453
454 bd->mode.status |= BD_DONE;
455 sdmac->buf_tail++;
456 sdmac->buf_tail %= sdmac->num_bd;
457
458 if (sdmac->desc.callback)
459 sdmac->desc.callback(sdmac->desc.callback_param);
460 }
461}
462
463static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
464{
465 struct sdma_buffer_descriptor *bd;
466 int i, error = 0;
467
468 /*
469 * non loop mode. Iterate over all descriptors, collect
470 * errors and call callback function
471 */
472 for (i = 0; i < sdmac->num_bd; i++) {
473 bd = &sdmac->bd[i];
474
475 if (bd->mode.status & (BD_DONE | BD_RROR))
476 error = -EIO;
477 }
478
479 if (error)
480 sdmac->status = DMA_ERROR;
481 else
482 sdmac->status = DMA_SUCCESS;
483
484 if (sdmac->desc.callback)
485 sdmac->desc.callback(sdmac->desc.callback_param);
486 sdmac->last_completed = sdmac->desc.cookie;
487}
488
489static void mxc_sdma_handle_channel(struct sdma_channel *sdmac)
490{
491 complete(&sdmac->done);
492
493 /* not interested in channel 0 interrupts */
494 if (sdmac->channel == 0)
495 return;
496
497 if (sdmac->flags & IMX_DMA_SG_LOOP)
498 sdma_handle_channel_loop(sdmac);
499 else
500 mxc_sdma_handle_channel_normal(sdmac);
501}
502
503static irqreturn_t sdma_int_handler(int irq, void *dev_id)
504{
505 struct sdma_engine *sdma = dev_id;
506 u32 stat;
507
508 stat = __raw_readl(sdma->regs + SDMA_H_INTR);
509 __raw_writel(stat, sdma->regs + SDMA_H_INTR);
510
511 while (stat) {
512 int channel = fls(stat) - 1;
513 struct sdma_channel *sdmac = &sdma->channel[channel];
514
515 mxc_sdma_handle_channel(sdmac);
516
517 stat &= ~(1 << channel);
518 }
519
520 return IRQ_HANDLED;
521}
522
523/*
524 * sets the pc of SDMA script according to the peripheral type
525 */
526static void sdma_get_pc(struct sdma_channel *sdmac,
527 enum sdma_peripheral_type peripheral_type)
528{
529 struct sdma_engine *sdma = sdmac->sdma;
530 int per_2_emi = 0, emi_2_per = 0;
531 /*
532 * These are needed once we start to support transfers between
533 * two peripherals or memory-to-memory transfers
534 */
535 int per_2_per = 0, emi_2_emi = 0;
536
537 sdmac->pc_from_device = 0;
538 sdmac->pc_to_device = 0;
539
540 switch (peripheral_type) {
541 case IMX_DMATYPE_MEMORY:
542 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
543 break;
544 case IMX_DMATYPE_DSP:
545 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
546 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
547 break;
548 case IMX_DMATYPE_FIRI:
549 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
550 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
551 break;
552 case IMX_DMATYPE_UART:
553 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
554 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
555 break;
556 case IMX_DMATYPE_UART_SP:
557 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
558 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
559 break;
560 case IMX_DMATYPE_ATA:
561 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
562 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
563 break;
564 case IMX_DMATYPE_CSPI:
565 case IMX_DMATYPE_EXT:
566 case IMX_DMATYPE_SSI:
567 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
568 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
569 break;
570 case IMX_DMATYPE_SSI_SP:
571 case IMX_DMATYPE_MMC:
572 case IMX_DMATYPE_SDHC:
573 case IMX_DMATYPE_CSPI_SP:
574 case IMX_DMATYPE_ESAI:
575 case IMX_DMATYPE_MSHC_SP:
576 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
577 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
578 break;
579 case IMX_DMATYPE_ASRC:
580 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
581 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
582 per_2_per = sdma->script_addrs->per_2_per_addr;
583 break;
584 case IMX_DMATYPE_MSHC:
585 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
586 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
587 break;
588 case IMX_DMATYPE_CCM:
589 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
590 break;
591 case IMX_DMATYPE_SPDIF:
592 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
593 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
594 break;
595 case IMX_DMATYPE_IPU_MEMORY:
596 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
597 break;
598 default:
599 break;
600 }
601
602 sdmac->pc_from_device = per_2_emi;
603 sdmac->pc_to_device = emi_2_per;
604}
605
606static int sdma_load_context(struct sdma_channel *sdmac)
607{
608 struct sdma_engine *sdma = sdmac->sdma;
609 int channel = sdmac->channel;
610 int load_address;
611 struct sdma_context_data *context = sdma->context;
612 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
613 int ret;
614
615 if (sdmac->direction == DMA_FROM_DEVICE) {
616 load_address = sdmac->pc_from_device;
617 } else {
618 load_address = sdmac->pc_to_device;
619 }
620
621 if (load_address < 0)
622 return load_address;
623
624 dev_dbg(sdma->dev, "load_address = %d\n", load_address);
625 dev_dbg(sdma->dev, "wml = 0x%08x\n", sdmac->watermark_level);
626 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
627 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
628 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", sdmac->event_mask0);
629 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", sdmac->event_mask1);
630
631 memset(context, 0, sizeof(*context));
632 context->channel_state.pc = load_address;
633
634 /* Send by context the event mask,base address for peripheral
635 * and watermark level
636 */
637 context->gReg[0] = sdmac->event_mask1;
638 context->gReg[1] = sdmac->event_mask0;
639 context->gReg[2] = sdmac->per_addr;
640 context->gReg[6] = sdmac->shp_addr;
641 context->gReg[7] = sdmac->watermark_level;
642
643 bd0->mode.command = C0_SETDM;
644 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
645 bd0->mode.count = sizeof(*context) / 4;
646 bd0->buffer_addr = sdma->context_phys;
647 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
648
649 ret = sdma_run_channel(&sdma->channel[0]);
650
651 return ret;
652}
653
654static void sdma_disable_channel(struct sdma_channel *sdmac)
655{
656 struct sdma_engine *sdma = sdmac->sdma;
657 int channel = sdmac->channel;
658
659 __raw_writel(1 << channel, sdma->regs + SDMA_H_STATSTOP);
660 sdmac->status = DMA_ERROR;
661}
662
663static int sdma_config_channel(struct sdma_channel *sdmac)
664{
665 int ret;
666
667 sdma_disable_channel(sdmac);
668
669 sdmac->event_mask0 = 0;
670 sdmac->event_mask1 = 0;
671 sdmac->shp_addr = 0;
672 sdmac->per_addr = 0;
673
674 if (sdmac->event_id0) {
675 if (sdmac->event_id0 > 32)
676 return -EINVAL;
677 sdma_event_enable(sdmac, sdmac->event_id0);
678 }
679
680 switch (sdmac->peripheral_type) {
681 case IMX_DMATYPE_DSP:
682 sdma_config_ownership(sdmac, false, true, true);
683 break;
684 case IMX_DMATYPE_MEMORY:
685 sdma_config_ownership(sdmac, false, true, false);
686 break;
687 default:
688 sdma_config_ownership(sdmac, true, true, false);
689 break;
690 }
691
692 sdma_get_pc(sdmac, sdmac->peripheral_type);
693
694 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
695 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
696 /* Handle multiple event channels differently */
697 if (sdmac->event_id1) {
698 sdmac->event_mask1 = 1 << (sdmac->event_id1 % 32);
699 if (sdmac->event_id1 > 31)
700 sdmac->watermark_level |= 1 << 31;
701 sdmac->event_mask0 = 1 << (sdmac->event_id0 % 32);
702 if (sdmac->event_id0 > 31)
703 sdmac->watermark_level |= 1 << 30;
704 } else {
705 sdmac->event_mask0 = 1 << sdmac->event_id0;
706 sdmac->event_mask1 = 1 << (sdmac->event_id0 - 32);
707 }
708 /* Watermark Level */
709 sdmac->watermark_level |= sdmac->watermark_level;
710 /* Address */
711 sdmac->shp_addr = sdmac->per_address;
712 } else {
713 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
714 }
715
716 ret = sdma_load_context(sdmac);
717
718 return ret;
719}
720
721static int sdma_set_channel_priority(struct sdma_channel *sdmac,
722 unsigned int priority)
723{
724 struct sdma_engine *sdma = sdmac->sdma;
725 int channel = sdmac->channel;
726
727 if (priority < MXC_SDMA_MIN_PRIORITY
728 || priority > MXC_SDMA_MAX_PRIORITY) {
729 return -EINVAL;
730 }
731
732 __raw_writel(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
733
734 return 0;
735}
736
737static int sdma_request_channel(struct sdma_channel *sdmac)
738{
739 struct sdma_engine *sdma = sdmac->sdma;
740 int channel = sdmac->channel;
741 int ret = -EBUSY;
742
743 sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
744 if (!sdmac->bd) {
745 ret = -ENOMEM;
746 goto out;
747 }
748
749 memset(sdmac->bd, 0, PAGE_SIZE);
750
751 sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
752 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
753
754 clk_enable(sdma->clk);
755
756 sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
757
758 init_completion(&sdmac->done);
759
760 sdmac->buf_tail = 0;
761
762 return 0;
763out:
764
765 return ret;
766}
767
768static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
769{
770 __raw_writel(1 << channel, sdma->regs + SDMA_H_START);
771}
772
773static dma_cookie_t sdma_assign_cookie(struct sdma_channel *sdma)
774{
775 dma_cookie_t cookie = sdma->chan.cookie;
776
777 if (++cookie < 0)
778 cookie = 1;
779
780 sdma->chan.cookie = cookie;
781 sdma->desc.cookie = cookie;
782
783 return cookie;
784}
785
786static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
787{
788 return container_of(chan, struct sdma_channel, chan);
789}
790
791static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
792{
793 struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
794 struct sdma_engine *sdma = sdmac->sdma;
795 dma_cookie_t cookie;
796
797 spin_lock_irq(&sdmac->lock);
798
799 cookie = sdma_assign_cookie(sdmac);
800
801 sdma_enable_channel(sdma, tx->chan->chan_id);
802
803 spin_unlock_irq(&sdmac->lock);
804
805 return cookie;
806}
807
808static int sdma_alloc_chan_resources(struct dma_chan *chan)
809{
810 struct sdma_channel *sdmac = to_sdma_chan(chan);
811 struct imx_dma_data *data = chan->private;
812 int prio, ret;
813
814 /* No need to execute this for internal channel 0 */
815 if (chan->chan_id == 0)
816 return 0;
817
818 if (!data)
819 return -EINVAL;
820
821 switch (data->priority) {
822 case DMA_PRIO_HIGH:
823 prio = 3;
824 break;
825 case DMA_PRIO_MEDIUM:
826 prio = 2;
827 break;
828 case DMA_PRIO_LOW:
829 default:
830 prio = 1;
831 break;
832 }
833
834 sdmac->peripheral_type = data->peripheral_type;
835 sdmac->event_id0 = data->dma_request;
836 ret = sdma_set_channel_priority(sdmac, prio);
837 if (ret)
838 return ret;
839
840 ret = sdma_request_channel(sdmac);
841 if (ret)
842 return ret;
843
844 dma_async_tx_descriptor_init(&sdmac->desc, chan);
845 sdmac->desc.tx_submit = sdma_tx_submit;
846 /* txd.flags will be overwritten in prep funcs */
847 sdmac->desc.flags = DMA_CTRL_ACK;
848
849 return 0;
850}
851
852static void sdma_free_chan_resources(struct dma_chan *chan)
853{
854 struct sdma_channel *sdmac = to_sdma_chan(chan);
855 struct sdma_engine *sdma = sdmac->sdma;
856
857 sdma_disable_channel(sdmac);
858
859 if (sdmac->event_id0)
860 sdma_event_disable(sdmac, sdmac->event_id0);
861 if (sdmac->event_id1)
862 sdma_event_disable(sdmac, sdmac->event_id1);
863
864 sdmac->event_id0 = 0;
865 sdmac->event_id1 = 0;
866
867 sdma_set_channel_priority(sdmac, 0);
868
869 dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
870
871 clk_disable(sdma->clk);
872}
873
874static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
875 struct dma_chan *chan, struct scatterlist *sgl,
876 unsigned int sg_len, enum dma_data_direction direction,
877 unsigned long flags)
878{
879 struct sdma_channel *sdmac = to_sdma_chan(chan);
880 struct sdma_engine *sdma = sdmac->sdma;
881 int ret, i, count;
882 int channel = chan->chan_id;
883 struct scatterlist *sg;
884
885 if (sdmac->status == DMA_IN_PROGRESS)
886 return NULL;
887 sdmac->status = DMA_IN_PROGRESS;
888
889 sdmac->flags = 0;
890
891 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
892 sg_len, channel);
893
894 sdmac->direction = direction;
895 ret = sdma_load_context(sdmac);
896 if (ret)
897 goto err_out;
898
899 if (sg_len > NUM_BD) {
900 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
901 channel, sg_len, NUM_BD);
902 ret = -EINVAL;
903 goto err_out;
904 }
905
906 for_each_sg(sgl, sg, sg_len, i) {
907 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
908 int param;
909
Anatolij Gustschind2f5c272010-11-22 18:35:18 +0100910 bd->buffer_addr = sg->dma_address;
Sascha Hauer1ec1e822010-09-30 13:56:34 +0000911
912 count = sg->length;
913
914 if (count > 0xffff) {
915 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
916 channel, count, 0xffff);
917 ret = -EINVAL;
918 goto err_out;
919 }
920
921 bd->mode.count = count;
922
923 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
924 ret = -EINVAL;
925 goto err_out;
926 }
927 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
928 bd->mode.command = 0;
929 else
930 bd->mode.command = sdmac->word_size;
931
932 param = BD_DONE | BD_EXTD | BD_CONT;
933
934 if (sdmac->flags & IMX_DMA_SG_LOOP) {
935 param |= BD_INTR;
936 if (i + 1 == sg_len)
937 param |= BD_WRAP;
938 }
939
940 if (i + 1 == sg_len)
941 param |= BD_INTR;
942
943 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
944 i, count, sg->dma_address,
945 param & BD_WRAP ? "wrap" : "",
946 param & BD_INTR ? " intr" : "");
947
948 bd->mode.status = param;
949 }
950
951 sdmac->num_bd = sg_len;
952 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
953
954 return &sdmac->desc;
955err_out:
956 return NULL;
957}
958
959static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
960 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
961 size_t period_len, enum dma_data_direction direction)
962{
963 struct sdma_channel *sdmac = to_sdma_chan(chan);
964 struct sdma_engine *sdma = sdmac->sdma;
965 int num_periods = buf_len / period_len;
966 int channel = chan->chan_id;
967 int ret, i = 0, buf = 0;
968
969 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
970
971 if (sdmac->status == DMA_IN_PROGRESS)
972 return NULL;
973
974 sdmac->status = DMA_IN_PROGRESS;
975
976 sdmac->flags |= IMX_DMA_SG_LOOP;
977 sdmac->direction = direction;
978 ret = sdma_load_context(sdmac);
979 if (ret)
980 goto err_out;
981
982 if (num_periods > NUM_BD) {
983 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
984 channel, num_periods, NUM_BD);
985 goto err_out;
986 }
987
988 if (period_len > 0xffff) {
989 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
990 channel, period_len, 0xffff);
991 goto err_out;
992 }
993
994 while (buf < buf_len) {
995 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
996 int param;
997
998 bd->buffer_addr = dma_addr;
999
1000 bd->mode.count = period_len;
1001
1002 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1003 goto err_out;
1004 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1005 bd->mode.command = 0;
1006 else
1007 bd->mode.command = sdmac->word_size;
1008
1009 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1010 if (i + 1 == num_periods)
1011 param |= BD_WRAP;
1012
1013 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
1014 i, period_len, dma_addr,
1015 param & BD_WRAP ? "wrap" : "",
1016 param & BD_INTR ? " intr" : "");
1017
1018 bd->mode.status = param;
1019
1020 dma_addr += period_len;
1021 buf += period_len;
1022
1023 i++;
1024 }
1025
1026 sdmac->num_bd = num_periods;
1027 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1028
1029 return &sdmac->desc;
1030err_out:
1031 sdmac->status = DMA_ERROR;
1032 return NULL;
1033}
1034
1035static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1036 unsigned long arg)
1037{
1038 struct sdma_channel *sdmac = to_sdma_chan(chan);
1039 struct dma_slave_config *dmaengine_cfg = (void *)arg;
1040
1041 switch (cmd) {
1042 case DMA_TERMINATE_ALL:
1043 sdma_disable_channel(sdmac);
1044 return 0;
1045 case DMA_SLAVE_CONFIG:
1046 if (dmaengine_cfg->direction == DMA_FROM_DEVICE) {
1047 sdmac->per_address = dmaengine_cfg->src_addr;
1048 sdmac->watermark_level = dmaengine_cfg->src_maxburst;
1049 sdmac->word_size = dmaengine_cfg->src_addr_width;
1050 } else {
1051 sdmac->per_address = dmaengine_cfg->dst_addr;
1052 sdmac->watermark_level = dmaengine_cfg->dst_maxburst;
1053 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1054 }
1055 return sdma_config_channel(sdmac);
1056 default:
1057 return -ENOSYS;
1058 }
1059
1060 return -EINVAL;
1061}
1062
1063static enum dma_status sdma_tx_status(struct dma_chan *chan,
1064 dma_cookie_t cookie,
1065 struct dma_tx_state *txstate)
1066{
1067 struct sdma_channel *sdmac = to_sdma_chan(chan);
1068 dma_cookie_t last_used;
1069 enum dma_status ret;
1070
1071 last_used = chan->cookie;
1072
1073 ret = dma_async_is_complete(cookie, sdmac->last_completed, last_used);
1074 dma_set_tx_state(txstate, sdmac->last_completed, last_used, 0);
1075
1076 return ret;
1077}
1078
1079static void sdma_issue_pending(struct dma_chan *chan)
1080{
1081 /*
1082 * Nothing to do. We only have a single descriptor
1083 */
1084}
1085
Sascha Hauer5b28aa32010-10-06 15:41:15 +02001086#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1087
1088static void sdma_add_scripts(struct sdma_engine *sdma,
1089 const struct sdma_script_start_addrs *addr)
1090{
1091 s32 *addr_arr = (u32 *)addr;
1092 s32 *saddr_arr = (u32 *)sdma->script_addrs;
1093 int i;
1094
1095 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1096 if (addr_arr[i] > 0)
1097 saddr_arr[i] = addr_arr[i];
1098}
1099
1100static int __init sdma_get_firmware(struct sdma_engine *sdma,
1101 const char *cpu_name, int to_version)
1102{
1103 const struct firmware *fw;
1104 char *fwname;
1105 const struct sdma_firmware_header *header;
1106 int ret;
1107 const struct sdma_script_start_addrs *addr;
1108 unsigned short *ram_code;
1109
1110 fwname = kasprintf(GFP_KERNEL, "sdma-%s-to%d.bin", cpu_name, to_version);
1111 if (!fwname)
1112 return -ENOMEM;
1113
1114 ret = request_firmware(&fw, fwname, sdma->dev);
1115 if (ret) {
1116 kfree(fwname);
1117 return ret;
1118 }
1119 kfree(fwname);
1120
1121 if (fw->size < sizeof(*header))
1122 goto err_firmware;
1123
1124 header = (struct sdma_firmware_header *)fw->data;
1125
1126 if (header->magic != SDMA_FIRMWARE_MAGIC)
1127 goto err_firmware;
1128 if (header->ram_code_start + header->ram_code_size > fw->size)
1129 goto err_firmware;
1130
1131 addr = (void *)header + header->script_addrs_start;
1132 ram_code = (void *)header + header->ram_code_start;
1133
1134 clk_enable(sdma->clk);
1135 /* download the RAM image for SDMA */
1136 sdma_load_script(sdma, ram_code,
1137 header->ram_code_size,
1138 sdma->script_addrs->ram_code_start_addr);
1139 clk_disable(sdma->clk);
1140
1141 sdma_add_scripts(sdma, addr);
1142
1143 dev_info(sdma->dev, "loaded firmware %d.%d\n",
1144 header->version_major,
1145 header->version_minor);
1146
1147err_firmware:
1148 release_firmware(fw);
1149
1150 return ret;
1151}
1152
1153static int __init sdma_init(struct sdma_engine *sdma)
Sascha Hauer1ec1e822010-09-30 13:56:34 +00001154{
1155 int i, ret;
1156 dma_addr_t ccb_phys;
1157
1158 switch (sdma->version) {
1159 case 1:
1160 sdma->num_events = 32;
1161 break;
1162 case 2:
1163 sdma->num_events = 48;
1164 break;
1165 default:
1166 dev_err(sdma->dev, "Unknown version %d. aborting\n", sdma->version);
1167 return -ENODEV;
1168 }
1169
1170 clk_enable(sdma->clk);
1171
1172 /* Be sure SDMA has not started yet */
1173 __raw_writel(0, sdma->regs + SDMA_H_C0PTR);
1174
1175 sdma->channel_control = dma_alloc_coherent(NULL,
1176 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1177 sizeof(struct sdma_context_data),
1178 &ccb_phys, GFP_KERNEL);
1179
1180 if (!sdma->channel_control) {
1181 ret = -ENOMEM;
1182 goto err_dma_alloc;
1183 }
1184
1185 sdma->context = (void *)sdma->channel_control +
1186 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1187 sdma->context_phys = ccb_phys +
1188 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1189
1190 /* Zero-out the CCB structures array just allocated */
1191 memset(sdma->channel_control, 0,
1192 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1193
1194 /* disable all channels */
1195 for (i = 0; i < sdma->num_events; i++)
1196 __raw_writel(0, sdma->regs + chnenbl_ofs(sdma, i));
1197
1198 /* All channels have priority 0 */
1199 for (i = 0; i < MAX_DMA_CHANNELS; i++)
1200 __raw_writel(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1201
1202 ret = sdma_request_channel(&sdma->channel[0]);
1203 if (ret)
1204 goto err_dma_alloc;
1205
1206 sdma_config_ownership(&sdma->channel[0], false, true, false);
1207
1208 /* Set Command Channel (Channel Zero) */
1209 __raw_writel(0x4050, sdma->regs + SDMA_CHN0ADDR);
1210
1211 /* Set bits of CONFIG register but with static context switching */
1212 /* FIXME: Check whether to set ACR bit depending on clock ratios */
1213 __raw_writel(0, sdma->regs + SDMA_H_CONFIG);
1214
1215 __raw_writel(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1216
Sascha Hauer1ec1e822010-09-30 13:56:34 +00001217 /* Set bits of CONFIG register with given context switching mode */
1218 __raw_writel(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
1219
1220 /* Initializes channel's priorities */
1221 sdma_set_channel_priority(&sdma->channel[0], 7);
1222
1223 clk_disable(sdma->clk);
1224
1225 return 0;
1226
1227err_dma_alloc:
1228 clk_disable(sdma->clk);
1229 dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1230 return ret;
1231}
1232
1233static int __init sdma_probe(struct platform_device *pdev)
1234{
1235 int ret;
Sascha Hauer1ec1e822010-09-30 13:56:34 +00001236 int irq;
Sascha Hauer1ec1e822010-09-30 13:56:34 +00001237 struct resource *iores;
1238 struct sdma_platform_data *pdata = pdev->dev.platform_data;
Sascha Hauer1ec1e822010-09-30 13:56:34 +00001239 int i;
1240 dma_cap_mask_t mask;
1241 struct sdma_engine *sdma;
1242
1243 sdma = kzalloc(sizeof(*sdma), GFP_KERNEL);
1244 if (!sdma)
1245 return -ENOMEM;
1246
1247 sdma->dev = &pdev->dev;
1248
1249 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1250 irq = platform_get_irq(pdev, 0);
1251 if (!iores || irq < 0 || !pdata) {
1252 ret = -EINVAL;
1253 goto err_irq;
1254 }
1255
1256 if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) {
1257 ret = -EBUSY;
1258 goto err_request_region;
1259 }
1260
1261 sdma->clk = clk_get(&pdev->dev, NULL);
1262 if (IS_ERR(sdma->clk)) {
1263 ret = PTR_ERR(sdma->clk);
1264 goto err_clk;
1265 }
1266
1267 sdma->regs = ioremap(iores->start, resource_size(iores));
1268 if (!sdma->regs) {
1269 ret = -ENOMEM;
1270 goto err_ioremap;
1271 }
1272
1273 ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma);
1274 if (ret)
1275 goto err_request_irq;
1276
Sascha Hauer5b28aa32010-10-06 15:41:15 +02001277 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
Sascha Hauer1ec1e822010-09-30 13:56:34 +00001278 if (!sdma->script_addrs)
Sascha Hauer5b28aa32010-10-06 15:41:15 +02001279 goto err_alloc;
Sascha Hauer1ec1e822010-09-30 13:56:34 +00001280
1281 sdma->version = pdata->sdma_version;
1282
1283 INIT_LIST_HEAD(&sdma->dma_device.channels);
1284 /* Initialize channel parameters */
1285 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1286 struct sdma_channel *sdmac = &sdma->channel[i];
1287
1288 sdmac->sdma = sdma;
1289 spin_lock_init(&sdmac->lock);
1290
1291 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1292 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1293
1294 sdmac->chan.device = &sdma->dma_device;
1295 sdmac->chan.chan_id = i;
1296 sdmac->channel = i;
1297
1298 /* Add the channel to the DMAC list */
1299 list_add_tail(&sdmac->chan.device_node, &sdma->dma_device.channels);
1300 }
1301
Sascha Hauer5b28aa32010-10-06 15:41:15 +02001302 ret = sdma_init(sdma);
Sascha Hauer1ec1e822010-09-30 13:56:34 +00001303 if (ret)
1304 goto err_init;
1305
Sascha Hauer5b28aa32010-10-06 15:41:15 +02001306 if (pdata->script_addrs)
1307 sdma_add_scripts(sdma, pdata->script_addrs);
1308
1309 sdma_get_firmware(sdma, pdata->cpu_name, pdata->to_version);
1310
Sascha Hauer1ec1e822010-09-30 13:56:34 +00001311 sdma->dma_device.dev = &pdev->dev;
1312
1313 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1314 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1315 sdma->dma_device.device_tx_status = sdma_tx_status;
1316 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1317 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1318 sdma->dma_device.device_control = sdma_control;
1319 sdma->dma_device.device_issue_pending = sdma_issue_pending;
1320
1321 ret = dma_async_device_register(&sdma->dma_device);
1322 if (ret) {
1323 dev_err(&pdev->dev, "unable to register\n");
1324 goto err_init;
1325 }
1326
Sascha Hauer1ec1e822010-09-30 13:56:34 +00001327 /* request channel 0. This is an internal control channel
1328 * to the SDMA engine and not available to clients.
1329 */
1330 dma_cap_zero(mask);
1331 dma_cap_set(DMA_SLAVE, mask);
1332 dma_request_channel(mask, NULL, NULL);
1333
Sascha Hauer5b28aa32010-10-06 15:41:15 +02001334 dev_info(sdma->dev, "initialized\n");
Sascha Hauer1ec1e822010-09-30 13:56:34 +00001335
1336 return 0;
1337
1338err_init:
1339 kfree(sdma->script_addrs);
Sascha Hauer5b28aa32010-10-06 15:41:15 +02001340err_alloc:
Sascha Hauer1ec1e822010-09-30 13:56:34 +00001341 free_irq(irq, sdma);
1342err_request_irq:
1343 iounmap(sdma->regs);
1344err_ioremap:
1345 clk_put(sdma->clk);
1346err_clk:
1347 release_mem_region(iores->start, resource_size(iores));
1348err_request_region:
1349err_irq:
1350 kfree(sdma);
1351 return 0;
1352}
1353
1354static int __exit sdma_remove(struct platform_device *pdev)
1355{
1356 return -EBUSY;
1357}
1358
1359static struct platform_driver sdma_driver = {
1360 .driver = {
1361 .name = "imx-sdma",
1362 },
1363 .remove = __exit_p(sdma_remove),
1364};
1365
1366static int __init sdma_module_init(void)
1367{
1368 return platform_driver_probe(&sdma_driver, sdma_probe);
1369}
Sascha Hauerc989a7f2010-12-06 11:09:57 +01001370module_init(sdma_module_init);
Sascha Hauer1ec1e822010-09-30 13:56:34 +00001371
1372MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1373MODULE_DESCRIPTION("i.MX SDMA driver");
1374MODULE_LICENSE("GPL");