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Jan Engelhardt96de0e22007-10-19 23:21:04 +02001PXA2xx SPI on SSP driver HOWTO
Stephen Streete0c99052006-03-07 23:53:24 -08002===================================================
3This a mini howto on the pxa2xx_spi driver. The driver turns a PXA2xx
4synchronous serial port into a SPI master controller
5(see Documentation/spi/spi_summary). The driver has the following features
6
7- Support for any PXA2xx SSP
8- SSP PIO and SSP DMA data transfers.
9- External and Internal (SSPFRM) chip selects.
10- Per slave device (chip) configuration.
11- Full suspend, freeze, resume support.
12
13The driver is built around a "spi_message" fifo serviced by workqueue and a
14tasklet. The workqueue, "pump_messages", drives message fifo and the tasklet
15(pump_transfer) is responsible for queuing SPI transactions and setting up and
16launching the dma/interrupt driven transfers.
17
18Declaring PXA2xx Master Controllers
19-----------------------------------
20Typically a SPI master is defined in the arch/.../mach-*/board-*.c as a
21"platform device". The master configuration is passed to the driver via a table
Sebastian Andrzej Siewior8348c252010-11-22 17:12:15 -080022found in include/linux/spi/pxa2xx_spi.h:
Stephen Streete0c99052006-03-07 23:53:24 -080023
24struct pxa2xx_spi_master {
Stephen Streete0c99052006-03-07 23:53:24 -080025 u32 clock_enable;
26 u16 num_chipselect;
27 u8 enable_dma;
28};
29
Stephen Streete0c99052006-03-07 23:53:24 -080030The "pxa2xx_spi_master.clock_enable" field is used to enable/disable the
31corresponding SSP peripheral block in the "Clock Enable Register (CKEN"). See
32the "PXA2xx Developer Manual" section "Clocks and Power Management".
33
34The "pxa2xx_spi_master.num_chipselect" field is used to determine the number of
35slave device (chips) attached to this SPI master.
36
37The "pxa2xx_spi_master.enable_dma" field informs the driver that SSP DMA should
38be used. This caused the driver to acquire two DMA channels: rx_channel and
39tx_channel. The rx_channel has a higher DMA service priority the tx_channel.
40See the "PXA2xx Developer Manual" section "DMA Controller".
41
42NSSP MASTER SAMPLE
43------------------
44Below is a sample configuration using the PXA255 NSSP.
45
46static struct resource pxa_spi_nssp_resources[] = {
47 [0] = {
48 .start = __PREG(SSCR0_P(2)), /* Start address of NSSP */
49 .end = __PREG(SSCR0_P(2)) + 0x2c, /* Range of registers */
50 .flags = IORESOURCE_MEM,
51 },
52 [1] = {
53 .start = IRQ_NSSP, /* NSSP IRQ */
54 .end = IRQ_NSSP,
55 .flags = IORESOURCE_IRQ,
56 },
57};
58
59static struct pxa2xx_spi_master pxa_nssp_master_info = {
Eric Miao7053acb2007-04-05 04:07:20 +010060 .clock_enable = CKEN_NSSP, /* NSSP Peripheral clock */
Stephen Streete0c99052006-03-07 23:53:24 -080061 .num_chipselect = 1, /* Matches the number of chips attached to NSSP */
62 .enable_dma = 1, /* Enables NSSP DMA */
63};
64
65static struct platform_device pxa_spi_nssp = {
66 .name = "pxa2xx-spi", /* MUST BE THIS VALUE, so device match driver */
67 .id = 2, /* Bus number, MUST MATCH SSP number 1..n */
68 .resource = pxa_spi_nssp_resources,
69 .num_resources = ARRAY_SIZE(pxa_spi_nssp_resources),
70 .dev = {
71 .platform_data = &pxa_nssp_master_info, /* Passed to driver */
72 },
73};
74
75static struct platform_device *devices[] __initdata = {
76 &pxa_spi_nssp,
77};
78
79static void __init board_init(void)
80{
81 (void)platform_add_device(devices, ARRAY_SIZE(devices));
82}
83
84Declaring Slave Devices
85-----------------------
86Typically each SPI slave (chip) is defined in the arch/.../mach-*/board-*.c
87using the "spi_board_info" structure found in "linux/spi/spi.h". See
88"Documentation/spi/spi_summary" for additional information.
89
90Each slave device attached to the PXA must provide slave specific configuration
91information via the structure "pxa2xx_spi_chip" found in
Sebastian Andrzej Siewior8348c252010-11-22 17:12:15 -080092"include/linux/spi/pxa2xx_spi.h". The pxa2xx_spi master controller driver
Stephen Streete0c99052006-03-07 23:53:24 -080093will uses the configuration whenever the driver communicates with the slave
Vernon Sauderf1f640a2008-10-15 22:02:43 -070094device. All fields are optional.
Stephen Streete0c99052006-03-07 23:53:24 -080095
96struct pxa2xx_spi_chip {
97 u8 tx_threshold;
98 u8 rx_threshold;
99 u8 dma_burst_size;
Stephen Street8d94cc52006-12-10 02:18:54 -0800100 u32 timeout;
Stephen Streete0c99052006-03-07 23:53:24 -0800101 u8 enable_loopback;
102 void (*cs_control)(u32 command);
103};
104
105The "pxa2xx_spi_chip.tx_threshold" and "pxa2xx_spi_chip.rx_threshold" fields are
106used to configure the SSP hardware fifo. These fields are critical to the
107performance of pxa2xx_spi driver and misconfiguration will result in rx
108fifo overruns (especially in PIO mode transfers). Good default values are
109
Vernon Sauderf1f640a2008-10-15 22:02:43 -0700110 .tx_threshold = 8,
111 .rx_threshold = 8,
112
113The range is 1 to 16 where zero indicates "use default".
Stephen Streete0c99052006-03-07 23:53:24 -0800114
115The "pxa2xx_spi_chip.dma_burst_size" field is used to configure PXA2xx DMA
116engine and is related the "spi_device.bits_per_word" field. Read and understand
117the PXA2xx "Developer Manual" sections on the DMA controller and SSP Controllers
118to determine the correct value. An SSP configured for byte-wide transfers would
Vernon Sauderf1f640a2008-10-15 22:02:43 -0700119use a value of 8. The driver will determine a reasonable default if
120dma_burst_size == 0.
Stephen Streete0c99052006-03-07 23:53:24 -0800121
Stephen Street8d94cc52006-12-10 02:18:54 -0800122The "pxa2xx_spi_chip.timeout" fields is used to efficiently handle
Stephen Streete0c99052006-03-07 23:53:24 -0800123trailing bytes in the SSP receiver fifo. The correct value for this field is
124dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the specific
Paolo Ornati670e9f32006-10-03 22:57:56 +0200125slave device. Please note that the PXA2xx SSP 1 does not support trailing byte
Stephen Streete0c99052006-03-07 23:53:24 -0800126timeouts and must busy-wait any trailing bytes.
127
128The "pxa2xx_spi_chip.enable_loopback" field is used to place the SSP porting
129into internal loopback mode. In this mode the SSP controller internally
Paolo Ornati670e9f32006-10-03 22:57:56 +0200130connects the SSPTX pin to the SSPRX pin. This is useful for initial setup
Stephen Streete0c99052006-03-07 23:53:24 -0800131testing.
132
133The "pxa2xx_spi_chip.cs_control" field is used to point to a board specific
134function for asserting/deasserting a slave device chip select. If the field is
135NULL, the pxa2xx_spi master controller driver assumes that the SSP port is
136configured to use SSPFRM instead.
137
Vernon Sauderf1f640a2008-10-15 22:02:43 -0700138NOTE: the SPI driver cannot control the chip select if SSPFRM is used, so the
139chipselect is dropped after each spi_transfer. Most devices need chip select
140asserted around the complete message. Use SSPFRM as a GPIO (through cs_control)
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300141to accommodate these chips.
Vernon Sauderf1f640a2008-10-15 22:02:43 -0700142
143
144NSSP SLAVE SAMPLE
Stephen Streete0c99052006-03-07 23:53:24 -0800145-----------------
146The pxa2xx_spi_chip structure is passed to the pxa2xx_spi driver in the
147"spi_board_info.controller_data" field. Below is a sample configuration using
148the PXA255 NSSP.
149
150/* Chip Select control for the CS8415A SPI slave device */
151static void cs8415a_cs_control(u32 command)
152{
153 if (command & PXA2XX_CS_ASSERT)
154 GPCR(2) = GPIO_bit(2);
155 else
156 GPSR(2) = GPIO_bit(2);
157}
158
159/* Chip Select control for the CS8405A SPI slave device */
160static void cs8405a_cs_control(u32 command)
161{
162 if (command & PXA2XX_CS_ASSERT)
163 GPCR(3) = GPIO_bit(3);
164 else
165 GPSR(3) = GPIO_bit(3);
166}
167
168static struct pxa2xx_spi_chip cs8415a_chip_info = {
Stephen Street8d94cc52006-12-10 02:18:54 -0800169 .tx_threshold = 8, /* SSP hardward FIFO threshold */
170 .rx_threshold = 8, /* SSP hardward FIFO threshold */
Stephen Streete0c99052006-03-07 23:53:24 -0800171 .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
Stephen Street8d94cc52006-12-10 02:18:54 -0800172 .timeout = 235, /* See Intel documentation */
Stephen Streete0c99052006-03-07 23:53:24 -0800173 .cs_control = cs8415a_cs_control, /* Use external chip select */
174};
175
176static struct pxa2xx_spi_chip cs8405a_chip_info = {
Stephen Street8d94cc52006-12-10 02:18:54 -0800177 .tx_threshold = 8, /* SSP hardward FIFO threshold */
178 .rx_threshold = 8, /* SSP hardward FIFO threshold */
Stephen Streete0c99052006-03-07 23:53:24 -0800179 .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
Stephen Street8d94cc52006-12-10 02:18:54 -0800180 .timeout = 235, /* See Intel documentation */
Stephen Streete0c99052006-03-07 23:53:24 -0800181 .cs_control = cs8405a_cs_control, /* Use external chip select */
182};
183
184static struct spi_board_info streetracer_spi_board_info[] __initdata = {
185 {
186 .modalias = "cs8415a", /* Name of spi_driver for this device */
187 .max_speed_hz = 3686400, /* Run SSP as fast a possbile */
188 .bus_num = 2, /* Framework bus number */
189 .chip_select = 0, /* Framework chip select */
190 .platform_data = NULL; /* No spi_driver specific config */
191 .controller_data = &cs8415a_chip_info, /* Master chip config */
192 .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */
193 },
194 {
195 .modalias = "cs8405a", /* Name of spi_driver for this device */
196 .max_speed_hz = 3686400, /* Run SSP as fast a possbile */
197 .bus_num = 2, /* Framework bus number */
198 .chip_select = 1, /* Framework chip select */
199 .controller_data = &cs8405a_chip_info, /* Master chip config */
200 .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */
201 },
202};
203
204static void __init streetracer_init(void)
205{
206 spi_register_board_info(streetracer_spi_board_info,
207 ARRAY_SIZE(streetracer_spi_board_info));
208}
209
210
211DMA and PIO I/O Support
212-----------------------
Vernon Sauderf1f640a2008-10-15 22:02:43 -0700213The pxa2xx_spi driver supports both DMA and interrupt driven PIO message
214transfers. The driver defaults to PIO mode and DMA transfers must be enabled
215by setting the "enable_dma" flag in the "pxa2xx_spi_master" structure. The DMA
216mode supports both coherent and stream based DMA mappings.
Stephen Streete0c99052006-03-07 23:53:24 -0800217
218The following logic is used to determine the type of I/O to be used on
219a per "spi_transfer" basis:
220
Vernon Sauderf1f640a2008-10-15 22:02:43 -0700221if !enable_dma then
Stephen Streete0c99052006-03-07 23:53:24 -0800222 always use PIO transfers
223
Vernon Sauderf1f640a2008-10-15 22:02:43 -0700224if spi_message.len > 8191 then
225 print "rate limited" warning
226 use PIO transfers
227
Stephen Streete0c99052006-03-07 23:53:24 -0800228if spi_message.is_dma_mapped and rx_dma_buf != 0 and tx_dma_buf != 0 then
229 use coherent DMA mode
230
231if rx_buf and tx_buf are aligned on 8 byte boundary then
232 use streaming DMA mode
233
234otherwise
235 use PIO transfer
236
237THANKS TO
238---------
239
240David Brownell and others for mentoring the development of this driver.
241