Grant Likely | c103de2 | 2011-06-04 18:38:28 -0600 | [diff] [blame] | 1 | /* |
| 2 | * Moorestown platform Langwell chip GPIO driver |
| 3 | * |
Andy Shevchenko | 611a485 | 2013-05-22 13:20:14 +0300 | [diff] [blame] | 4 | * Copyright (c) 2008, 2009, 2013, Intel Corporation. |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 18 | */ |
| 19 | |
| 20 | /* Supports: |
| 21 | * Moorestown platform Langwell chip. |
Alek Du | 8081c84 | 2010-05-26 14:42:25 -0700 | [diff] [blame] | 22 | * Medfield platform Penwell chip. |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 23 | * Clovertrail platform Cloverview chip. |
| 24 | * Merrifield platform Tangier chip. |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 25 | */ |
| 26 | |
| 27 | #include <linux/module.h> |
| 28 | #include <linux/pci.h> |
Alan Cox | 72b4379 | 2010-10-27 15:33:23 -0700 | [diff] [blame] | 29 | #include <linux/platform_device.h> |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 30 | #include <linux/kernel.h> |
| 31 | #include <linux/delay.h> |
| 32 | #include <linux/stddef.h> |
| 33 | #include <linux/interrupt.h> |
| 34 | #include <linux/init.h> |
| 35 | #include <linux/irq.h> |
| 36 | #include <linux/io.h> |
| 37 | #include <linux/gpio.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 38 | #include <linux/slab.h> |
Kristen Carlson Accardi | 7812803 | 2011-05-10 14:23:45 +0100 | [diff] [blame] | 39 | #include <linux/pm_runtime.h> |
Mika Westerberg | 465f2bd | 2012-05-02 11:15:50 +0300 | [diff] [blame] | 40 | #include <linux/irqdomain.h> |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 41 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 42 | #define INTEL_MID_IRQ_TYPE_EDGE (1 << 0) |
| 43 | #define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1) |
David Cohen | d56d6b3 | 2013-10-04 13:01:40 -0700 | [diff] [blame] | 44 | |
Alek Du | 8081c84 | 2010-05-26 14:42:25 -0700 | [diff] [blame] | 45 | /* |
| 46 | * Langwell chip has 64 pins and thus there are 2 32bit registers to control |
| 47 | * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit |
| 48 | * registers to control them, so we only define the order here instead of a |
| 49 | * structure, to get a bit offset for a pin (use GPDR as an example): |
| 50 | * |
| 51 | * nreg = ngpio / 32; |
| 52 | * reg = offset / 32; |
| 53 | * bit = offset % 32; |
| 54 | * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4; |
| 55 | * |
| 56 | * so the bit of reg_addr is to control pin offset's GPDR feature |
| 57 | */ |
| 58 | |
| 59 | enum GPIO_REG { |
| 60 | GPLR = 0, /* pin level read-only */ |
| 61 | GPDR, /* pin direction */ |
| 62 | GPSR, /* pin set */ |
| 63 | GPCR, /* pin clear */ |
| 64 | GRER, /* rising edge detect */ |
| 65 | GFER, /* falling edge detect */ |
| 66 | GEDR, /* edge detect result */ |
Adrian Hunter | 8c0f7b1 | 2011-10-03 14:36:07 +0300 | [diff] [blame] | 67 | GAFR, /* alt function */ |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 68 | }; |
| 69 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 70 | /* intel_mid gpio driver data */ |
| 71 | struct intel_mid_gpio_ddata { |
David Cohen | d56d6b3 | 2013-10-04 13:01:40 -0700 | [diff] [blame] | 72 | u16 ngpio; /* number of gpio pins */ |
| 73 | u32 gplr_offset; /* offset of first GPLR register from base */ |
| 74 | u32 flis_base; /* base address of FLIS registers */ |
| 75 | u32 flis_len; /* length of FLIS registers */ |
| 76 | u32 (*get_flis_offset)(int gpio); |
| 77 | u32 chip_irq_type; /* chip interrupt type */ |
| 78 | }; |
| 79 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 80 | struct intel_mid_gpio { |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 81 | struct gpio_chip chip; |
Andy Shevchenko | 64c8cbc | 2013-05-22 13:20:11 +0300 | [diff] [blame] | 82 | void __iomem *reg_base; |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 83 | spinlock_t lock; |
Kristen Carlson Accardi | 7812803 | 2011-05-10 14:23:45 +0100 | [diff] [blame] | 84 | struct pci_dev *pdev; |
Mika Westerberg | 465f2bd | 2012-05-02 11:15:50 +0300 | [diff] [blame] | 85 | struct irq_domain *domain; |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 86 | }; |
| 87 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 88 | #define to_intel_gpio_priv(chip) container_of(chip, struct intel_mid_gpio, chip) |
David Cohen | 46ebfbc | 2012-12-20 14:45:51 -0800 | [diff] [blame] | 89 | |
Alek Du | 8081c84 | 2010-05-26 14:42:25 -0700 | [diff] [blame] | 90 | static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset, |
Andy Shevchenko | 611a485 | 2013-05-22 13:20:14 +0300 | [diff] [blame] | 91 | enum GPIO_REG reg_type) |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 92 | { |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 93 | struct intel_mid_gpio *priv = to_intel_gpio_priv(chip); |
Alek Du | 8081c84 | 2010-05-26 14:42:25 -0700 | [diff] [blame] | 94 | unsigned nreg = chip->ngpio / 32; |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 95 | u8 reg = offset / 32; |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 96 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 97 | return priv->reg_base + reg_type * nreg * 4 + reg * 4; |
Alek Du | 8081c84 | 2010-05-26 14:42:25 -0700 | [diff] [blame] | 98 | } |
| 99 | |
Adrian Hunter | 8c0f7b1 | 2011-10-03 14:36:07 +0300 | [diff] [blame] | 100 | static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset, |
| 101 | enum GPIO_REG reg_type) |
| 102 | { |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 103 | struct intel_mid_gpio *priv = to_intel_gpio_priv(chip); |
Adrian Hunter | 8c0f7b1 | 2011-10-03 14:36:07 +0300 | [diff] [blame] | 104 | unsigned nreg = chip->ngpio / 32; |
| 105 | u8 reg = offset / 16; |
Adrian Hunter | 8c0f7b1 | 2011-10-03 14:36:07 +0300 | [diff] [blame] | 106 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 107 | return priv->reg_base + reg_type * nreg * 4 + reg * 4; |
Adrian Hunter | 8c0f7b1 | 2011-10-03 14:36:07 +0300 | [diff] [blame] | 108 | } |
| 109 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 110 | static int intel_gpio_request(struct gpio_chip *chip, unsigned offset) |
Adrian Hunter | 8c0f7b1 | 2011-10-03 14:36:07 +0300 | [diff] [blame] | 111 | { |
| 112 | void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR); |
| 113 | u32 value = readl(gafr); |
| 114 | int shift = (offset % 16) << 1, af = (value >> shift) & 3; |
| 115 | |
| 116 | if (af) { |
| 117 | value &= ~(3 << shift); |
| 118 | writel(value, gafr); |
| 119 | } |
| 120 | return 0; |
| 121 | } |
| 122 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 123 | static int intel_gpio_get(struct gpio_chip *chip, unsigned offset) |
Alek Du | 8081c84 | 2010-05-26 14:42:25 -0700 | [diff] [blame] | 124 | { |
| 125 | void __iomem *gplr = gpio_reg(chip, offset, GPLR); |
| 126 | |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 127 | return readl(gplr) & BIT(offset % 32); |
| 128 | } |
| 129 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 130 | static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 131 | { |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 132 | void __iomem *gpsr, *gpcr; |
| 133 | |
| 134 | if (value) { |
Alek Du | 8081c84 | 2010-05-26 14:42:25 -0700 | [diff] [blame] | 135 | gpsr = gpio_reg(chip, offset, GPSR); |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 136 | writel(BIT(offset % 32), gpsr); |
| 137 | } else { |
Alek Du | 8081c84 | 2010-05-26 14:42:25 -0700 | [diff] [blame] | 138 | gpcr = gpio_reg(chip, offset, GPCR); |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 139 | writel(BIT(offset % 32), gpcr); |
| 140 | } |
| 141 | } |
| 142 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 143 | static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 144 | { |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 145 | struct intel_mid_gpio *priv = to_intel_gpio_priv(chip); |
Alek Du | 8081c84 | 2010-05-26 14:42:25 -0700 | [diff] [blame] | 146 | void __iomem *gpdr = gpio_reg(chip, offset, GPDR); |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 147 | u32 value; |
| 148 | unsigned long flags; |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 149 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 150 | if (priv->pdev) |
| 151 | pm_runtime_get(&priv->pdev->dev); |
Kristen Carlson Accardi | 7812803 | 2011-05-10 14:23:45 +0100 | [diff] [blame] | 152 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 153 | spin_lock_irqsave(&priv->lock, flags); |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 154 | value = readl(gpdr); |
| 155 | value &= ~BIT(offset % 32); |
| 156 | writel(value, gpdr); |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 157 | spin_unlock_irqrestore(&priv->lock, flags); |
Kristen Carlson Accardi | 7812803 | 2011-05-10 14:23:45 +0100 | [diff] [blame] | 158 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 159 | if (priv->pdev) |
| 160 | pm_runtime_put(&priv->pdev->dev); |
Kristen Carlson Accardi | 7812803 | 2011-05-10 14:23:45 +0100 | [diff] [blame] | 161 | |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 162 | return 0; |
| 163 | } |
| 164 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 165 | static int intel_gpio_direction_output(struct gpio_chip *chip, |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 166 | unsigned offset, int value) |
| 167 | { |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 168 | struct intel_mid_gpio *priv = to_intel_gpio_priv(chip); |
Alek Du | 8081c84 | 2010-05-26 14:42:25 -0700 | [diff] [blame] | 169 | void __iomem *gpdr = gpio_reg(chip, offset, GPDR); |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 170 | unsigned long flags; |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 171 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 172 | intel_gpio_set(chip, offset, value); |
Kristen Carlson Accardi | 7812803 | 2011-05-10 14:23:45 +0100 | [diff] [blame] | 173 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 174 | if (priv->pdev) |
| 175 | pm_runtime_get(&priv->pdev->dev); |
Kristen Carlson Accardi | 7812803 | 2011-05-10 14:23:45 +0100 | [diff] [blame] | 176 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 177 | spin_lock_irqsave(&priv->lock, flags); |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 178 | value = readl(gpdr); |
Justin P. Mattock | 6eab04a | 2011-04-08 19:49:08 -0700 | [diff] [blame] | 179 | value |= BIT(offset % 32); |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 180 | writel(value, gpdr); |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 181 | spin_unlock_irqrestore(&priv->lock, flags); |
Kristen Carlson Accardi | 7812803 | 2011-05-10 14:23:45 +0100 | [diff] [blame] | 182 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 183 | if (priv->pdev) |
| 184 | pm_runtime_put(&priv->pdev->dev); |
Kristen Carlson Accardi | 7812803 | 2011-05-10 14:23:45 +0100 | [diff] [blame] | 185 | |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 186 | return 0; |
| 187 | } |
| 188 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 189 | static int intel_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 190 | { |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 191 | struct intel_mid_gpio *priv = to_intel_gpio_priv(chip); |
| 192 | return irq_create_mapping(priv->domain, offset); |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 193 | } |
| 194 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 195 | static int intel_mid_irq_type(struct irq_data *d, unsigned type) |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 196 | { |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 197 | struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d); |
Mika Westerberg | 465f2bd | 2012-05-02 11:15:50 +0300 | [diff] [blame] | 198 | u32 gpio = irqd_to_hwirq(d); |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 199 | unsigned long flags; |
| 200 | u32 value; |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 201 | void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER); |
| 202 | void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER); |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 203 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 204 | if (gpio >= priv->chip.ngpio) |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 205 | return -EINVAL; |
Kristen Carlson Accardi | 7812803 | 2011-05-10 14:23:45 +0100 | [diff] [blame] | 206 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 207 | if (priv->pdev) |
| 208 | pm_runtime_get(&priv->pdev->dev); |
Kristen Carlson Accardi | 7812803 | 2011-05-10 14:23:45 +0100 | [diff] [blame] | 209 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 210 | spin_lock_irqsave(&priv->lock, flags); |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 211 | if (type & IRQ_TYPE_EDGE_RISING) |
| 212 | value = readl(grer) | BIT(gpio % 32); |
| 213 | else |
| 214 | value = readl(grer) & (~BIT(gpio % 32)); |
| 215 | writel(value, grer); |
| 216 | |
| 217 | if (type & IRQ_TYPE_EDGE_FALLING) |
| 218 | value = readl(gfer) | BIT(gpio % 32); |
| 219 | else |
| 220 | value = readl(gfer) & (~BIT(gpio % 32)); |
| 221 | writel(value, gfer); |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 222 | spin_unlock_irqrestore(&priv->lock, flags); |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 223 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 224 | if (priv->pdev) |
| 225 | pm_runtime_put(&priv->pdev->dev); |
Kristen Carlson Accardi | 7812803 | 2011-05-10 14:23:45 +0100 | [diff] [blame] | 226 | |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 227 | return 0; |
Andrew Morton | fd0574c | 2010-10-27 15:33:22 -0700 | [diff] [blame] | 228 | } |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 229 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 230 | static void intel_mid_irq_unmask(struct irq_data *d) |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 231 | { |
Andrew Morton | fd0574c | 2010-10-27 15:33:22 -0700 | [diff] [blame] | 232 | } |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 233 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 234 | static void intel_mid_irq_mask(struct irq_data *d) |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 235 | { |
Andrew Morton | fd0574c | 2010-10-27 15:33:22 -0700 | [diff] [blame] | 236 | } |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 237 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 238 | static struct irq_chip intel_mid_irqchip = { |
| 239 | .name = "INTEL_MID-GPIO", |
| 240 | .irq_mask = intel_mid_irq_mask, |
| 241 | .irq_unmask = intel_mid_irq_unmask, |
| 242 | .irq_set_type = intel_mid_irq_type, |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 243 | }; |
| 244 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 245 | static const struct intel_mid_gpio_ddata gpio_lincroft = { |
David Cohen | d56d6b3 | 2013-10-04 13:01:40 -0700 | [diff] [blame] | 246 | .ngpio = 64, |
| 247 | }; |
| 248 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 249 | static const struct intel_mid_gpio_ddata gpio_penwell_aon = { |
David Cohen | d56d6b3 | 2013-10-04 13:01:40 -0700 | [diff] [blame] | 250 | .ngpio = 96, |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 251 | .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE, |
David Cohen | d56d6b3 | 2013-10-04 13:01:40 -0700 | [diff] [blame] | 252 | }; |
| 253 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 254 | static const struct intel_mid_gpio_ddata gpio_penwell_core = { |
David Cohen | d56d6b3 | 2013-10-04 13:01:40 -0700 | [diff] [blame] | 255 | .ngpio = 96, |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 256 | .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE, |
David Cohen | d56d6b3 | 2013-10-04 13:01:40 -0700 | [diff] [blame] | 257 | }; |
| 258 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 259 | static const struct intel_mid_gpio_ddata gpio_cloverview_aon = { |
David Cohen | d56d6b3 | 2013-10-04 13:01:40 -0700 | [diff] [blame] | 260 | .ngpio = 96, |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 261 | .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL, |
David Cohen | d56d6b3 | 2013-10-04 13:01:40 -0700 | [diff] [blame] | 262 | }; |
| 263 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 264 | static const struct intel_mid_gpio_ddata gpio_cloverview_core = { |
David Cohen | d56d6b3 | 2013-10-04 13:01:40 -0700 | [diff] [blame] | 265 | .ngpio = 96, |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 266 | .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE, |
David Cohen | d56d6b3 | 2013-10-04 13:01:40 -0700 | [diff] [blame] | 267 | }; |
| 268 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 269 | static const struct intel_mid_gpio_ddata gpio_tangier = { |
David Cohen | d56d6b3 | 2013-10-04 13:01:40 -0700 | [diff] [blame] | 270 | .ngpio = 192, |
| 271 | .gplr_offset = 4, |
| 272 | .flis_base = 0xff0c0000, |
| 273 | .flis_len = 0x8000, |
| 274 | .get_flis_offset = NULL, |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 275 | .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE, |
David Cohen | d56d6b3 | 2013-10-04 13:01:40 -0700 | [diff] [blame] | 276 | }; |
| 277 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 278 | static DEFINE_PCI_DEVICE_TABLE(intel_gpio_ids) = { |
David Cohen | d56d6b3 | 2013-10-04 13:01:40 -0700 | [diff] [blame] | 279 | { |
| 280 | /* Lincroft */ |
| 281 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f), |
| 282 | .driver_data = (kernel_ulong_t)&gpio_lincroft, |
| 283 | }, |
| 284 | { |
| 285 | /* Penwell AON */ |
| 286 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f), |
| 287 | .driver_data = (kernel_ulong_t)&gpio_penwell_aon, |
| 288 | }, |
| 289 | { |
| 290 | /* Penwell Core */ |
| 291 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a), |
| 292 | .driver_data = (kernel_ulong_t)&gpio_penwell_core, |
| 293 | }, |
| 294 | { |
| 295 | /* Cloverview Aon */ |
| 296 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb), |
| 297 | .driver_data = (kernel_ulong_t)&gpio_cloverview_aon, |
| 298 | }, |
| 299 | { |
| 300 | /* Cloverview Core */ |
| 301 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7), |
| 302 | .driver_data = (kernel_ulong_t)&gpio_cloverview_core, |
| 303 | }, |
| 304 | { |
| 305 | /* Tangier */ |
| 306 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1199), |
| 307 | .driver_data = (kernel_ulong_t)&gpio_tangier, |
| 308 | }, |
| 309 | { 0 } |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 310 | }; |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 311 | MODULE_DEVICE_TABLE(pci, intel_gpio_ids); |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 312 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 313 | static void intel_mid_irq_handler(unsigned irq, struct irq_desc *desc) |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 314 | { |
Thomas Gleixner | 20e2aa9 | 2011-03-17 19:32:49 +0000 | [diff] [blame] | 315 | struct irq_data *data = irq_desc_get_irq_data(desc); |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 316 | struct intel_mid_gpio *priv = irq_data_get_irq_handler_data(data); |
Thomas Gleixner | 20e2aa9 | 2011-03-17 19:32:49 +0000 | [diff] [blame] | 317 | struct irq_chip *chip = irq_data_get_irq_chip(data); |
Thomas Gleixner | 84bead6 | 2011-03-17 19:32:58 +0000 | [diff] [blame] | 318 | u32 base, gpio, mask; |
Thomas Gleixner | 732063b | 2011-03-17 19:32:55 +0000 | [diff] [blame] | 319 | unsigned long pending; |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 320 | void __iomem *gedr; |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 321 | |
| 322 | /* check GPIO controller to check which pin triggered the interrupt */ |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 323 | for (base = 0; base < priv->chip.ngpio; base += 32) { |
| 324 | gedr = gpio_reg(&priv->chip, base, GEDR); |
Mika Westerberg | c8f925b | 2012-05-10 13:01:22 +0300 | [diff] [blame] | 325 | while ((pending = readl(gedr))) { |
Mathias Nyman | 2345b20 | 2011-07-08 10:02:18 +0100 | [diff] [blame] | 326 | gpio = __ffs(pending); |
Thomas Gleixner | 84bead6 | 2011-03-17 19:32:58 +0000 | [diff] [blame] | 327 | mask = BIT(gpio); |
Thomas Gleixner | 84bead6 | 2011-03-17 19:32:58 +0000 | [diff] [blame] | 328 | /* Clear before handling so we can't lose an edge */ |
| 329 | writel(mask, gedr); |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 330 | generic_handle_irq(irq_find_mapping(priv->domain, |
Mika Westerberg | 465f2bd | 2012-05-02 11:15:50 +0300 | [diff] [blame] | 331 | base + gpio)); |
Thomas Gleixner | 732063b | 2011-03-17 19:32:55 +0000 | [diff] [blame] | 332 | } |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 333 | } |
Feng Tang | 0766d20 | 2011-01-25 15:07:15 -0800 | [diff] [blame] | 334 | |
Thomas Gleixner | 20e2aa9 | 2011-03-17 19:32:49 +0000 | [diff] [blame] | 335 | chip->irq_eoi(data); |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 336 | } |
| 337 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 338 | static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv) |
Mika Westerberg | f5f9311 | 2012-04-05 12:15:17 +0300 | [diff] [blame] | 339 | { |
| 340 | void __iomem *reg; |
| 341 | unsigned base; |
| 342 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 343 | for (base = 0; base < priv->chip.ngpio; base += 32) { |
Mika Westerberg | f5f9311 | 2012-04-05 12:15:17 +0300 | [diff] [blame] | 344 | /* Clear the rising-edge detect register */ |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 345 | reg = gpio_reg(&priv->chip, base, GRER); |
Mika Westerberg | f5f9311 | 2012-04-05 12:15:17 +0300 | [diff] [blame] | 346 | writel(0, reg); |
| 347 | /* Clear the falling-edge detect register */ |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 348 | reg = gpio_reg(&priv->chip, base, GFER); |
Mika Westerberg | f5f9311 | 2012-04-05 12:15:17 +0300 | [diff] [blame] | 349 | writel(0, reg); |
| 350 | /* Clear the edge detect status register */ |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 351 | reg = gpio_reg(&priv->chip, base, GEDR); |
Mika Westerberg | f5f9311 | 2012-04-05 12:15:17 +0300 | [diff] [blame] | 352 | writel(~0, reg); |
| 353 | } |
| 354 | } |
| 355 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 356 | static int intel_gpio_irq_map(struct irq_domain *d, unsigned int virq, |
Mika Westerberg | 465f2bd | 2012-05-02 11:15:50 +0300 | [diff] [blame] | 357 | irq_hw_number_t hw) |
| 358 | { |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 359 | struct intel_mid_gpio *priv = d->host_data; |
Mika Westerberg | 465f2bd | 2012-05-02 11:15:50 +0300 | [diff] [blame] | 360 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 361 | irq_set_chip_and_handler_name(virq, &intel_mid_irqchip, |
| 362 | handle_simple_irq, "demux"); |
| 363 | irq_set_chip_data(virq, priv); |
Mika Westerberg | 465f2bd | 2012-05-02 11:15:50 +0300 | [diff] [blame] | 364 | irq_set_irq_type(virq, IRQ_TYPE_NONE); |
| 365 | |
| 366 | return 0; |
| 367 | } |
| 368 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 369 | static const struct irq_domain_ops intel_gpio_irq_ops = { |
| 370 | .map = intel_gpio_irq_map, |
Mika Westerberg | 465f2bd | 2012-05-02 11:15:50 +0300 | [diff] [blame] | 371 | .xlate = irq_domain_xlate_twocell, |
| 372 | }; |
| 373 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 374 | static int intel_gpio_runtime_idle(struct device *dev) |
Kristen Carlson Accardi | 7812803 | 2011-05-10 14:23:45 +0100 | [diff] [blame] | 375 | { |
Rafael J. Wysocki | 45f0a85 | 2013-06-03 21:49:52 +0200 | [diff] [blame] | 376 | pm_schedule_suspend(dev, 500); |
Kristen Carlson Accardi | 7812803 | 2011-05-10 14:23:45 +0100 | [diff] [blame] | 377 | return -EBUSY; |
| 378 | } |
| 379 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 380 | static const struct dev_pm_ops intel_gpio_pm_ops = { |
| 381 | SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle) |
Kristen Carlson Accardi | 7812803 | 2011-05-10 14:23:45 +0100 | [diff] [blame] | 382 | }; |
| 383 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 384 | static int intel_gpio_probe(struct pci_dev *pdev, |
Andy Shevchenko | 64c8cbc | 2013-05-22 13:20:11 +0300 | [diff] [blame] | 385 | const struct pci_device_id *id) |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 386 | { |
Andy Shevchenko | 64c8cbc | 2013-05-22 13:20:11 +0300 | [diff] [blame] | 387 | void __iomem *base; |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 388 | struct intel_mid_gpio *priv; |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 389 | u32 gpio_base; |
David Cohen | 2519f9a | 2013-05-06 16:11:03 -0700 | [diff] [blame] | 390 | u32 irq_base; |
Julia Lawall | d6a2b7b | 2012-08-05 11:52:34 +0200 | [diff] [blame] | 391 | int retval; |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 392 | struct intel_mid_gpio_ddata *ddata = |
| 393 | (struct intel_mid_gpio_ddata *)id->driver_data; |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 394 | |
Andy Shevchenko | 786e07e | 2013-05-22 13:20:12 +0300 | [diff] [blame] | 395 | retval = pcim_enable_device(pdev); |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 396 | if (retval) |
Mika Westerberg | 8302c74 | 2012-04-05 12:15:15 +0300 | [diff] [blame] | 397 | return retval; |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 398 | |
Andy Shevchenko | 786e07e | 2013-05-22 13:20:12 +0300 | [diff] [blame] | 399 | retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev)); |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 400 | if (retval) { |
Andy Shevchenko | 786e07e | 2013-05-22 13:20:12 +0300 | [diff] [blame] | 401 | dev_err(&pdev->dev, "I/O memory mapping error\n"); |
| 402 | return retval; |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 403 | } |
Andy Shevchenko | 786e07e | 2013-05-22 13:20:12 +0300 | [diff] [blame] | 404 | |
| 405 | base = pcim_iomap_table(pdev)[1]; |
Andy Shevchenko | 64c8cbc | 2013-05-22 13:20:11 +0300 | [diff] [blame] | 406 | |
| 407 | irq_base = readl(base); |
| 408 | gpio_base = readl(sizeof(u32) + base); |
| 409 | |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 410 | /* release the IO mapping, since we already get the info from bar1 */ |
Andy Shevchenko | 786e07e | 2013-05-22 13:20:12 +0300 | [diff] [blame] | 411 | pcim_iounmap_regions(pdev, 1 << 1); |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 412 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 413 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
| 414 | if (!priv) { |
Andy Shevchenko | 8aca119 | 2013-05-22 13:20:13 +0300 | [diff] [blame] | 415 | dev_err(&pdev->dev, "can't allocate chip data\n"); |
Andy Shevchenko | 786e07e | 2013-05-22 13:20:12 +0300 | [diff] [blame] | 416 | return -ENOMEM; |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 417 | } |
Mika Westerberg | b3e35af | 2012-04-05 12:15:16 +0300 | [diff] [blame] | 418 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 419 | priv->reg_base = pcim_iomap_table(pdev)[0]; |
| 420 | priv->chip.label = dev_name(&pdev->dev); |
| 421 | priv->chip.request = intel_gpio_request; |
| 422 | priv->chip.direction_input = intel_gpio_direction_input; |
| 423 | priv->chip.direction_output = intel_gpio_direction_output; |
| 424 | priv->chip.get = intel_gpio_get; |
| 425 | priv->chip.set = intel_gpio_set; |
| 426 | priv->chip.to_irq = intel_gpio_to_irq; |
| 427 | priv->chip.base = gpio_base; |
| 428 | priv->chip.ngpio = ddata->ngpio; |
| 429 | priv->chip.can_sleep = 0; |
| 430 | priv->pdev = pdev; |
David Cohen | 2519f9a | 2013-05-06 16:11:03 -0700 | [diff] [blame] | 431 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 432 | spin_lock_init(&priv->lock); |
Andy Shevchenko | aeb168f | 2013-05-22 13:20:10 +0300 | [diff] [blame] | 433 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 434 | priv->domain = irq_domain_add_simple(pdev->dev.of_node, ddata->ngpio, |
| 435 | irq_base, &intel_gpio_irq_ops, priv); |
| 436 | if (!priv->domain) |
Andy Shevchenko | 786e07e | 2013-05-22 13:20:12 +0300 | [diff] [blame] | 437 | return -ENOMEM; |
David Cohen | 2519f9a | 2013-05-06 16:11:03 -0700 | [diff] [blame] | 438 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 439 | pci_set_drvdata(pdev, priv); |
| 440 | retval = gpiochip_add(&priv->chip); |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 441 | if (retval) { |
Andy Shevchenko | 8aca119 | 2013-05-22 13:20:13 +0300 | [diff] [blame] | 442 | dev_err(&pdev->dev, "gpiochip_add error %d\n", retval); |
Andy Shevchenko | 786e07e | 2013-05-22 13:20:12 +0300 | [diff] [blame] | 443 | return retval; |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 444 | } |
Mika Westerberg | f5f9311 | 2012-04-05 12:15:17 +0300 | [diff] [blame] | 445 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 446 | intel_mid_irq_init_hw(priv); |
Mika Westerberg | f5f9311 | 2012-04-05 12:15:17 +0300 | [diff] [blame] | 447 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 448 | irq_set_handler_data(pdev->irq, priv); |
| 449 | irq_set_chained_handler(pdev->irq, intel_mid_irq_handler); |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 450 | |
Kristen Carlson Accardi | 7812803 | 2011-05-10 14:23:45 +0100 | [diff] [blame] | 451 | pm_runtime_put_noidle(&pdev->dev); |
| 452 | pm_runtime_allow(&pdev->dev); |
| 453 | |
Mika Westerberg | 8302c74 | 2012-04-05 12:15:15 +0300 | [diff] [blame] | 454 | return 0; |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 455 | } |
| 456 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 457 | static struct pci_driver intel_gpio_driver = { |
| 458 | .name = "intel_mid_gpio", |
| 459 | .id_table = intel_gpio_ids, |
| 460 | .probe = intel_gpio_probe, |
Kristen Carlson Accardi | 7812803 | 2011-05-10 14:23:45 +0100 | [diff] [blame] | 461 | .driver = { |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 462 | .pm = &intel_gpio_pm_ops, |
Kristen Carlson Accardi | 7812803 | 2011-05-10 14:23:45 +0100 | [diff] [blame] | 463 | }, |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 464 | }; |
| 465 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 466 | static int __init intel_gpio_init(void) |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 467 | { |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 468 | return pci_register_driver(&intel_gpio_driver); |
Alek Du | 8bf0261 | 2009-09-22 16:46:36 -0700 | [diff] [blame] | 469 | } |
| 470 | |
David Cohen | f89a768 | 2013-10-04 13:01:42 -0700 | [diff] [blame] | 471 | device_initcall(intel_gpio_init); |