blob: 6edc25e0dd15250286919650c8f575f9cb334b02 [file] [log] [blame]
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001/*
2 * Copyright (C) 1999 - 2010 Intel Corporation.
Tomoyae91530e2010-12-12 20:24:15 +00003 * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19#include <linux/interrupt.h>
20#include <linux/delay.h>
21#include <linux/io.h>
22#include <linux/module.h>
23#include <linux/sched.h>
24#include <linux/pci.h>
25#include <linux/init.h>
26#include <linux/kernel.h>
27#include <linux/types.h>
28#include <linux/errno.h>
29#include <linux/netdevice.h>
30#include <linux/skbuff.h>
31#include <linux/can.h>
32#include <linux/can/dev.h>
33#include <linux/can/error.h>
34
Tomoya0a804102010-11-17 14:06:25 +000035#define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */
36#define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */
37#define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1))
38#define PCH_CTRL_CCE BIT(6)
39#define PCH_CTRL_OPT BIT(7) /* The OPT bit of CANCONT register. */
40#define PCH_OPT_SILENT BIT(3) /* The Silent bit of CANOPT reg. */
41#define PCH_OPT_LBACK BIT(4) /* The LoopBack bit of CANOPT reg. */
42
Tomoya086b5652010-11-17 01:13:16 +000043#define PCH_CMASK_RX_TX_SET 0x00f3
44#define PCH_CMASK_RX_TX_GET 0x0073
45#define PCH_CMASK_ALL 0xff
Tomoya0a804102010-11-17 14:06:25 +000046#define PCH_CMASK_NEWDAT BIT(2)
47#define PCH_CMASK_CLRINTPND BIT(3)
48#define PCH_CMASK_CTRL BIT(4)
49#define PCH_CMASK_ARB BIT(5)
50#define PCH_CMASK_MASK BIT(6)
51#define PCH_CMASK_RDWR BIT(7)
52#define PCH_IF_MCONT_NEWDAT BIT(15)
53#define PCH_IF_MCONT_MSGLOST BIT(14)
54#define PCH_IF_MCONT_INTPND BIT(13)
55#define PCH_IF_MCONT_UMASK BIT(12)
56#define PCH_IF_MCONT_TXIE BIT(11)
57#define PCH_IF_MCONT_RXIE BIT(10)
58#define PCH_IF_MCONT_RMTEN BIT(9)
59#define PCH_IF_MCONT_TXRQXT BIT(8)
60#define PCH_IF_MCONT_EOB BIT(7)
61#define PCH_IF_MCONT_DLC (BIT(0) | BIT(1) | BIT(2) | BIT(3))
62#define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15))
63#define PCH_ID2_DIR BIT(13)
64#define PCH_ID2_XTD BIT(14)
65#define PCH_ID_MSGVAL BIT(15)
66#define PCH_IF_CREQ_BUSY BIT(15)
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +000067
Tomoya086b5652010-11-17 01:13:16 +000068#define PCH_STATUS_INT 0x8000
Xi Wang44b0052c2011-12-12 02:16:20 -050069#define PCH_RP 0x00008000
Tomoya086b5652010-11-17 01:13:16 +000070#define PCH_REC 0x00007f00
71#define PCH_TEC 0x000000ff
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +000072
Tomoya0a804102010-11-17 14:06:25 +000073#define PCH_TX_OK BIT(3)
74#define PCH_RX_OK BIT(4)
75#define PCH_EPASSIV BIT(5)
76#define PCH_EWARN BIT(6)
77#define PCH_BUS_OFF BIT(7)
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +000078
79/* bit position of certain controller bits. */
Tomoyabd58cbc2010-12-12 20:24:12 +000080#define PCH_BIT_BRP_SHIFT 0
81#define PCH_BIT_SJW_SHIFT 6
82#define PCH_BIT_TSEG1_SHIFT 8
83#define PCH_BIT_TSEG2_SHIFT 12
84#define PCH_BIT_BRPE_BRPE_SHIFT 6
85
Tomoya086b5652010-11-17 01:13:16 +000086#define PCH_MSK_BITT_BRP 0x3f
87#define PCH_MSK_BRPE_BRPE 0x3c0
88#define PCH_MSK_CTRL_IE_SIE_EIE 0x07
89#define PCH_COUNTER_LIMIT 10
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +000090
91#define PCH_CAN_CLK 50000000 /* 50MHz */
92
Tomoya9388b162010-12-12 20:24:17 +000093/*
94 * Define the number of message object.
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +000095 * PCH CAN communications are done via Message RAM.
Tomoya9388b162010-12-12 20:24:17 +000096 * The Message RAM consists of 32 message objects.
97 */
Tomoya15ffc8f2010-11-29 18:15:02 +000098#define PCH_RX_OBJ_NUM 26
99#define PCH_TX_OBJ_NUM 6
100#define PCH_RX_OBJ_START 1
101#define PCH_RX_OBJ_END PCH_RX_OBJ_NUM
102#define PCH_TX_OBJ_START (PCH_RX_OBJ_END + 1)
103#define PCH_TX_OBJ_END (PCH_RX_OBJ_NUM + PCH_TX_OBJ_NUM)
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000104
105#define PCH_FIFO_THRESH 16
106
Tomoya76d94b22010-12-12 20:24:07 +0000107/* TxRqst2 show status of MsgObjNo.17~32 */
108#define PCH_TREQ2_TX_MASK (((1 << PCH_TX_OBJ_NUM) - 1) <<\
109 (PCH_RX_OBJ_END - 16))
110
Tomoya8339a7e2010-11-29 18:11:52 +0000111enum pch_ifreg {
112 PCH_RX_IFREG,
113 PCH_TX_IFREG,
114};
115
Tomoyad68f6832010-11-29 18:16:15 +0000116enum pch_can_err {
117 PCH_STUF_ERR = 1,
118 PCH_FORM_ERR,
119 PCH_ACK_ERR,
120 PCH_BIT1_ERR,
121 PCH_BIT0_ERR,
122 PCH_CRC_ERR,
123 PCH_LEC_ALL,
124};
125
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000126enum pch_can_mode {
127 PCH_CAN_ENABLE,
128 PCH_CAN_DISABLE,
129 PCH_CAN_ALL,
130 PCH_CAN_NONE,
131 PCH_CAN_STOP,
Tomoya9388b162010-12-12 20:24:17 +0000132 PCH_CAN_RUN,
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000133};
134
Tomoya8339a7e2010-11-29 18:11:52 +0000135struct pch_can_if_regs {
136 u32 creq;
137 u32 cmask;
138 u32 mask1;
139 u32 mask2;
140 u32 id1;
141 u32 id2;
142 u32 mcont;
Tomoya8ac97022010-12-12 20:24:09 +0000143 u32 data[4];
Tomoya8339a7e2010-11-29 18:11:52 +0000144 u32 rsv[13];
145};
146
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000147struct pch_can_regs {
148 u32 cont;
149 u32 stat;
150 u32 errc;
151 u32 bitt;
152 u32 intr;
153 u32 opt;
154 u32 brpe;
Tomoya8339a7e2010-11-29 18:11:52 +0000155 u32 reserve;
156 struct pch_can_if_regs ifregs[2]; /* [0]=if1 [1]=if2 */
157 u32 reserve1[8];
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000158 u32 treq1;
159 u32 treq2;
Tomoya8339a7e2010-11-29 18:11:52 +0000160 u32 reserve2[6];
161 u32 data1;
162 u32 data2;
163 u32 reserve3[6];
164 u32 canipend1;
165 u32 canipend2;
166 u32 reserve4[6];
167 u32 canmval1;
168 u32 canmval2;
169 u32 reserve5[37];
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000170 u32 srst;
171};
172
173struct pch_can_priv {
174 struct can_priv can;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000175 struct pci_dev *dev;
Tomoyabd58cbc2010-12-12 20:24:12 +0000176 u32 tx_enable[PCH_TX_OBJ_END];
177 u32 rx_enable[PCH_TX_OBJ_END];
178 u32 rx_link[PCH_TX_OBJ_END];
179 u32 int_enables;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000180 struct net_device *ndev;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000181 struct pch_can_regs __iomem *regs;
182 struct napi_struct napi;
Tomoyabd58cbc2010-12-12 20:24:12 +0000183 int tx_obj; /* Point next Tx Obj index */
184 int use_msi;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000185};
186
187static struct can_bittiming_const pch_can_bittiming_const = {
188 .name = KBUILD_MODNAME,
Tomoya MORINAGAebc02e92011-02-09 16:46:21 -0800189 .tseg1_min = 2,
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000190 .tseg1_max = 16,
Tomoya MORINAGAebc02e92011-02-09 16:46:21 -0800191 .tseg2_min = 1,
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000192 .tseg2_max = 8,
193 .sjw_max = 4,
194 .brp_min = 1,
195 .brp_max = 1024, /* 6bit + extended 4bit */
196 .brp_inc = 1,
197};
198
199static DEFINE_PCI_DEVICE_TABLE(pch_pci_tbl) = {
200 {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,},
201 {0,}
202};
203MODULE_DEVICE_TABLE(pci, pch_pci_tbl);
204
Marc Kleine-Budde526de532010-10-30 16:27:48 -0700205static inline void pch_can_bit_set(void __iomem *addr, u32 mask)
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000206{
207 iowrite32(ioread32(addr) | mask, addr);
208}
209
Marc Kleine-Budde526de532010-10-30 16:27:48 -0700210static inline void pch_can_bit_clear(void __iomem *addr, u32 mask)
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000211{
212 iowrite32(ioread32(addr) & ~mask, addr);
213}
214
215static void pch_can_set_run_mode(struct pch_can_priv *priv,
216 enum pch_can_mode mode)
217{
218 switch (mode) {
219 case PCH_CAN_RUN:
Tomoya086b5652010-11-17 01:13:16 +0000220 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000221 break;
222
223 case PCH_CAN_STOP:
Tomoya086b5652010-11-17 01:13:16 +0000224 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000225 break;
226
227 default:
Tomoya435b4ef2010-12-12 20:24:16 +0000228 netdev_err(priv->ndev, "%s -> Invalid Mode.\n", __func__);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000229 break;
230 }
231}
232
233static void pch_can_set_optmode(struct pch_can_priv *priv)
234{
235 u32 reg_val = ioread32(&priv->regs->opt);
236
237 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
Tomoya086b5652010-11-17 01:13:16 +0000238 reg_val |= PCH_OPT_SILENT;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000239
240 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
Tomoya086b5652010-11-17 01:13:16 +0000241 reg_val |= PCH_OPT_LBACK;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000242
Tomoya086b5652010-11-17 01:13:16 +0000243 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000244 iowrite32(reg_val, &priv->regs->opt);
245}
246
Tomoyabd58cbc2010-12-12 20:24:12 +0000247static void pch_can_rw_msg_obj(void __iomem *creq_addr, u32 num)
248{
249 int counter = PCH_COUNTER_LIMIT;
250 u32 ifx_creq;
251
252 iowrite32(num, creq_addr);
253 while (counter) {
254 ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY;
255 if (!ifx_creq)
256 break;
257 counter--;
258 udelay(1);
259 }
260 if (!counter)
261 pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__);
262}
263
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000264static void pch_can_set_int_enables(struct pch_can_priv *priv,
265 enum pch_can_mode interrupt_no)
266{
267 switch (interrupt_no) {
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000268 case PCH_CAN_DISABLE:
Tomoya086b5652010-11-17 01:13:16 +0000269 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000270 break;
271
272 case PCH_CAN_ALL:
Tomoya086b5652010-11-17 01:13:16 +0000273 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000274 break;
275
276 case PCH_CAN_NONE:
Tomoya086b5652010-11-17 01:13:16 +0000277 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000278 break;
279
280 default:
Tomoya435b4ef2010-12-12 20:24:16 +0000281 netdev_err(priv->ndev, "Invalid interrupt number.\n");
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000282 break;
283 }
284}
285
Tomoya8339a7e2010-11-29 18:11:52 +0000286static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num,
Tomoyabd58cbc2010-12-12 20:24:12 +0000287 int set, enum pch_ifreg dir)
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000288{
Tomoya8339a7e2010-11-29 18:11:52 +0000289 u32 ie;
290
291 if (dir)
292 ie = PCH_IF_MCONT_TXIE;
293 else
294 ie = PCH_IF_MCONT_RXIE;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000295
Tomoyac7551452010-12-12 20:24:21 +0000296 /* Reading the Msg buffer from Message RAM to IF1/2 registers. */
Tomoya8339a7e2010-11-29 18:11:52 +0000297 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
Tomoyabd58cbc2010-12-12 20:24:12 +0000298 pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000299
Tomoya9388b162010-12-12 20:24:17 +0000300 /* Setting the IF1/2MASK1 register to access MsgVal and RxIE bits */
Tomoya086b5652010-11-17 01:13:16 +0000301 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL,
Tomoya8339a7e2010-11-29 18:11:52 +0000302 &priv->regs->ifregs[dir].cmask);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000303
Tomoyabd58cbc2010-12-12 20:24:12 +0000304 if (set) {
Tomoya9388b162010-12-12 20:24:17 +0000305 /* Setting the MsgVal and RxIE/TxIE bits */
Tomoya8339a7e2010-11-29 18:11:52 +0000306 pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie);
307 pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
Tomoyabd58cbc2010-12-12 20:24:12 +0000308 } else {
Tomoya9388b162010-12-12 20:24:17 +0000309 /* Clearing the MsgVal and RxIE/TxIE bits */
Tomoya8339a7e2010-11-29 18:11:52 +0000310 pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie);
311 pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000312 }
313
Tomoyabd58cbc2010-12-12 20:24:12 +0000314 pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000315}
316
Tomoyabd58cbc2010-12-12 20:24:12 +0000317static void pch_can_set_rx_all(struct pch_can_priv *priv, int set)
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000318{
319 int i;
320
321 /* Traversing to obtain the object configured as receivers. */
Tomoya15ffc8f2010-11-29 18:15:02 +0000322 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++)
323 pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000324}
325
Tomoyabd58cbc2010-12-12 20:24:12 +0000326static void pch_can_set_tx_all(struct pch_can_priv *priv, int set)
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000327{
328 int i;
329
330 /* Traversing to obtain the object configured as transmit object. */
Tomoya15ffc8f2010-11-29 18:15:02 +0000331 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
332 pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000333}
334
Tomoyabd58cbc2010-12-12 20:24:12 +0000335static u32 pch_can_int_pending(struct pch_can_priv *priv)
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000336{
337 return ioread32(&priv->regs->intr) & 0xffff;
338}
339
Tomoyabd58cbc2010-12-12 20:24:12 +0000340static void pch_can_clear_if_buffers(struct pch_can_priv *priv)
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000341{
Tomoyabd58cbc2010-12-12 20:24:12 +0000342 int i; /* Msg Obj ID (1~32) */
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000343
Tomoyabd58cbc2010-12-12 20:24:12 +0000344 for (i = PCH_RX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
Tomoya8339a7e2010-11-29 18:11:52 +0000345 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask);
346 iowrite32(0xffff, &priv->regs->ifregs[0].mask1);
347 iowrite32(0xffff, &priv->regs->ifregs[0].mask2);
348 iowrite32(0x0, &priv->regs->ifregs[0].id1);
349 iowrite32(0x0, &priv->regs->ifregs[0].id2);
350 iowrite32(0x0, &priv->regs->ifregs[0].mcont);
Tomoya8ac97022010-12-12 20:24:09 +0000351 iowrite32(0x0, &priv->regs->ifregs[0].data[0]);
352 iowrite32(0x0, &priv->regs->ifregs[0].data[1]);
353 iowrite32(0x0, &priv->regs->ifregs[0].data[2]);
354 iowrite32(0x0, &priv->regs->ifregs[0].data[3]);
Tomoya086b5652010-11-17 01:13:16 +0000355 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
356 PCH_CMASK_ARB | PCH_CMASK_CTRL,
Tomoya8339a7e2010-11-29 18:11:52 +0000357 &priv->regs->ifregs[0].cmask);
Tomoyabd58cbc2010-12-12 20:24:12 +0000358 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000359 }
360}
361
362static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
363{
364 int i;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000365
Tomoya15ffc8f2010-11-29 18:15:02 +0000366 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
Tomoya9388b162010-12-12 20:24:17 +0000367 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
Tomoyabd58cbc2010-12-12 20:24:12 +0000368 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000369
Tomoya15ffc8f2010-11-29 18:15:02 +0000370 iowrite32(0x0, &priv->regs->ifregs[0].id1);
371 iowrite32(0x0, &priv->regs->ifregs[0].id2);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000372
Tomoya15ffc8f2010-11-29 18:15:02 +0000373 pch_can_bit_set(&priv->regs->ifregs[0].mcont,
374 PCH_IF_MCONT_UMASK);
375
Tomoya15ffc8f2010-11-29 18:15:02 +0000376 /* In case FIFO mode, Last EoB of Rx Obj must be 1 */
377 if (i == PCH_RX_OBJ_END)
Tomoya8339a7e2010-11-29 18:11:52 +0000378 pch_can_bit_set(&priv->regs->ifregs[0].mcont,
Tomoyabd58cbc2010-12-12 20:24:12 +0000379 PCH_IF_MCONT_EOB);
380 else
381 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
Tomoya086b5652010-11-17 01:13:16 +0000382 PCH_IF_MCONT_EOB);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000383
Tomoya15ffc8f2010-11-29 18:15:02 +0000384 iowrite32(0, &priv->regs->ifregs[0].mask1);
385 pch_can_bit_clear(&priv->regs->ifregs[0].mask2,
386 0x1fff | PCH_MASK2_MDIR_MXTD);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000387
Tomoya15ffc8f2010-11-29 18:15:02 +0000388 /* Setting CMASK for writing */
Tomoya9388b162010-12-12 20:24:17 +0000389 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB |
390 PCH_CMASK_CTRL, &priv->regs->ifregs[0].cmask);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000391
Tomoyabd58cbc2010-12-12 20:24:12 +0000392 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
Tomoya15ffc8f2010-11-29 18:15:02 +0000393 }
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000394
Tomoya15ffc8f2010-11-29 18:15:02 +0000395 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
Tomoya9388b162010-12-12 20:24:17 +0000396 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask);
Tomoyabd58cbc2010-12-12 20:24:12 +0000397 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000398
Tomoya15ffc8f2010-11-29 18:15:02 +0000399 /* Resetting DIR bit for reception */
400 iowrite32(0x0, &priv->regs->ifregs[1].id1);
Tomoya44c9aa82010-12-12 20:24:14 +0000401 iowrite32(PCH_ID2_DIR, &priv->regs->ifregs[1].id2);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000402
Tomoya15ffc8f2010-11-29 18:15:02 +0000403 /* Setting EOB bit for transmitter */
Tomoya44c9aa82010-12-12 20:24:14 +0000404 iowrite32(PCH_IF_MCONT_EOB | PCH_IF_MCONT_UMASK,
405 &priv->regs->ifregs[1].mcont);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000406
Tomoya15ffc8f2010-11-29 18:15:02 +0000407 iowrite32(0, &priv->regs->ifregs[1].mask1);
408 pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000409
Tomoya15ffc8f2010-11-29 18:15:02 +0000410 /* Setting CMASK for writing */
Tomoya9388b162010-12-12 20:24:17 +0000411 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB |
412 PCH_CMASK_CTRL, &priv->regs->ifregs[1].cmask);
Tomoya15ffc8f2010-11-29 18:15:02 +0000413
Tomoyabd58cbc2010-12-12 20:24:12 +0000414 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000415 }
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000416}
417
418static void pch_can_init(struct pch_can_priv *priv)
419{
420 /* Stopping the Can device. */
421 pch_can_set_run_mode(priv, PCH_CAN_STOP);
422
423 /* Clearing all the message object buffers. */
Tomoyabd58cbc2010-12-12 20:24:12 +0000424 pch_can_clear_if_buffers(priv);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000425
426 /* Configuring the respective message object as either rx/tx object. */
427 pch_can_config_rx_tx_buffers(priv);
428
429 /* Enabling the interrupts. */
430 pch_can_set_int_enables(priv, PCH_CAN_ALL);
431}
432
433static void pch_can_release(struct pch_can_priv *priv)
434{
435 /* Stooping the CAN device. */
436 pch_can_set_run_mode(priv, PCH_CAN_STOP);
437
438 /* Disabling the interrupts. */
439 pch_can_set_int_enables(priv, PCH_CAN_NONE);
440
441 /* Disabling all the receive object. */
Tomoya8339a7e2010-11-29 18:11:52 +0000442 pch_can_set_rx_all(priv, 0);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000443
444 /* Disabling all the transmit object. */
Tomoya8339a7e2010-11-29 18:11:52 +0000445 pch_can_set_tx_all(priv, 0);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000446}
447
448/* This function clears interrupt(s) from the CAN device. */
449static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
450{
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000451 /* Clear interrupt for transmit object */
Tomoya15ffc8f2010-11-29 18:15:02 +0000452 if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) {
453 /* Setting CMASK for clearing the reception interrupts. */
454 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
455 &priv->regs->ifregs[0].cmask);
456
457 /* Clearing the Dir bit. */
458 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
459
460 /* Clearing NewDat & IntPnd */
461 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
462 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND);
463
Tomoyabd58cbc2010-12-12 20:24:12 +0000464 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, mask);
Tomoya15ffc8f2010-11-29 18:15:02 +0000465 } else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) {
Tomoya9388b162010-12-12 20:24:17 +0000466 /*
467 * Setting CMASK for clearing interrupts for frame transmission.
468 */
Tomoya086b5652010-11-17 01:13:16 +0000469 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
Tomoya8339a7e2010-11-29 18:11:52 +0000470 &priv->regs->ifregs[1].cmask);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000471
472 /* Resetting the ID registers. */
Tomoya8339a7e2010-11-29 18:11:52 +0000473 pch_can_bit_set(&priv->regs->ifregs[1].id2,
Tomoya086b5652010-11-17 01:13:16 +0000474 PCH_ID2_DIR | (0x7ff << 2));
Tomoya8339a7e2010-11-29 18:11:52 +0000475 iowrite32(0x0, &priv->regs->ifregs[1].id1);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000476
477 /* Claring NewDat, TxRqst & IntPnd */
Tomoya8339a7e2010-11-29 18:11:52 +0000478 pch_can_bit_clear(&priv->regs->ifregs[1].mcont,
Tomoya086b5652010-11-17 01:13:16 +0000479 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
480 PCH_IF_MCONT_TXRQXT);
Tomoyabd58cbc2010-12-12 20:24:12 +0000481 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, mask);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000482 }
483}
484
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000485static void pch_can_reset(struct pch_can_priv *priv)
486{
487 /* write to sw reset register */
488 iowrite32(1, &priv->regs->srst);
489 iowrite32(0, &priv->regs->srst);
490}
491
492static void pch_can_error(struct net_device *ndev, u32 status)
493{
494 struct sk_buff *skb;
495 struct pch_can_priv *priv = netdev_priv(ndev);
496 struct can_frame *cf;
Tomoyad68f6832010-11-29 18:16:15 +0000497 u32 errc, lec;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000498 struct net_device_stats *stats = &(priv->ndev->stats);
499 enum can_state state = priv->can.state;
500
501 skb = alloc_can_err_skb(ndev, &cf);
502 if (!skb)
503 return;
504
505 if (status & PCH_BUS_OFF) {
Tomoya8339a7e2010-11-29 18:11:52 +0000506 pch_can_set_tx_all(priv, 0);
507 pch_can_set_rx_all(priv, 0);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000508 state = CAN_STATE_BUS_OFF;
509 cf->can_id |= CAN_ERR_BUSOFF;
510 can_bus_off(ndev);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000511 }
512
Tomoya44c9aa82010-12-12 20:24:14 +0000513 errc = ioread32(&priv->regs->errc);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000514 /* Warning interrupt. */
515 if (status & PCH_EWARN) {
516 state = CAN_STATE_ERROR_WARNING;
517 priv->can.can_stats.error_warning++;
518 cf->can_id |= CAN_ERR_CRTL;
Tomoya086b5652010-11-17 01:13:16 +0000519 if (((errc & PCH_REC) >> 8) > 96)
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000520 cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
Tomoya086b5652010-11-17 01:13:16 +0000521 if ((errc & PCH_TEC) > 96)
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000522 cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
Tomoya435b4ef2010-12-12 20:24:16 +0000523 netdev_dbg(ndev,
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000524 "%s -> Error Counter is more than 96.\n", __func__);
525 }
526 /* Error passive interrupt. */
527 if (status & PCH_EPASSIV) {
528 priv->can.can_stats.error_passive++;
529 state = CAN_STATE_ERROR_PASSIVE;
530 cf->can_id |= CAN_ERR_CRTL;
Xi Wang44b0052c2011-12-12 02:16:20 -0500531 if (errc & PCH_RP)
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000532 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
Tomoya086b5652010-11-17 01:13:16 +0000533 if ((errc & PCH_TEC) > 127)
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000534 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
Tomoya435b4ef2010-12-12 20:24:16 +0000535 netdev_dbg(ndev,
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000536 "%s -> CAN controller is ERROR PASSIVE .\n", __func__);
537 }
538
Tomoyad68f6832010-11-29 18:16:15 +0000539 lec = status & PCH_LEC_ALL;
540 switch (lec) {
541 case PCH_STUF_ERR:
542 cf->data[2] |= CAN_ERR_PROT_STUFF;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000543 priv->can.can_stats.bus_error++;
544 stats->rx_errors++;
Tomoyad68f6832010-11-29 18:16:15 +0000545 break;
546 case PCH_FORM_ERR:
547 cf->data[2] |= CAN_ERR_PROT_FORM;
548 priv->can.can_stats.bus_error++;
549 stats->rx_errors++;
550 break;
551 case PCH_ACK_ERR:
552 cf->can_id |= CAN_ERR_ACK;
553 priv->can.can_stats.bus_error++;
554 stats->rx_errors++;
555 break;
556 case PCH_BIT1_ERR:
557 case PCH_BIT0_ERR:
558 cf->data[2] |= CAN_ERR_PROT_BIT;
559 priv->can.can_stats.bus_error++;
560 stats->rx_errors++;
561 break;
562 case PCH_CRC_ERR:
563 cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ |
564 CAN_ERR_PROT_LOC_CRC_DEL;
565 priv->can.can_stats.bus_error++;
566 stats->rx_errors++;
567 break;
568 case PCH_LEC_ALL: /* Written by CPU. No error status */
569 break;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000570 }
571
Tomoya0c78ab72010-12-12 20:24:25 +0000572 cf->data[6] = errc & PCH_TEC;
573 cf->data[7] = (errc & PCH_REC) >> 8;
574
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000575 priv->can.state = state;
Tomoyacfb7e5f2010-12-12 20:24:26 +0000576 netif_receive_skb(skb);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000577
578 stats->rx_packets++;
579 stats->rx_bytes += cf->can_dlc;
580}
581
582static irqreturn_t pch_can_interrupt(int irq, void *dev_id)
583{
584 struct net_device *ndev = (struct net_device *)dev_id;
585 struct pch_can_priv *priv = netdev_priv(ndev);
586
Tomoya3332bc52010-12-12 20:24:23 +0000587 if (!pch_can_int_pending(priv))
588 return IRQ_NONE;
589
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000590 pch_can_set_int_enables(priv, PCH_CAN_NONE);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000591 napi_schedule(&priv->napi);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000592 return IRQ_HANDLED;
593}
594
Tomoya1d5b4b22010-12-12 20:24:10 +0000595static void pch_fifo_thresh(struct pch_can_priv *priv, int obj_id)
596{
597 if (obj_id < PCH_FIFO_THRESH) {
598 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL |
599 PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask);
600
601 /* Clearing the Dir bit. */
602 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
603
604 /* Clearing NewDat & IntPnd */
605 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
606 PCH_IF_MCONT_INTPND);
Tomoyabd58cbc2010-12-12 20:24:12 +0000607 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
Tomoya1d5b4b22010-12-12 20:24:10 +0000608 } else if (obj_id > PCH_FIFO_THRESH) {
609 pch_can_int_clr(priv, obj_id);
610 } else if (obj_id == PCH_FIFO_THRESH) {
611 int cnt;
612 for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++)
613 pch_can_int_clr(priv, cnt + 1);
614 }
615}
616
617static void pch_can_rx_msg_lost(struct net_device *ndev, int obj_id)
618{
619 struct pch_can_priv *priv = netdev_priv(ndev);
620 struct net_device_stats *stats = &(priv->ndev->stats);
621 struct sk_buff *skb;
622 struct can_frame *cf;
623
624 netdev_dbg(priv->ndev, "Msg Obj is overwritten.\n");
625 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
626 PCH_IF_MCONT_MSGLOST);
627 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
628 &priv->regs->ifregs[0].cmask);
Tomoyabd58cbc2010-12-12 20:24:12 +0000629 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
Tomoya1d5b4b22010-12-12 20:24:10 +0000630
631 skb = alloc_can_err_skb(ndev, &cf);
632 if (!skb)
633 return;
634
635 cf->can_id |= CAN_ERR_CRTL;
636 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
637 stats->rx_over_errors++;
638 stats->rx_errors++;
639
640 netif_receive_skb(skb);
641}
642
643static int pch_can_rx_normal(struct net_device *ndev, u32 obj_num, int quota)
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000644{
645 u32 reg;
646 canid_t id;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000647 int rcv_pkts = 0;
648 struct sk_buff *skb;
649 struct can_frame *cf;
650 struct pch_can_priv *priv = netdev_priv(ndev);
651 struct net_device_stats *stats = &(priv->ndev->stats);
Tomoya1d5b4b22010-12-12 20:24:10 +0000652 int i;
653 u32 id2;
Tomoya8ac97022010-12-12 20:24:09 +0000654 u16 data_reg;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000655
Tomoya1d5b4b22010-12-12 20:24:10 +0000656 do {
Justin P. Mattock70f23fd2011-05-10 10:16:21 +0200657 /* Reading the message object from the Message RAM */
Tomoya1d5b4b22010-12-12 20:24:10 +0000658 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
Tomoyabd58cbc2010-12-12 20:24:12 +0000659 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_num);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000660
Tomoya1d5b4b22010-12-12 20:24:10 +0000661 /* Reading the MCONT register. */
662 reg = ioread32(&priv->regs->ifregs[0].mcont);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000663
Tomoya1d5b4b22010-12-12 20:24:10 +0000664 if (reg & PCH_IF_MCONT_EOB)
665 break;
666
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000667 /* If MsgLost bit set. */
Tomoya086b5652010-11-17 01:13:16 +0000668 if (reg & PCH_IF_MCONT_MSGLOST) {
Tomoya1d5b4b22010-12-12 20:24:10 +0000669 pch_can_rx_msg_lost(ndev, obj_num);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000670 rcv_pkts++;
Tomoya1d5b4b22010-12-12 20:24:10 +0000671 quota--;
672 obj_num++;
673 continue;
674 } else if (!(reg & PCH_IF_MCONT_NEWDAT)) {
675 obj_num++;
676 continue;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000677 }
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000678
679 skb = alloc_can_skb(priv->ndev, &cf);
Tomoya3332bc52010-12-12 20:24:23 +0000680 if (!skb) {
681 netdev_err(ndev, "alloc_can_skb Failed\n");
682 return rcv_pkts;
683 }
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000684
685 /* Get Received data */
Tomoya1d5b4b22010-12-12 20:24:10 +0000686 id2 = ioread32(&priv->regs->ifregs[0].id2);
687 if (id2 & PCH_ID2_XTD) {
Tomoya8339a7e2010-11-29 18:11:52 +0000688 id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff);
Tomoya1d5b4b22010-12-12 20:24:10 +0000689 id |= (((id2) & 0x1fff) << 16);
690 cf->can_id = id | CAN_EFF_FLAG;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000691 } else {
Tomoya1d5b4b22010-12-12 20:24:10 +0000692 id = (id2 >> 2) & CAN_SFF_MASK;
693 cf->can_id = id;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000694 }
695
Tomoya1d5b4b22010-12-12 20:24:10 +0000696 if (id2 & PCH_ID2_DIR)
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000697 cf->can_id |= CAN_RTR_FLAG;
Tomoya1d5b4b22010-12-12 20:24:10 +0000698
699 cf->can_dlc = get_can_dlc((ioread32(&priv->regs->
700 ifregs[0].mcont)) & 0xF);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000701
Tomoya8ac97022010-12-12 20:24:09 +0000702 for (i = 0; i < cf->can_dlc; i += 2) {
703 data_reg = ioread16(&priv->regs->ifregs[0].data[i / 2]);
704 cf->data[i] = data_reg;
705 cf->data[i + 1] = data_reg >> 8;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000706 }
707
708 netif_receive_skb(skb);
709 rcv_pkts++;
710 stats->rx_packets++;
Tomoya1d5b4b22010-12-12 20:24:10 +0000711 quota--;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000712 stats->rx_bytes += cf->can_dlc;
713
Tomoya1d5b4b22010-12-12 20:24:10 +0000714 pch_fifo_thresh(priv, obj_num);
715 obj_num++;
716 } while (quota > 0);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000717
718 return rcv_pkts;
719}
Tomoyae489cce2010-12-12 20:24:08 +0000720
721static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat)
722{
723 struct pch_can_priv *priv = netdev_priv(ndev);
724 struct net_device_stats *stats = &(priv->ndev->stats);
725 u32 dlc;
726
727 can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1);
728 iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND,
729 &priv->regs->ifregs[1].cmask);
Tomoyabd58cbc2010-12-12 20:24:12 +0000730 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, int_stat);
Tomoyae489cce2010-12-12 20:24:08 +0000731 dlc = get_can_dlc(ioread32(&priv->regs->ifregs[1].mcont) &
732 PCH_IF_MCONT_DLC);
733 stats->tx_bytes += dlc;
734 stats->tx_packets++;
735 if (int_stat == PCH_TX_OBJ_END)
736 netif_wake_queue(ndev);
737}
738
Tomoyabd58cbc2010-12-12 20:24:12 +0000739static int pch_can_poll(struct napi_struct *napi, int quota)
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000740{
741 struct net_device *ndev = napi->dev;
742 struct pch_can_priv *priv = netdev_priv(ndev);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000743 u32 int_stat;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000744 u32 reg_stat;
Tomoya3332bc52010-12-12 20:24:23 +0000745 int quota_save = quota;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000746
747 int_stat = pch_can_int_pending(priv);
748 if (!int_stat)
Tomoyae489cce2010-12-12 20:24:08 +0000749 goto end;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000750
Tomoya8714fca2010-12-12 20:24:18 +0000751 if (int_stat == PCH_STATUS_INT) {
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000752 reg_stat = ioread32(&priv->regs->stat);
Tomoyafea92942010-12-12 20:24:24 +0000753
754 if ((reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) &&
755 ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL)) {
756 pch_can_error(ndev, reg_stat);
757 quota--;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000758 }
759
Tomoyafea92942010-12-12 20:24:24 +0000760 if (reg_stat & (PCH_TX_OK | PCH_RX_OK))
761 pch_can_bit_clear(&priv->regs->stat,
762 reg_stat & (PCH_TX_OK | PCH_RX_OK));
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000763
764 int_stat = pch_can_int_pending(priv);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000765 }
766
Tomoyae489cce2010-12-12 20:24:08 +0000767 if (quota == 0)
768 goto end;
769
Tomoya15ffc8f2010-11-29 18:15:02 +0000770 if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) {
Tomoya3332bc52010-12-12 20:24:23 +0000771 quota -= pch_can_rx_normal(ndev, int_stat, quota);
Tomoya15ffc8f2010-11-29 18:15:02 +0000772 } else if ((int_stat >= PCH_TX_OBJ_START) &&
773 (int_stat <= PCH_TX_OBJ_END)) {
774 /* Handle transmission interrupt */
Tomoyae489cce2010-12-12 20:24:08 +0000775 pch_can_tx_complete(ndev, int_stat);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000776 }
777
Tomoyae489cce2010-12-12 20:24:08 +0000778end:
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000779 napi_complete(napi);
780 pch_can_set_int_enables(priv, PCH_CAN_ALL);
781
Tomoya3332bc52010-12-12 20:24:23 +0000782 return quota_save - quota;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000783}
784
785static int pch_set_bittiming(struct net_device *ndev)
786{
787 struct pch_can_priv *priv = netdev_priv(ndev);
788 const struct can_bittiming *bt = &priv->can.bittiming;
789 u32 canbit;
790 u32 bepe;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000791
792 /* Setting the CCE bit for accessing the Can Timing register. */
Tomoya086b5652010-11-17 01:13:16 +0000793 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000794
Tomoya0e0805c2010-12-12 20:24:19 +0000795 canbit = (bt->brp - 1) & PCH_MSK_BITT_BRP;
Tomoyabd58cbc2010-12-12 20:24:12 +0000796 canbit |= (bt->sjw - 1) << PCH_BIT_SJW_SHIFT;
797 canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1_SHIFT;
798 canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2_SHIFT;
Tomoya0e0805c2010-12-12 20:24:19 +0000799 bepe = ((bt->brp - 1) & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE_SHIFT;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000800 iowrite32(canbit, &priv->regs->bitt);
801 iowrite32(bepe, &priv->regs->brpe);
Tomoya086b5652010-11-17 01:13:16 +0000802 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000803
804 return 0;
805}
806
807static void pch_can_start(struct net_device *ndev)
808{
809 struct pch_can_priv *priv = netdev_priv(ndev);
810
811 if (priv->can.state != CAN_STATE_STOPPED)
812 pch_can_reset(priv);
813
814 pch_set_bittiming(ndev);
815 pch_can_set_optmode(priv);
816
Tomoya8339a7e2010-11-29 18:11:52 +0000817 pch_can_set_tx_all(priv, 1);
818 pch_can_set_rx_all(priv, 1);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000819
820 /* Setting the CAN to run mode. */
821 pch_can_set_run_mode(priv, PCH_CAN_RUN);
822
823 priv->can.state = CAN_STATE_ERROR_ACTIVE;
824
825 return;
826}
827
828static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode)
829{
830 int ret = 0;
831
832 switch (mode) {
833 case CAN_MODE_START:
834 pch_can_start(ndev);
835 netif_wake_queue(ndev);
836 break;
837 default:
838 ret = -EOPNOTSUPP;
839 break;
840 }
841
842 return ret;
843}
844
845static int pch_can_open(struct net_device *ndev)
846{
847 struct pch_can_priv *priv = netdev_priv(ndev);
848 int retval;
849
Tomoyac7551452010-12-12 20:24:21 +0000850 /* Regstering the interrupt. */
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000851 retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED,
852 ndev->name, ndev);
853 if (retval) {
Tomoya435b4ef2010-12-12 20:24:16 +0000854 netdev_err(ndev, "request_irq failed.\n");
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000855 goto req_irq_err;
856 }
857
858 /* Open common can device */
859 retval = open_candev(ndev);
860 if (retval) {
Tomoya435b4ef2010-12-12 20:24:16 +0000861 netdev_err(ndev, "open_candev() failed %d\n", retval);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000862 goto err_open_candev;
863 }
864
865 pch_can_init(priv);
866 pch_can_start(ndev);
867 napi_enable(&priv->napi);
868 netif_start_queue(ndev);
869
870 return 0;
871
872err_open_candev:
873 free_irq(priv->dev->irq, ndev);
874req_irq_err:
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000875 pch_can_release(priv);
876
877 return retval;
878}
879
880static int pch_close(struct net_device *ndev)
881{
882 struct pch_can_priv *priv = netdev_priv(ndev);
883
884 netif_stop_queue(ndev);
885 napi_disable(&priv->napi);
886 pch_can_release(priv);
887 free_irq(priv->dev->irq, ndev);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000888 close_candev(ndev);
889 priv->can.state = CAN_STATE_STOPPED;
890 return 0;
891}
892
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000893static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
894{
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000895 struct pch_can_priv *priv = netdev_priv(ndev);
896 struct can_frame *cf = (struct can_frame *)skb->data;
Tomoyabd58cbc2010-12-12 20:24:12 +0000897 int tx_obj_no;
Tomoya8ac97022010-12-12 20:24:09 +0000898 int i;
Tomoya44c9aa82010-12-12 20:24:14 +0000899 u32 id2;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000900
901 if (can_dropped_invalid_skb(ndev, skb))
902 return NETDEV_TX_OK;
903
Tomoyafea92942010-12-12 20:24:24 +0000904 tx_obj_no = priv->tx_obj;
Tomoya76d94b22010-12-12 20:24:07 +0000905 if (priv->tx_obj == PCH_TX_OBJ_END) {
906 if (ioread32(&priv->regs->treq2) & PCH_TREQ2_TX_MASK)
907 netif_stop_queue(ndev);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000908
Tomoya76d94b22010-12-12 20:24:07 +0000909 priv->tx_obj = PCH_TX_OBJ_START;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000910 } else {
Tomoya76d94b22010-12-12 20:24:07 +0000911 priv->tx_obj++;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000912 }
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000913
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000914 /* Setting the CMASK register. */
Tomoya8339a7e2010-11-29 18:11:52 +0000915 pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000916
917 /* If ID extended is set. */
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000918 if (cf->can_id & CAN_EFF_FLAG) {
Tomoya44c9aa82010-12-12 20:24:14 +0000919 iowrite32(cf->can_id & 0xffff, &priv->regs->ifregs[1].id1);
920 id2 = ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000921 } else {
Tomoya44c9aa82010-12-12 20:24:14 +0000922 iowrite32(0, &priv->regs->ifregs[1].id1);
923 id2 = (cf->can_id & CAN_SFF_MASK) << 2;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000924 }
925
Tomoya44c9aa82010-12-12 20:24:14 +0000926 id2 |= PCH_ID_MSGVAL;
927
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000928 /* If remote frame has to be transmitted.. */
Tomoyafea92942010-12-12 20:24:24 +0000929 if (!(cf->can_id & CAN_RTR_FLAG))
Tomoya44c9aa82010-12-12 20:24:14 +0000930 id2 |= PCH_ID2_DIR;
931
932 iowrite32(id2, &priv->regs->ifregs[1].id2);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000933
Tomoya8ac97022010-12-12 20:24:09 +0000934 /* Copy data to register */
935 for (i = 0; i < cf->can_dlc; i += 2) {
936 iowrite16(cf->data[i] | (cf->data[i + 1] << 8),
937 &priv->regs->ifregs[1].data[i / 2]);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000938 }
939
Tomoyabd58cbc2010-12-12 20:24:12 +0000940 can_put_echo_skb(skb, ndev, tx_obj_no - PCH_RX_OBJ_END - 1);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000941
Tomoyac7551452010-12-12 20:24:21 +0000942 /* Set the size of the data. Update if2_mcont */
Tomoya44c9aa82010-12-12 20:24:14 +0000943 iowrite32(cf->can_dlc | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT |
944 PCH_IF_MCONT_TXIE, &priv->regs->ifregs[1].mcont);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000945
Tomoyabd58cbc2010-12-12 20:24:12 +0000946 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000947
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000948 return NETDEV_TX_OK;
949}
950
951static const struct net_device_ops pch_can_netdev_ops = {
952 .ndo_open = pch_can_open,
953 .ndo_stop = pch_close,
954 .ndo_start_xmit = pch_xmit,
955};
956
957static void __devexit pch_can_remove(struct pci_dev *pdev)
958{
959 struct net_device *ndev = pci_get_drvdata(pdev);
960 struct pch_can_priv *priv = netdev_priv(ndev);
961
962 unregister_candev(priv->ndev);
Tomoyaa6f6d6b2010-12-12 20:24:22 +0000963 if (priv->use_msi)
964 pci_disable_msi(priv->dev);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000965 pci_release_regions(pdev);
966 pci_disable_device(pdev);
967 pci_set_drvdata(pdev, NULL);
968 pch_can_reset(priv);
Tomoyace9736d2011-02-07 23:29:02 +0000969 pci_iounmap(pdev, priv->regs);
Tomoyaa6f6d6b2010-12-12 20:24:22 +0000970 free_candev(priv->ndev);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +0000971}
972
973#ifdef CONFIG_PM
Tomoya7f2bc502010-12-12 20:24:11 +0000974static void pch_can_set_int_custom(struct pch_can_priv *priv)
975{
976 /* Clearing the IE, SIE and EIE bits of Can control register. */
977 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
978
979 /* Appropriately setting them. */
980 pch_can_bit_set(&priv->regs->cont,
981 ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1));
982}
983
984/* This function retrieves interrupt enabled for the CAN device. */
Tomoyaca2b0042010-12-12 20:24:13 +0000985static u32 pch_can_get_int_enables(struct pch_can_priv *priv)
Tomoya7f2bc502010-12-12 20:24:11 +0000986{
987 /* Obtaining the status of IE, SIE and EIE interrupt bits. */
Tomoyaca2b0042010-12-12 20:24:13 +0000988 return (ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1;
Tomoya7f2bc502010-12-12 20:24:11 +0000989}
990
991static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num,
992 enum pch_ifreg dir)
993{
994 u32 ie, enable;
995
996 if (dir)
997 ie = PCH_IF_MCONT_RXIE;
998 else
999 ie = PCH_IF_MCONT_TXIE;
1000
1001 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
Tomoyabd58cbc2010-12-12 20:24:12 +00001002 pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
Tomoya7f2bc502010-12-12 20:24:11 +00001003
1004 if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) &&
Tomoya9388b162010-12-12 20:24:17 +00001005 ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie))
Tomoya7f2bc502010-12-12 20:24:11 +00001006 enable = 1;
Tomoya9388b162010-12-12 20:24:17 +00001007 else
Tomoya7f2bc502010-12-12 20:24:11 +00001008 enable = 0;
Tomoya9388b162010-12-12 20:24:17 +00001009
Tomoya7f2bc502010-12-12 20:24:11 +00001010 return enable;
1011}
1012
1013static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
Tomoyabd58cbc2010-12-12 20:24:12 +00001014 u32 buffer_num, int set)
Tomoya7f2bc502010-12-12 20:24:11 +00001015{
1016 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
Tomoyabd58cbc2010-12-12 20:24:12 +00001017 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
Tomoya7f2bc502010-12-12 20:24:11 +00001018 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
1019 &priv->regs->ifregs[0].cmask);
Tomoyabd58cbc2010-12-12 20:24:12 +00001020 if (set)
Tomoya7f2bc502010-12-12 20:24:11 +00001021 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
1022 PCH_IF_MCONT_EOB);
1023 else
1024 pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB);
1025
Tomoyabd58cbc2010-12-12 20:24:12 +00001026 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
Tomoya7f2bc502010-12-12 20:24:11 +00001027}
1028
Tomoyaca2b0042010-12-12 20:24:13 +00001029static u32 pch_can_get_rx_buffer_link(struct pch_can_priv *priv, u32 buffer_num)
Tomoya7f2bc502010-12-12 20:24:11 +00001030{
Tomoyaca2b0042010-12-12 20:24:13 +00001031 u32 link;
1032
Tomoya7f2bc502010-12-12 20:24:11 +00001033 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
Tomoyabd58cbc2010-12-12 20:24:12 +00001034 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
Tomoya7f2bc502010-12-12 20:24:11 +00001035
1036 if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB)
Tomoyaca2b0042010-12-12 20:24:13 +00001037 link = 0;
Tomoya7f2bc502010-12-12 20:24:11 +00001038 else
Tomoyaca2b0042010-12-12 20:24:13 +00001039 link = 1;
1040 return link;
Tomoya7f2bc502010-12-12 20:24:11 +00001041}
1042
1043static int pch_can_get_buffer_status(struct pch_can_priv *priv)
1044{
1045 return (ioread32(&priv->regs->treq1) & 0xffff) |
Tomoyabd58cbc2010-12-12 20:24:12 +00001046 (ioread32(&priv->regs->treq2) << 16);
Tomoya7f2bc502010-12-12 20:24:11 +00001047}
1048
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001049static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
1050{
Tomoyac7551452010-12-12 20:24:21 +00001051 int i;
1052 int retval;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001053 u32 buf_stat; /* Variable for reading the transmit buffer status. */
Tomoyabd58cbc2010-12-12 20:24:12 +00001054 int counter = PCH_COUNTER_LIMIT;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001055
1056 struct net_device *dev = pci_get_drvdata(pdev);
1057 struct pch_can_priv *priv = netdev_priv(dev);
1058
1059 /* Stop the CAN controller */
1060 pch_can_set_run_mode(priv, PCH_CAN_STOP);
1061
1062 /* Indicate that we are aboutto/in suspend */
Tomoyad06848b2010-12-12 20:24:20 +00001063 priv->can.state = CAN_STATE_STOPPED;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001064
1065 /* Waiting for all transmission to complete. */
1066 while (counter) {
1067 buf_stat = pch_can_get_buffer_status(priv);
1068 if (!buf_stat)
1069 break;
1070 counter--;
1071 udelay(1);
1072 }
1073 if (!counter)
1074 dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__);
1075
1076 /* Save interrupt configuration and then disable them */
Tomoyaca2b0042010-12-12 20:24:13 +00001077 priv->int_enables = pch_can_get_int_enables(priv);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001078 pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1079
1080 /* Save Tx buffer enable state */
Tomoya15ffc8f2010-11-29 18:15:02 +00001081 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
Tomoyaf622691c2010-12-22 03:00:39 +00001082 priv->tx_enable[i - 1] = pch_can_get_rxtx_ir(priv, i,
1083 PCH_TX_IFREG);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001084
1085 /* Disable all Transmit buffers */
Tomoya8339a7e2010-11-29 18:11:52 +00001086 pch_can_set_tx_all(priv, 0);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001087
1088 /* Save Rx buffer enable state */
Tomoya15ffc8f2010-11-29 18:15:02 +00001089 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
Tomoyaf622691c2010-12-22 03:00:39 +00001090 priv->rx_enable[i - 1] = pch_can_get_rxtx_ir(priv, i,
1091 PCH_RX_IFREG);
1092 priv->rx_link[i - 1] = pch_can_get_rx_buffer_link(priv, i);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001093 }
1094
1095 /* Disable all Receive buffers */
Tomoya8339a7e2010-11-29 18:11:52 +00001096 pch_can_set_rx_all(priv, 0);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001097 retval = pci_save_state(pdev);
1098 if (retval) {
1099 dev_err(&pdev->dev, "pci_save_state failed.\n");
1100 } else {
1101 pci_enable_wake(pdev, PCI_D3hot, 0);
1102 pci_disable_device(pdev);
1103 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1104 }
1105
1106 return retval;
1107}
1108
1109static int pch_can_resume(struct pci_dev *pdev)
1110{
Tomoyac7551452010-12-12 20:24:21 +00001111 int i;
1112 int retval;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001113 struct net_device *dev = pci_get_drvdata(pdev);
1114 struct pch_can_priv *priv = netdev_priv(dev);
1115
1116 pci_set_power_state(pdev, PCI_D0);
1117 pci_restore_state(pdev);
1118 retval = pci_enable_device(pdev);
1119 if (retval) {
1120 dev_err(&pdev->dev, "pci_enable_device failed.\n");
1121 return retval;
1122 }
1123
1124 pci_enable_wake(pdev, PCI_D3hot, 0);
1125
1126 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1127
1128 /* Disabling all interrupts. */
1129 pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1130
1131 /* Setting the CAN device in Stop Mode. */
1132 pch_can_set_run_mode(priv, PCH_CAN_STOP);
1133
1134 /* Configuring the transmit and receive buffers. */
1135 pch_can_config_rx_tx_buffers(priv);
1136
1137 /* Restore the CAN state */
1138 pch_set_bittiming(dev);
1139
1140 /* Listen/Active */
1141 pch_can_set_optmode(priv);
1142
1143 /* Enabling the transmit buffer. */
Tomoya15ffc8f2010-11-29 18:15:02 +00001144 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
Tomoyaf622691c2010-12-22 03:00:39 +00001145 pch_can_set_rxtx(priv, i, priv->tx_enable[i - 1], PCH_TX_IFREG);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001146
1147 /* Configuring the receive buffer and enabling them. */
Tomoya15ffc8f2010-11-29 18:15:02 +00001148 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
1149 /* Restore buffer link */
Tomoyaf622691c2010-12-22 03:00:39 +00001150 pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i - 1]);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001151
Tomoya15ffc8f2010-11-29 18:15:02 +00001152 /* Restore buffer enables */
Tomoyaf622691c2010-12-22 03:00:39 +00001153 pch_can_set_rxtx(priv, i, priv->rx_enable[i - 1], PCH_RX_IFREG);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001154 }
1155
1156 /* Enable CAN Interrupts */
1157 pch_can_set_int_custom(priv);
1158
1159 /* Restore Run Mode */
1160 pch_can_set_run_mode(priv, PCH_CAN_RUN);
1161
1162 return retval;
1163}
1164#else
1165#define pch_can_suspend NULL
1166#define pch_can_resume NULL
1167#endif
1168
1169static int pch_can_get_berr_counter(const struct net_device *dev,
1170 struct can_berr_counter *bec)
1171{
1172 struct pch_can_priv *priv = netdev_priv(dev);
Tomoya44c9aa82010-12-12 20:24:14 +00001173 u32 errc = ioread32(&priv->regs->errc);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001174
Tomoya44c9aa82010-12-12 20:24:14 +00001175 bec->txerr = errc & PCH_TEC;
1176 bec->rxerr = (errc & PCH_REC) >> 8;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001177
1178 return 0;
1179}
1180
1181static int __devinit pch_can_probe(struct pci_dev *pdev,
1182 const struct pci_device_id *id)
1183{
1184 struct net_device *ndev;
1185 struct pch_can_priv *priv;
1186 int rc;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001187 void __iomem *addr;
1188
1189 rc = pci_enable_device(pdev);
1190 if (rc) {
1191 dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc);
1192 goto probe_exit_endev;
1193 }
1194
1195 rc = pci_request_regions(pdev, KBUILD_MODNAME);
1196 if (rc) {
1197 dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc);
1198 goto probe_exit_pcireq;
1199 }
1200
1201 addr = pci_iomap(pdev, 1, 0);
1202 if (!addr) {
1203 rc = -EIO;
1204 dev_err(&pdev->dev, "Failed pci_iomap\n");
1205 goto probe_exit_ipmap;
1206 }
1207
Tomoya15ffc8f2010-11-29 18:15:02 +00001208 ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_END);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001209 if (!ndev) {
1210 rc = -ENOMEM;
1211 dev_err(&pdev->dev, "Failed alloc_candev\n");
1212 goto probe_exit_alloc_candev;
1213 }
1214
1215 priv = netdev_priv(ndev);
1216 priv->ndev = ndev;
1217 priv->regs = addr;
1218 priv->dev = pdev;
1219 priv->can.bittiming_const = &pch_can_bittiming_const;
1220 priv->can.do_set_mode = pch_can_do_set_mode;
1221 priv->can.do_get_berr_counter = pch_can_get_berr_counter;
1222 priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
1223 CAN_CTRLMODE_LOOPBACK;
Tomoya15ffc8f2010-11-29 18:15:02 +00001224 priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj */
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001225
1226 ndev->irq = pdev->irq;
1227 ndev->flags |= IFF_ECHO;
1228
1229 pci_set_drvdata(pdev, ndev);
1230 SET_NETDEV_DEV(ndev, &pdev->dev);
1231 ndev->netdev_ops = &pch_can_netdev_ops;
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001232 priv->can.clock.freq = PCH_CAN_CLK; /* Hz */
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001233
Tomoyabd58cbc2010-12-12 20:24:12 +00001234 netif_napi_add(ndev, &priv->napi, pch_can_poll, PCH_RX_OBJ_END);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001235
Tomoyaa6f6d6b2010-12-12 20:24:22 +00001236 rc = pci_enable_msi(priv->dev);
1237 if (rc) {
1238 netdev_err(ndev, "PCH CAN opened without MSI\n");
1239 priv->use_msi = 0;
1240 } else {
1241 netdev_err(ndev, "PCH CAN opened with MSI\n");
Tomoyac69b9092011-02-07 23:29:03 +00001242 pci_set_master(pdev);
Tomoyaa6f6d6b2010-12-12 20:24:22 +00001243 priv->use_msi = 1;
1244 }
1245
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001246 rc = register_candev(ndev);
1247 if (rc) {
1248 dev_err(&pdev->dev, "Failed register_candev %d\n", rc);
1249 goto probe_exit_reg_candev;
1250 }
1251
1252 return 0;
1253
1254probe_exit_reg_candev:
Tomoyaa6f6d6b2010-12-12 20:24:22 +00001255 if (priv->use_msi)
1256 pci_disable_msi(priv->dev);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001257 free_candev(ndev);
1258probe_exit_alloc_candev:
1259 pci_iounmap(pdev, addr);
1260probe_exit_ipmap:
1261 pci_release_regions(pdev);
1262probe_exit_pcireq:
1263 pci_disable_device(pdev);
1264probe_exit_endev:
1265 return rc;
1266}
1267
Marc Kleine-Buddebdfa3d82010-10-30 16:28:16 -07001268static struct pci_driver pch_can_pci_driver = {
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001269 .name = "pch_can",
1270 .id_table = pch_pci_tbl,
1271 .probe = pch_can_probe,
1272 .remove = __devexit_p(pch_can_remove),
1273 .suspend = pch_can_suspend,
1274 .resume = pch_can_resume,
1275};
1276
1277static int __init pch_can_pci_init(void)
1278{
Marc Kleine-Buddebdfa3d82010-10-30 16:28:16 -07001279 return pci_register_driver(&pch_can_pci_driver);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001280}
1281module_init(pch_can_pci_init);
1282
1283static void __exit pch_can_pci_exit(void)
1284{
Marc Kleine-Buddebdfa3d82010-10-30 16:28:16 -07001285 pci_unregister_driver(&pch_can_pci_driver);
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001286}
1287module_exit(pch_can_pci_exit);
1288
Tomoyae91530e2010-12-12 20:24:15 +00001289MODULE_DESCRIPTION("Intel EG20T PCH CAN(Controller Area Network) Driver");
Masayuki Ohtakeb21d18b2010-10-15 03:00:28 +00001290MODULE_LICENSE("GPL v2");
1291MODULE_VERSION("0.94");