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Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
11 *
12 *
13 * TODO
14 * Maybe PLL mode
15 * Look into engine reset on timeout errors. Should not be
16 * required.
17 */
18
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/init.h>
24#include <linux/blkdev.h>
25#include <linux/delay.h>
26#include <scsi/scsi_host.h>
27#include <linux/libata.h>
28
29#define DRV_NAME "pata_hpt366"
Alan Cox6ddd6862008-02-26 13:35:54 -080030#define DRV_VERSION "0.6.2"
Jeff Garzik669a5db2006-08-29 18:12:40 -040031
32struct hpt_clock {
33 u8 xfer_speed;
34 u32 timing;
35};
36
37/* key for bus clock timings
38 * bit
39 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
40 * DMA. cycles = value + 1
41 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
42 * DMA. cycles = value + 1
43 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
44 * register access.
45 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
46 * register access.
47 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
48 * during task file register access.
49 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
50 * xfer.
51 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
52 * register access.
53 * 28 UDMA enable
54 * 29 DMA enable
55 * 30 PIO_MST enable. if set, the chip is in bus master mode during
56 * PIO.
57 * 31 FIFO enable.
58 */
59
60static const struct hpt_clock hpt366_40[] = {
61 { XFER_UDMA_4, 0x900fd943 },
62 { XFER_UDMA_3, 0x900ad943 },
63 { XFER_UDMA_2, 0x900bd943 },
64 { XFER_UDMA_1, 0x9008d943 },
65 { XFER_UDMA_0, 0x9008d943 },
66
67 { XFER_MW_DMA_2, 0xa008d943 },
68 { XFER_MW_DMA_1, 0xa010d955 },
69 { XFER_MW_DMA_0, 0xa010d9fc },
70
71 { XFER_PIO_4, 0xc008d963 },
72 { XFER_PIO_3, 0xc010d974 },
73 { XFER_PIO_2, 0xc010d997 },
74 { XFER_PIO_1, 0xc010d9c7 },
75 { XFER_PIO_0, 0xc018d9d9 },
76 { 0, 0x0120d9d9 }
77};
78
79static const struct hpt_clock hpt366_33[] = {
80 { XFER_UDMA_4, 0x90c9a731 },
81 { XFER_UDMA_3, 0x90cfa731 },
82 { XFER_UDMA_2, 0x90caa731 },
83 { XFER_UDMA_1, 0x90cba731 },
84 { XFER_UDMA_0, 0x90c8a731 },
85
86 { XFER_MW_DMA_2, 0xa0c8a731 },
87 { XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
88 { XFER_MW_DMA_0, 0xa0c8a797 },
89
90 { XFER_PIO_4, 0xc0c8a731 },
91 { XFER_PIO_3, 0xc0c8a742 },
92 { XFER_PIO_2, 0xc0d0a753 },
93 { XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
94 { XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
95 { 0, 0x0120a7a7 }
96};
97
98static const struct hpt_clock hpt366_25[] = {
99 { XFER_UDMA_4, 0x90c98521 },
100 { XFER_UDMA_3, 0x90cf8521 },
101 { XFER_UDMA_2, 0x90cf8521 },
102 { XFER_UDMA_1, 0x90cb8521 },
103 { XFER_UDMA_0, 0x90cb8521 },
104
105 { XFER_MW_DMA_2, 0xa0ca8521 },
106 { XFER_MW_DMA_1, 0xa0ca8532 },
107 { XFER_MW_DMA_0, 0xa0ca8575 },
108
109 { XFER_PIO_4, 0xc0ca8521 },
110 { XFER_PIO_3, 0xc0ca8532 },
111 { XFER_PIO_2, 0xc0ca8542 },
112 { XFER_PIO_1, 0xc0d08572 },
113 { XFER_PIO_0, 0xc0d08585 },
114 { 0, 0x01208585 }
115};
116
117static const char *bad_ata33[] = {
118 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
119 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
120 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
121 "Maxtor 90510D4",
122 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
123 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
124 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
125 NULL
126};
127
128static const char *bad_ata66_4[] = {
129 "IBM-DTLA-307075",
130 "IBM-DTLA-307060",
131 "IBM-DTLA-307045",
132 "IBM-DTLA-307030",
133 "IBM-DTLA-307020",
134 "IBM-DTLA-307015",
135 "IBM-DTLA-305040",
136 "IBM-DTLA-305030",
137 "IBM-DTLA-305020",
138 "IC35L010AVER07-0",
139 "IC35L020AVER07-0",
140 "IC35L030AVER07-0",
141 "IC35L040AVER07-0",
142 "IC35L060AVER07-0",
143 "WDC AC310200R",
144 NULL
145};
146
147static const char *bad_ata66_3[] = {
148 "WDC AC310200R",
149 NULL
150};
151
152static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
153{
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900154 unsigned char model_num[ATA_ID_PROD_LEN + 1];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400155 int i = 0;
156
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900157 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400158
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900159 while (list[i] != NULL) {
160 if (!strcmp(list[i], model_num)) {
Jeff Garzik85cd7252006-08-31 00:03:49 -0400161 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
Jeff Garzik669a5db2006-08-29 18:12:40 -0400162 modestr, list[i]);
163 return 1;
164 }
165 i++;
166 }
167 return 0;
168}
169
170/**
171 * hpt366_filter - mode selection filter
Jeff Garzik669a5db2006-08-29 18:12:40 -0400172 * @adev: ATA device
173 *
174 * Block UDMA on devices that cause trouble with this controller.
175 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400176
Alan Coxa76b62c2007-03-09 09:34:07 -0500177static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400178{
179 if (adev->class == ATA_DEV_ATA) {
180 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
181 mask &= ~ATA_MASK_UDMA;
182 if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
Alan Cox6ddd6862008-02-26 13:35:54 -0800183 mask &= ~(0xF8 << ATA_SHIFT_UDMA);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400184 if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
Alan Cox6ddd6862008-02-26 13:35:54 -0800185 mask &= ~(0xF0 << ATA_SHIFT_UDMA);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400186 }
Tejun Heo9363c382008-04-07 22:47:16 +0900187 return ata_bmdma_mode_filter(adev, mask);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400188}
189
190/**
191 * hpt36x_find_mode - reset the hpt36x bus
192 * @ap: ATA port
193 * @speed: transfer mode
194 *
195 * Return the 32bit register programming information for this channel
196 * that matches the speed provided.
197 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400198
Jeff Garzik669a5db2006-08-29 18:12:40 -0400199static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
200{
201 struct hpt_clock *clocks = ap->host->private_data;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400202
Jeff Garzik669a5db2006-08-29 18:12:40 -0400203 while(clocks->xfer_speed) {
204 if (clocks->xfer_speed == speed)
205 return clocks->timing;
206 clocks++;
207 }
208 BUG();
209 return 0xffffffffU; /* silence compiler warning */
210}
Jeff Garzik85cd7252006-08-31 00:03:49 -0400211
Alan Coxfecfda52007-03-08 19:34:28 +0000212static int hpt36x_cable_detect(struct ata_port *ap)
213{
214 u8 ata66;
215 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
216
217 pci_read_config_byte(pdev, 0x5A, &ata66);
218 if (ata66 & (1 << ap->port_no))
219 return ATA_CBL_PATA40;
220 return ATA_CBL_PATA80;
221}
222
Jeff Garzik669a5db2006-08-29 18:12:40 -0400223/**
224 * hpt366_set_piomode - PIO setup
225 * @ap: ATA interface
226 * @adev: device on the interface
227 *
Jeff Garzik85cd7252006-08-31 00:03:49 -0400228 * Perform PIO mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400229 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400230
Jeff Garzik669a5db2006-08-29 18:12:40 -0400231static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
232{
233 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
234 u32 addr1, addr2;
235 u32 reg;
236 u32 mode;
237 u8 fast;
238
239 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
240 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400241
Jeff Garzik669a5db2006-08-29 18:12:40 -0400242 /* Fast interrupt prediction disable, hold off interrupt disable */
243 pci_read_config_byte(pdev, addr2, &fast);
244 if (fast & 0x80) {
245 fast &= ~0x80;
246 pci_write_config_byte(pdev, addr2, fast);
247 }
Jeff Garzik85cd7252006-08-31 00:03:49 -0400248
Jeff Garzik669a5db2006-08-29 18:12:40 -0400249 pci_read_config_dword(pdev, addr1, &reg);
250 mode = hpt36x_find_mode(ap, adev->pio_mode);
251 mode &= ~0x8000000; /* No FIFO in PIO */
252 mode &= ~0x30070000; /* Leave config bits alone */
253 reg &= 0x30070000; /* Strip timing bits */
254 pci_write_config_dword(pdev, addr1, reg | mode);
255}
256
257/**
258 * hpt366_set_dmamode - DMA timing setup
259 * @ap: ATA interface
260 * @adev: Device being configured
261 *
262 * Set up the channel for MWDMA or UDMA modes. Much the same as with
263 * PIO, load the mode number and then set MWDMA or UDMA flag.
264 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400265
Jeff Garzik669a5db2006-08-29 18:12:40 -0400266static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
267{
268 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
269 u32 addr1, addr2;
270 u32 reg;
271 u32 mode;
272 u8 fast;
273
274 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
275 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400276
Jeff Garzik669a5db2006-08-29 18:12:40 -0400277 /* Fast interrupt prediction disable, hold off interrupt disable */
278 pci_read_config_byte(pdev, addr2, &fast);
279 if (fast & 0x80) {
280 fast &= ~0x80;
281 pci_write_config_byte(pdev, addr2, fast);
282 }
Jeff Garzik85cd7252006-08-31 00:03:49 -0400283
Jeff Garzik669a5db2006-08-29 18:12:40 -0400284 pci_read_config_dword(pdev, addr1, &reg);
285 mode = hpt36x_find_mode(ap, adev->dma_mode);
286 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
287 mode &= ~0xC0000000; /* Leave config bits alone */
288 reg &= 0xC0000000; /* Strip timing bits */
289 pci_write_config_dword(pdev, addr1, reg | mode);
290}
291
292static struct scsi_host_template hpt36x_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900293 ATA_BMDMA_SHT(DRV_NAME),
Jeff Garzik669a5db2006-08-29 18:12:40 -0400294};
295
296/*
297 * Configuration for HPT366/68
298 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400299
Jeff Garzik669a5db2006-08-29 18:12:40 -0400300static struct ata_port_operations hpt366_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900301 .inherits = &ata_bmdma_port_ops,
302 .cable_detect = hpt36x_cable_detect,
303 .mode_filter = hpt366_filter,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400304 .set_piomode = hpt366_set_piomode,
305 .set_dmamode = hpt366_set_dmamode,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400306};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400307
308/**
Alanaa54ab12006-11-27 16:24:15 +0000309 * hpt36x_init_chipset - common chip setup
310 * @dev: PCI device
311 *
312 * Perform the chip setup work that must be done at both init and
313 * resume time
314 */
315
316static void hpt36x_init_chipset(struct pci_dev *dev)
317{
318 u8 drive_fast;
319 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
320 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
321 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
322 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
323
324 pci_read_config_byte(dev, 0x51, &drive_fast);
325 if (drive_fast & 0x80)
326 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
327}
328
329/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400330 * hpt36x_init_one - Initialise an HPT366/368
331 * @dev: PCI device
332 * @id: Entry in match table
333 *
334 * Initialise an HPT36x device. There are some interesting complications
335 * here. Firstly the chip may report 366 and be one of several variants.
336 * Secondly all the timings depend on the clock for the chip which we must
337 * detect and look up
338 *
339 * This is the known chip mappings. It may be missing a couple of later
340 * releases.
341 *
342 * Chip version PCI Rev Notes
343 * HPT366 4 (HPT366) 0 UDMA66
344 * HPT366 4 (HPT366) 1 UDMA66
345 * HPT368 4 (HPT366) 2 UDMA66
346 * HPT37x/30x 4 (HPT366) 3+ Other driver
347 *
348 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400349
Jeff Garzik669a5db2006-08-29 18:12:40 -0400350static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
351{
Tejun Heo1626aeb2007-05-04 12:43:58 +0200352 static const struct ata_port_info info_hpt366 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400353 .flags = ATA_FLAG_SLAVE_POSS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400354 .pio_mask = 0x1f,
355 .mwdma_mask = 0x07,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400356 .udma_mask = ATA_UDMA4,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400357 .port_ops = &hpt366_port_ops
358 };
Tejun Heo887125e2008-03-25 12:22:49 +0900359 const struct ata_port_info *ppi[] = { &info_hpt366, NULL };
Jeff Garzik669a5db2006-08-29 18:12:40 -0400360
Tejun Heo887125e2008-03-25 12:22:49 +0900361 void *hpriv = NULL;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400362 u32 class_rev;
363 u32 reg1;
Tejun Heof08048e2008-03-25 12:22:47 +0900364 int rc;
365
366 rc = pcim_enable_device(dev);
367 if (rc)
368 return rc;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400369
370 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
371 class_rev &= 0xFF;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400372
Jeff Garzik669a5db2006-08-29 18:12:40 -0400373 /* May be a later chip in disguise. Check */
374 /* Newer chips are not in the HPT36x driver. Ignore them */
375 if (class_rev > 2)
376 return -ENODEV;
377
Alanaa54ab12006-11-27 16:24:15 +0000378 hpt36x_init_chipset(dev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400379
380 pci_read_config_dword(dev, 0x40, &reg1);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400381
Jeff Garzik669a5db2006-08-29 18:12:40 -0400382 /* PCI clocking determines the ATA timing values to use */
383 /* info_hpt366 is safe against re-entry so we can scribble on it */
OGAWA Hirofumi2c136ef2006-10-03 01:14:03 -0700384 switch((reg1 & 0x700) >> 8) {
Tejun Heo2456eb82008-12-08 18:48:42 +0900385 case 9:
Tejun Heo887125e2008-03-25 12:22:49 +0900386 hpriv = &hpt366_40;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400387 break;
Tejun Heo2456eb82008-12-08 18:48:42 +0900388 case 5:
Tejun Heo887125e2008-03-25 12:22:49 +0900389 hpriv = &hpt366_25;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400390 break;
391 default:
Tejun Heo887125e2008-03-25 12:22:49 +0900392 hpriv = &hpt366_33;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400393 break;
394 }
395 /* Now kick off ATA set up */
Tejun Heo9363c382008-04-07 22:47:16 +0900396 return ata_pci_sff_init_one(dev, ppi, &hpt36x_sht, hpriv);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400397}
398
Tejun Heo438ac6d2007-03-02 17:31:26 +0900399#ifdef CONFIG_PM
Alanaa54ab12006-11-27 16:24:15 +0000400static int hpt36x_reinit_one(struct pci_dev *dev)
401{
Tejun Heof08048e2008-03-25 12:22:47 +0900402 struct ata_host *host = dev_get_drvdata(&dev->dev);
403 int rc;
404
405 rc = ata_pci_device_do_resume(dev);
406 if (rc)
407 return rc;
Alanaa54ab12006-11-27 16:24:15 +0000408 hpt36x_init_chipset(dev);
Tejun Heof08048e2008-03-25 12:22:47 +0900409 ata_host_resume(host);
410 return 0;
Alanaa54ab12006-11-27 16:24:15 +0000411}
Tejun Heo438ac6d2007-03-02 17:31:26 +0900412#endif
Alanaa54ab12006-11-27 16:24:15 +0000413
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400414static const struct pci_device_id hpt36x[] = {
415 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400416 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400417};
418
419static struct pci_driver hpt36x_pci_driver = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400420 .name = DRV_NAME,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400421 .id_table = hpt36x,
422 .probe = hpt36x_init_one,
Alanaa54ab12006-11-27 16:24:15 +0000423 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900424#ifdef CONFIG_PM
Alanaa54ab12006-11-27 16:24:15 +0000425 .suspend = ata_pci_device_suspend,
426 .resume = hpt36x_reinit_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900427#endif
Jeff Garzik669a5db2006-08-29 18:12:40 -0400428};
429
430static int __init hpt36x_init(void)
431{
432 return pci_register_driver(&hpt36x_pci_driver);
433}
434
Jeff Garzik669a5db2006-08-29 18:12:40 -0400435static void __exit hpt36x_exit(void)
436{
437 pci_unregister_driver(&hpt36x_pci_driver);
438}
439
Jeff Garzik669a5db2006-08-29 18:12:40 -0400440MODULE_AUTHOR("Alan Cox");
441MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
442MODULE_LICENSE("GPL");
443MODULE_DEVICE_TABLE(pci, hpt36x);
444MODULE_VERSION(DRV_VERSION);
445
446module_init(hpt36x_init);
447module_exit(hpt36x_exit);