Russell King | 3c4ee4e | 2005-08-10 14:41:45 +0100 | [diff] [blame] | 1 | |
Russell King | 4a5f79e | 2005-11-03 15:48:21 +0000 | [diff] [blame] | 2 | #if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_CPU_32v6K) |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 3 | .macro bitop, instr |
| 4 | mov r2, #1 |
| 5 | and r3, r0, #7 @ Get bit offset |
| 6 | add r1, r1, r0, lsr #3 @ Get byte offset |
| 7 | mov r3, r2, lsl r3 |
| 8 | 1: ldrexb r2, [r1] |
| 9 | \instr r2, r2, r3 |
| 10 | strexb r0, r2, [r1] |
Russell King | e7ec029 | 2005-07-28 20:36:26 +0100 | [diff] [blame] | 11 | cmp r0, #0 |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 12 | bne 1b |
| 13 | mov pc, lr |
| 14 | .endm |
| 15 | |
| 16 | .macro testop, instr, store |
| 17 | and r3, r0, #7 @ Get bit offset |
| 18 | mov r2, #1 |
| 19 | add r1, r1, r0, lsr #3 @ Get byte offset |
| 20 | mov r3, r2, lsl r3 @ create mask |
Russell King | bac4e96 | 2009-05-25 20:58:00 +0100 | [diff] [blame^] | 21 | smp_dmb |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 22 | 1: ldrexb r2, [r1] |
| 23 | ands r0, r2, r3 @ save old value of bit |
Russell King | 614d73e | 2005-07-27 23:00:05 +0100 | [diff] [blame] | 24 | \instr r2, r2, r3 @ toggle bit |
| 25 | strexb ip, r2, [r1] |
| 26 | cmp ip, #0 |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 27 | bne 1b |
Russell King | bac4e96 | 2009-05-25 20:58:00 +0100 | [diff] [blame^] | 28 | smp_dmb |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 29 | cmp r0, #0 |
| 30 | movne r0, #1 |
| 31 | 2: mov pc, lr |
| 32 | .endm |
| 33 | #else |
Russell King | 7a55fd0 | 2005-04-18 22:50:01 +0100 | [diff] [blame] | 34 | .macro bitop, instr |
| 35 | and r2, r0, #7 |
| 36 | mov r3, #1 |
| 37 | mov r3, r3, lsl r2 |
Russell King | 59d1ff3 | 2005-11-09 15:04:22 +0000 | [diff] [blame] | 38 | save_and_disable_irqs ip |
Russell King | 7a55fd0 | 2005-04-18 22:50:01 +0100 | [diff] [blame] | 39 | ldrb r2, [r1, r0, lsr #3] |
| 40 | \instr r2, r2, r3 |
| 41 | strb r2, [r1, r0, lsr #3] |
| 42 | restore_irqs ip |
| 43 | mov pc, lr |
| 44 | .endm |
| 45 | |
| 46 | /** |
| 47 | * testop - implement a test_and_xxx_bit operation. |
| 48 | * @instr: operational instruction |
| 49 | * @store: store instruction |
| 50 | * |
| 51 | * Note: we can trivially conditionalise the store instruction |
Simon Arlott | 6cbdc8c | 2007-05-11 20:40:30 +0100 | [diff] [blame] | 52 | * to avoid dirtying the data cache. |
Russell King | 7a55fd0 | 2005-04-18 22:50:01 +0100 | [diff] [blame] | 53 | */ |
| 54 | .macro testop, instr, store |
| 55 | add r1, r1, r0, lsr #3 |
| 56 | and r3, r0, #7 |
| 57 | mov r0, #1 |
Russell King | 59d1ff3 | 2005-11-09 15:04:22 +0000 | [diff] [blame] | 58 | save_and_disable_irqs ip |
Russell King | 7a55fd0 | 2005-04-18 22:50:01 +0100 | [diff] [blame] | 59 | ldrb r2, [r1] |
| 60 | tst r2, r0, lsl r3 |
| 61 | \instr r2, r2, r0, lsl r3 |
| 62 | \store r2, [r1] |
| 63 | restore_irqs ip |
| 64 | moveq r0, #0 |
| 65 | mov pc, lr |
| 66 | .endm |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 67 | #endif |