blob: 950c5d0b6dca0bc3210441017069b75dc9ed9866 [file] [log] [blame]
Shawn Guo179a5022012-10-04 17:13:49 -07001/*
2 * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/init.h>
13#include <linux/io.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18#include <linux/platform_device.h>
19#include <linux/rtc.h>
Sanchayan Maity7f899392014-12-10 15:54:17 -080020#include <linux/clk.h>
Frank Lid4828932015-05-27 00:25:57 +080021#include <linux/mfd/syscon.h>
22#include <linux/regmap.h>
23
24#define SNVS_LPREGISTER_OFFSET 0x34
Shawn Guo179a5022012-10-04 17:13:49 -070025
26/* These register offsets are relative to LP (Low Power) range */
27#define SNVS_LPCR 0x04
28#define SNVS_LPSR 0x18
29#define SNVS_LPSRTCMR 0x1c
30#define SNVS_LPSRTCLR 0x20
31#define SNVS_LPTAR 0x24
32#define SNVS_LPPGDR 0x30
33
34#define SNVS_LPCR_SRTC_ENV (1 << 0)
35#define SNVS_LPCR_LPTA_EN (1 << 1)
36#define SNVS_LPCR_LPWUI_EN (1 << 3)
37#define SNVS_LPSR_LPTA (1 << 0)
38
39#define SNVS_LPPGDR_INIT 0x41736166
40#define CNTR_TO_SECS_SH 15
41
42struct snvs_rtc_data {
43 struct rtc_device *rtc;
Frank Lid4828932015-05-27 00:25:57 +080044 struct regmap *regmap;
45 int offset;
Shawn Guo179a5022012-10-04 17:13:49 -070046 int irq;
Sanchayan Maity7f899392014-12-10 15:54:17 -080047 struct clk *clk;
Shawn Guo179a5022012-10-04 17:13:49 -070048};
49
Frank Lid4828932015-05-27 00:25:57 +080050static u32 rtc_read_lp_counter(struct snvs_rtc_data *data)
Shawn Guo179a5022012-10-04 17:13:49 -070051{
52 u64 read1, read2;
Frank Lid4828932015-05-27 00:25:57 +080053 u32 val;
Shawn Guo179a5022012-10-04 17:13:49 -070054
55 do {
Frank Lid4828932015-05-27 00:25:57 +080056 regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &val);
57 read1 = val;
Shawn Guo179a5022012-10-04 17:13:49 -070058 read1 <<= 32;
Frank Lid4828932015-05-27 00:25:57 +080059 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &val);
60 read1 |= val;
Shawn Guo179a5022012-10-04 17:13:49 -070061
Frank Lid4828932015-05-27 00:25:57 +080062 regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &val);
63 read2 = val;
Shawn Guo179a5022012-10-04 17:13:49 -070064 read2 <<= 32;
Frank Lid4828932015-05-27 00:25:57 +080065 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &val);
66 read2 |= val;
Shawn Guo179a5022012-10-04 17:13:49 -070067 } while (read1 != read2);
68
69 /* Convert 47-bit counter to 32-bit raw second count */
70 return (u32) (read1 >> CNTR_TO_SECS_SH);
71}
72
Frank Lid4828932015-05-27 00:25:57 +080073static void rtc_write_sync_lp(struct snvs_rtc_data *data)
Shawn Guo179a5022012-10-04 17:13:49 -070074{
75 u32 count1, count2, count3;
76 int i;
77
78 /* Wait for 3 CKIL cycles */
79 for (i = 0; i < 3; i++) {
80 do {
Frank Lid4828932015-05-27 00:25:57 +080081 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
82 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count2);
Shawn Guo179a5022012-10-04 17:13:49 -070083 } while (count1 != count2);
84
85 /* Now wait until counter value changes */
86 do {
87 do {
Frank Lid4828932015-05-27 00:25:57 +080088 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count2);
89 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count3);
Shawn Guo179a5022012-10-04 17:13:49 -070090 } while (count2 != count3);
91 } while (count3 == count1);
92 }
93}
94
95static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
96{
Shawn Guo179a5022012-10-04 17:13:49 -070097 int timeout = 1000;
98 u32 lpcr;
99
Frank Lid4828932015-05-27 00:25:57 +0800100 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV,
101 enable ? SNVS_LPCR_SRTC_ENV : 0);
Shawn Guo179a5022012-10-04 17:13:49 -0700102
103 while (--timeout) {
Frank Lid4828932015-05-27 00:25:57 +0800104 regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr);
Shawn Guo179a5022012-10-04 17:13:49 -0700105
106 if (enable) {
107 if (lpcr & SNVS_LPCR_SRTC_ENV)
108 break;
109 } else {
110 if (!(lpcr & SNVS_LPCR_SRTC_ENV))
111 break;
112 }
113 }
114
115 if (!timeout)
116 return -ETIMEDOUT;
117
118 return 0;
119}
120
121static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm)
122{
123 struct snvs_rtc_data *data = dev_get_drvdata(dev);
Frank Lid4828932015-05-27 00:25:57 +0800124 unsigned long time = rtc_read_lp_counter(data);
Shawn Guo179a5022012-10-04 17:13:49 -0700125
126 rtc_time_to_tm(time, tm);
127
128 return 0;
129}
130
131static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm)
132{
133 struct snvs_rtc_data *data = dev_get_drvdata(dev);
134 unsigned long time;
135
136 rtc_tm_to_time(tm, &time);
137
138 /* Disable RTC first */
139 snvs_rtc_enable(data, false);
140
141 /* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
Frank Lid4828932015-05-27 00:25:57 +0800142 regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH);
143 regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH));
Shawn Guo179a5022012-10-04 17:13:49 -0700144
145 /* Enable RTC again */
146 snvs_rtc_enable(data, true);
147
148 return 0;
149}
150
151static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
152{
153 struct snvs_rtc_data *data = dev_get_drvdata(dev);
154 u32 lptar, lpsr;
155
Frank Lid4828932015-05-27 00:25:57 +0800156 regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar);
Shawn Guo179a5022012-10-04 17:13:49 -0700157 rtc_time_to_tm(lptar, &alrm->time);
158
Frank Lid4828932015-05-27 00:25:57 +0800159 regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
Shawn Guo179a5022012-10-04 17:13:49 -0700160 alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;
161
162 return 0;
163}
164
165static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
166{
167 struct snvs_rtc_data *data = dev_get_drvdata(dev);
Shawn Guo179a5022012-10-04 17:13:49 -0700168
Frank Lid4828932015-05-27 00:25:57 +0800169 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR,
170 (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN),
171 enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0);
Shawn Guo179a5022012-10-04 17:13:49 -0700172
Frank Lid4828932015-05-27 00:25:57 +0800173 rtc_write_sync_lp(data);
Shawn Guo179a5022012-10-04 17:13:49 -0700174
175 return 0;
176}
177
178static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
179{
180 struct snvs_rtc_data *data = dev_get_drvdata(dev);
181 struct rtc_time *alrm_tm = &alrm->time;
182 unsigned long time;
Shawn Guo179a5022012-10-04 17:13:49 -0700183
184 rtc_tm_to_time(alrm_tm, &time);
185
Frank Lid4828932015-05-27 00:25:57 +0800186 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0);
187 regmap_write(data->regmap, data->offset + SNVS_LPTAR, time);
Shawn Guo179a5022012-10-04 17:13:49 -0700188
189 /* Clear alarm interrupt status bit */
Frank Lid4828932015-05-27 00:25:57 +0800190 regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA);
Shawn Guo179a5022012-10-04 17:13:49 -0700191
192 return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
193}
194
195static const struct rtc_class_ops snvs_rtc_ops = {
196 .read_time = snvs_rtc_read_time,
197 .set_time = snvs_rtc_set_time,
198 .read_alarm = snvs_rtc_read_alarm,
199 .set_alarm = snvs_rtc_set_alarm,
200 .alarm_irq_enable = snvs_rtc_alarm_irq_enable,
201};
202
203static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
204{
205 struct device *dev = dev_id;
206 struct snvs_rtc_data *data = dev_get_drvdata(dev);
207 u32 lpsr;
208 u32 events = 0;
209
Frank Lid4828932015-05-27 00:25:57 +0800210 regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
Shawn Guo179a5022012-10-04 17:13:49 -0700211
212 if (lpsr & SNVS_LPSR_LPTA) {
213 events |= (RTC_AF | RTC_IRQF);
214
215 /* RTC alarm should be one-shot */
216 snvs_rtc_alarm_irq_enable(dev, 0);
217
218 rtc_update_irq(data->rtc, 1, events);
219 }
220
221 /* clear interrupt status */
Frank Lid4828932015-05-27 00:25:57 +0800222 regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr);
Shawn Guo179a5022012-10-04 17:13:49 -0700223
224 return events ? IRQ_HANDLED : IRQ_NONE;
225}
226
Frank Lid4828932015-05-27 00:25:57 +0800227static const struct regmap_config snvs_rtc_config = {
228 .reg_bits = 32,
229 .val_bits = 32,
230 .reg_stride = 4,
231};
232
Greg Kroah-Hartman5a167f42012-12-21 13:09:38 -0800233static int snvs_rtc_probe(struct platform_device *pdev)
Shawn Guo179a5022012-10-04 17:13:49 -0700234{
235 struct snvs_rtc_data *data;
236 struct resource *res;
237 int ret;
Frank Lid4828932015-05-27 00:25:57 +0800238 void __iomem *mmio;
Shawn Guo179a5022012-10-04 17:13:49 -0700239
240 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
241 if (!data)
242 return -ENOMEM;
243
Frank Lid4828932015-05-27 00:25:57 +0800244 data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");
245
246 if (IS_ERR(data->regmap)) {
247 dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n");
248 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
249
250 mmio = devm_ioremap_resource(&pdev->dev, res);
251 if (IS_ERR(mmio))
252 return PTR_ERR(mmio);
253
254 data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config);
255 } else {
256 data->offset = SNVS_LPREGISTER_OFFSET;
257 of_property_read_u32(pdev->dev.of_node, "offset", &data->offset);
258 }
259
260 if (!data->regmap) {
261 dev_err(&pdev->dev, "Can't find snvs syscon\n");
262 return -ENODEV;
263 }
Shawn Guo179a5022012-10-04 17:13:49 -0700264
265 data->irq = platform_get_irq(pdev, 0);
266 if (data->irq < 0)
267 return data->irq;
268
Sanchayan Maity7f899392014-12-10 15:54:17 -0800269 data->clk = devm_clk_get(&pdev->dev, "snvs-rtc");
270 if (IS_ERR(data->clk)) {
271 data->clk = NULL;
272 } else {
273 ret = clk_prepare_enable(data->clk);
274 if (ret) {
275 dev_err(&pdev->dev,
276 "Could not prepare or enable the snvs clock\n");
277 return ret;
278 }
279 }
280
Shawn Guo179a5022012-10-04 17:13:49 -0700281 platform_set_drvdata(pdev, data);
282
Shawn Guo179a5022012-10-04 17:13:49 -0700283 /* Initialize glitch detect */
Frank Lid4828932015-05-27 00:25:57 +0800284 regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT);
Shawn Guo179a5022012-10-04 17:13:49 -0700285
286 /* Clear interrupt status */
Frank Lid4828932015-05-27 00:25:57 +0800287 regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff);
Shawn Guo179a5022012-10-04 17:13:49 -0700288
289 /* Enable RTC */
290 snvs_rtc_enable(data, true);
291
292 device_init_wakeup(&pdev->dev, true);
293
294 ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
295 IRQF_SHARED, "rtc alarm", &pdev->dev);
296 if (ret) {
297 dev_err(&pdev->dev, "failed to request irq %d: %d\n",
298 data->irq, ret);
Sanchayan Maity7f899392014-12-10 15:54:17 -0800299 goto error_rtc_device_register;
Shawn Guo179a5022012-10-04 17:13:49 -0700300 }
301
Jingoo Han904784c2013-04-29 16:19:12 -0700302 data->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
Shawn Guo179a5022012-10-04 17:13:49 -0700303 &snvs_rtc_ops, THIS_MODULE);
304 if (IS_ERR(data->rtc)) {
305 ret = PTR_ERR(data->rtc);
306 dev_err(&pdev->dev, "failed to register rtc: %d\n", ret);
Sanchayan Maity7f899392014-12-10 15:54:17 -0800307 goto error_rtc_device_register;
Shawn Guo179a5022012-10-04 17:13:49 -0700308 }
309
310 return 0;
Sanchayan Maity7f899392014-12-10 15:54:17 -0800311
312error_rtc_device_register:
313 if (data->clk)
314 clk_disable_unprepare(data->clk);
315
316 return ret;
Shawn Guo179a5022012-10-04 17:13:49 -0700317}
318
Shawn Guo179a5022012-10-04 17:13:49 -0700319#ifdef CONFIG_PM_SLEEP
320static int snvs_rtc_suspend(struct device *dev)
321{
322 struct snvs_rtc_data *data = dev_get_drvdata(dev);
323
324 if (device_may_wakeup(dev))
325 enable_irq_wake(data->irq);
326
Stefan Agner119434f2015-05-21 17:29:35 +0200327 return 0;
328}
329
330static int snvs_rtc_suspend_noirq(struct device *dev)
331{
332 struct snvs_rtc_data *data = dev_get_drvdata(dev);
333
Sanchayan Maity7f899392014-12-10 15:54:17 -0800334 if (data->clk)
335 clk_disable_unprepare(data->clk);
336
Shawn Guo179a5022012-10-04 17:13:49 -0700337 return 0;
338}
339
340static int snvs_rtc_resume(struct device *dev)
341{
342 struct snvs_rtc_data *data = dev_get_drvdata(dev);
343
344 if (device_may_wakeup(dev))
Stefan Agner119434f2015-05-21 17:29:35 +0200345 return disable_irq_wake(data->irq);
Shawn Guo179a5022012-10-04 17:13:49 -0700346
Stefan Agner119434f2015-05-21 17:29:35 +0200347 return 0;
348}
349
350static int snvs_rtc_resume_noirq(struct device *dev)
351{
352 struct snvs_rtc_data *data = dev_get_drvdata(dev);
353
354 if (data->clk)
355 return clk_prepare_enable(data->clk);
Sanchayan Maity7f899392014-12-10 15:54:17 -0800356
Shawn Guo179a5022012-10-04 17:13:49 -0700357 return 0;
358}
Shawn Guo179a5022012-10-04 17:13:49 -0700359
Sanchayan Maity7654e9d2014-12-10 15:54:20 -0800360static const struct dev_pm_ops snvs_rtc_pm_ops = {
Stefan Agner119434f2015-05-21 17:29:35 +0200361 .suspend = snvs_rtc_suspend,
362 .suspend_noirq = snvs_rtc_suspend_noirq,
363 .resume = snvs_rtc_resume,
364 .resume_noirq = snvs_rtc_resume_noirq,
Sanchayan Maity7654e9d2014-12-10 15:54:20 -0800365};
Shawn Guo179a5022012-10-04 17:13:49 -0700366
Guenter Roeck88221c32014-12-12 16:54:12 -0800367#define SNVS_RTC_PM_OPS (&snvs_rtc_pm_ops)
368
369#else
370
371#define SNVS_RTC_PM_OPS NULL
372
373#endif
374
Greg Kroah-Hartman5a167f42012-12-21 13:09:38 -0800375static const struct of_device_id snvs_dt_ids[] = {
Shawn Guo179a5022012-10-04 17:13:49 -0700376 { .compatible = "fsl,sec-v4.0-mon-rtc-lp", },
377 { /* sentinel */ }
378};
379MODULE_DEVICE_TABLE(of, snvs_dt_ids);
380
381static struct platform_driver snvs_rtc_driver = {
382 .driver = {
383 .name = "snvs_rtc",
Guenter Roeck88221c32014-12-12 16:54:12 -0800384 .pm = SNVS_RTC_PM_OPS,
Sachin Kamatc39b3712013-11-12 15:10:57 -0800385 .of_match_table = snvs_dt_ids,
Shawn Guo179a5022012-10-04 17:13:49 -0700386 },
387 .probe = snvs_rtc_probe,
Shawn Guo179a5022012-10-04 17:13:49 -0700388};
389module_platform_driver(snvs_rtc_driver);
390
391MODULE_AUTHOR("Freescale Semiconductor, Inc.");
392MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
393MODULE_LICENSE("GPL");