Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #ifndef _SDE_HW_CATALOG_H |
| 14 | #define _SDE_HW_CATALOG_H |
| 15 | |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/bug.h> |
| 18 | #include <linux/bitmap.h> |
| 19 | #include <linux/err.h> |
| 20 | |
| 21 | #define MAX_BLOCKS 8 |
| 22 | #define MAX_LAYERS 12 |
| 23 | |
| 24 | #define SDE_HW_VER(MAJOR, MINOR, STEP) (((MAJOR & 0xF) << 28) |\ |
| 25 | ((MINOR & 0xFFF) << 16) |\ |
| 26 | (STEP & 0xFFFF)) |
| 27 | |
| 28 | #define SDE_HW_MAJOR(rev) ((rev) >> 28) |
| 29 | #define SDE_HW_MINOR(rev) .(((rev) >> 16) & 0xFFF) |
| 30 | #define SDE_HW_STEP(rev) ((rev) & 0xFFFF) |
| 31 | #define SDE_HW_MAJOR_MINOR(rev) ((rev) >> 16) |
| 32 | |
| 33 | #define IS_SDE_MAJOR_MINOR_SAME(rev1, rev2) \ |
| 34 | (SDE_HW_MAJOR_MINOR((rev1)) == SDE_HW_MAJOR_MINOR((rev2))) |
| 35 | |
| 36 | #define SDE_HW_VER_170 SDE_HW_VER(1, 7, 0) /* 8996 v1.0 */ |
| 37 | #define SDE_HW_VER_171 SDE_HW_VER(1, 7, 1) /* 8996 v2.0 */ |
| 38 | #define SDE_HW_VER_172 SDE_HW_VER(1, 7, 2) /* 8996 v3.0 */ |
| 39 | #define SDE_HW_VER_300 SDE_HW_VER(3, 0, 0) /* 8998 v1.0 */ |
| 40 | |
| 41 | /** |
| 42 | * MDP TOP BLOCK features |
| 43 | * @SDE_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe |
| 44 | * @SDE_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats |
| 45 | * @SDE_MDP_BWC, MDSS HW supports Bandwidth compression. |
| 46 | * @SDE_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth |
| 47 | * compression initial revision |
| 48 | * @SDE_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5 |
| 49 | * @SDE_MDP_CDP, Client driven prefetch |
| 50 | * @SDE_MDP_MAX Maximum value |
| 51 | |
| 52 | */ |
| 53 | enum { |
| 54 | SDE_MDP_PANIC_PER_PIPE = 0x1, |
| 55 | SDE_MDP_10BIT_SUPPORT, |
| 56 | SDE_MDP_BWC, |
| 57 | SDE_MDP_UBWC_1_0, |
| 58 | SDE_MDP_UBWC_1_5, |
| 59 | SDE_MDP_CDP, |
| 60 | SDE_MDP_MAX |
| 61 | }; |
| 62 | |
| 63 | /** |
| 64 | * SSPP sub-blocks/features |
| 65 | * @SDE_SSPP_SRC Src and fetch part of the pipes, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 66 | * @SDE_SSPP_SCALER_QSEED2, QSEED2 algorithm support |
| 67 | * @SDE_SSPP_SCALER_QSEED3, QSEED3 alogorithm support |
| 68 | * @SDE_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes |
| 69 | * @SDE_SSPP_CSC, Support of Color space converion |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 70 | * @SDE_SSPP_PA_V1, Common op-mode register for PA blocks |
| 71 | * @SDE_SSPP_HIST_V1 Histogram programming method V1 |
| 72 | * @SDE_SSPP_IGC, Inverse gamma correction |
| 73 | * @SDE_SSPP_PCC, Color correction support |
| 74 | * @SDE_SSPP_CURSOR, SSPP can be used as a cursor layer |
| 75 | * @SDE_SSPP_MAX maximum value |
| 76 | */ |
| 77 | enum { |
| 78 | SDE_SSPP_SRC = 0x1, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 79 | SDE_SSPP_SCALER_QSEED2, |
| 80 | SDE_SSPP_SCALER_QSEED3, |
| 81 | SDE_SSPP_SCALER_RGB, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 82 | SDE_SSPP_CSC, |
| 83 | SDE_SSPP_PA_V1, /* Common op-mode register for PA blocks */ |
| 84 | SDE_SSPP_HIST_V1, |
| 85 | SDE_SSPP_IGC, |
| 86 | SDE_SSPP_PCC, |
| 87 | SDE_SSPP_CURSOR, |
| 88 | SDE_SSPP_MAX |
| 89 | }; |
| 90 | |
| 91 | /* |
| 92 | * MIXER sub-blocks/features |
| 93 | * @SDE_MIXER_LAYER Layer mixer layer blend configuration, |
| 94 | * @SDE_MIXER_SOURCESPLIT Layer mixer supports source-split configuration |
| 95 | * @SDE_MIXER_GC Gamma correction block |
| 96 | * @SDE_MIXER_MAX maximum value |
| 97 | */ |
| 98 | enum { |
| 99 | SDE_MIXER_LAYER = 0x1, |
| 100 | SDE_MIXER_SOURCESPLIT, |
| 101 | SDE_MIXER_GC, |
| 102 | SDE_MIXER_MAX |
| 103 | }; |
| 104 | |
| 105 | /** |
| 106 | * DSPP sub-blocks |
| 107 | * @SDE_DSPP_IGC DSPP Inverse gamma correction block |
| 108 | * @SDE_DSPP_PCC Panel color correction block |
| 109 | * @SDE_DSPP_GC Gamma correction block |
| 110 | * @SDE_DSPP_PA Picture adjustment block |
| 111 | * @SDE_DSPP_GAMUT Gamut bloc |
| 112 | * @SDE_DSPP_DITHER Dither block |
| 113 | * @SDE_DSPP_HIST Histogram bloc |
| 114 | * @SDE_DSPP_MAX maximum value |
| 115 | */ |
| 116 | enum { |
| 117 | SDE_DSPP_IGC = 0x1, |
| 118 | SDE_DSPP_PCC, |
| 119 | SDE_DSPP_GC, |
| 120 | SDE_DSPP_PA, |
| 121 | SDE_DSPP_GAMUT, |
| 122 | SDE_DSPP_DITHER, |
| 123 | SDE_DSPP_HIST, |
| 124 | SDE_DSPP_MAX |
| 125 | }; |
| 126 | |
| 127 | /** |
| 128 | * PINGPONG sub-blocks |
| 129 | * @SDE_PINGPONG_TE Tear check block |
| 130 | * @SDE_PINGPONG_TE2 Additional tear check block for split pipes |
| 131 | * @SDE_PINGPONG_SPLIT PP block supports split fifo |
| 132 | * @SDE_PINGPONG_DSC, Display stream compression blocks |
| 133 | * @SDE_PINGPONG_MAX |
| 134 | */ |
| 135 | enum { |
| 136 | SDE_PINGPONG_TE = 0x1, |
| 137 | SDE_PINGPONG_TE2, |
| 138 | SDE_PINGPONG_SPLIT, |
| 139 | SDE_PINGPONG_DSC, |
| 140 | SDE_PINGPONG_MAX |
| 141 | }; |
| 142 | |
| 143 | /** |
| 144 | * WB sub-blocks and features |
| 145 | * @SDE_WB_LINE_MODE Writeback module supports line/linear mode |
| 146 | * @SDE_WB_BLOCK_MODE Writeback module supports block mode read |
| 147 | * @SDE_WB_ROTATE rotation support,this is available if writeback |
| 148 | * supports block mode read |
| 149 | * @SDE_WB_CSC Writeback color conversion block support |
| 150 | * @SDE_WB_CHROMA_DOWN, Writeback chroma down block, |
| 151 | * @SDE_WB_DOWNSCALE, Writeback integer downscaler, |
| 152 | * @SDE_WB_DITHER, Dither block |
| 153 | * @SDE_WB_TRAFFIC_SHAPER, Writeback traffic shaper bloc |
| 154 | * @SDE_WB_UBWC_1_0, Writeback Universal bandwidth compression 1.0 |
| 155 | * support |
| 156 | * @SDE_WB_WBWC_1_5 UBWC 1.5 support |
Alan Kwong | 3232ca5 | 2016-07-29 02:27:47 -0400 | [diff] [blame] | 157 | * @SDE_WB_YUV_CONFIG Writeback supports output of YUV colorspace |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 158 | * @SDE_WB_MAX maximum value |
| 159 | */ |
| 160 | enum { |
| 161 | SDE_WB_LINE_MODE = 0x1, |
| 162 | SDE_WB_BLOCK_MODE, |
| 163 | SDE_WB_ROTATE = SDE_WB_BLOCK_MODE, |
| 164 | SDE_WB_CSC, |
| 165 | SDE_WB_CHROMA_DOWN, |
| 166 | SDE_WB_DOWNSCALE, |
| 167 | SDE_WB_DITHER, |
| 168 | SDE_WB_TRAFFIC_SHAPER, |
| 169 | SDE_WB_UBWC_1_0, |
Alan Kwong | 3232ca5 | 2016-07-29 02:27:47 -0400 | [diff] [blame] | 170 | SDE_WB_YUV_CONFIG, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 171 | SDE_WB_MAX |
| 172 | }; |
| 173 | |
| 174 | /** |
| 175 | * MACRO SDE_HW_BLK_INFO - information of HW blocks inside SDE |
| 176 | * @id: enum identifying this block |
| 177 | * @base: register base offset to mdss |
| 178 | * @features bit mask identifying sub-blocks/features |
| 179 | */ |
| 180 | #define SDE_HW_BLK_INFO \ |
| 181 | u32 id; \ |
| 182 | u32 base; \ |
Alan Kwong | d21960f | 2016-07-29 03:33:17 -0400 | [diff] [blame^] | 183 | unsigned long features |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 184 | |
| 185 | /** |
| 186 | * MACRO SDE_HW_SUBBLK_INFO - information of HW sub-block inside SDE |
| 187 | * @id: enum identifying this sub-block |
| 188 | * @base: offset of this sub-block relative to the block |
| 189 | * offset |
| 190 | * @len register block length of this sub-block |
| 191 | */ |
| 192 | #define SDE_HW_SUBBLK_INFO \ |
| 193 | u32 id; \ |
| 194 | u32 base; \ |
| 195 | u32 len |
| 196 | |
| 197 | /** |
| 198 | * struct sde_src_blk: SSPP part of the source pipes |
| 199 | * @info: HW register and features supported by this sub-blk |
| 200 | */ |
| 201 | struct sde_src_blk { |
| 202 | SDE_HW_SUBBLK_INFO; |
| 203 | }; |
| 204 | |
| 205 | /** |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 206 | * struct sde_scaler_blk: Scaler information |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 207 | * @info: HW register and features supported by this sub-blk |
| 208 | */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 209 | struct sde_scaler_blk { |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 210 | SDE_HW_SUBBLK_INFO; |
| 211 | }; |
| 212 | |
| 213 | struct sde_csc_blk { |
| 214 | SDE_HW_SUBBLK_INFO; |
| 215 | }; |
| 216 | |
| 217 | /** |
| 218 | * struct sde_pp_blk : Pixel processing sub-blk information |
| 219 | * @info: HW register and features supported by this sub-blk |
| 220 | * @version: HW Algorithm version |
| 221 | */ |
| 222 | struct sde_pp_blk { |
| 223 | SDE_HW_SUBBLK_INFO; |
| 224 | u32 version; |
| 225 | }; |
| 226 | |
| 227 | /** |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 228 | * struct sde_format_extended - define sde specific pixel format+modifier |
| 229 | * @fourcc_format: Base FOURCC pixel format code |
| 230 | * @modifier: 64-bit drm format modifier, same modifier must be applied to all |
| 231 | * framebuffer planes |
| 232 | */ |
| 233 | struct sde_format_extended { |
| 234 | uint32_t fourcc_format; |
| 235 | uint64_t modifier; |
| 236 | }; |
| 237 | |
| 238 | /** |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 239 | * struct sde_sspp_sub_blks : SSPP sub-blocks |
| 240 | * @maxdwnscale: max downscale ratio supported(without DECIMATION) |
| 241 | * @maxupscale: maxupscale ratio supported |
| 242 | * @maxwidth: max pixelwidth supported by this pipe |
| 243 | * @danger_lut: LUT to generate danger signals |
| 244 | * @safe_lut: LUT to generate safe signals |
| 245 | * @src_blk: |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 246 | * @scaler_blk: |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 247 | * @csc_blk: |
| 248 | * @pa_blk: |
| 249 | * @hist_lut: |
| 250 | * @pcc_blk: |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 251 | * @format_list: Pointer to list of supported formats |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 252 | */ |
| 253 | struct sde_sspp_sub_blks { |
| 254 | u32 maxlinewidth; |
| 255 | u32 danger_lut; |
| 256 | u32 safe_lut; |
| 257 | u32 maxdwnscale; |
| 258 | u32 maxupscale; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 259 | u32 maxhdeciexp; /* max decimation is 2^value */ |
| 260 | u32 maxvdeciexp; /* max decimation is 2^value */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 261 | struct sde_src_blk src_blk; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 262 | struct sde_scaler_blk scaler_blk; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 263 | struct sde_pp_blk csc_blk; |
| 264 | struct sde_pp_blk pa_blk; |
| 265 | struct sde_pp_blk hist_lut; |
| 266 | struct sde_pp_blk pcc_blk; |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 267 | |
| 268 | const struct sde_format_extended *format_list; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 269 | }; |
| 270 | |
| 271 | /** |
| 272 | * struct sde_lm_sub_blks: information of mixer block |
| 273 | * @maxwidth: Max pixel width supported by this mixer |
| 274 | * @maxblendstages: Max number of blend-stages supported |
| 275 | * @blendstage_base: Blend-stage register base offset |
| 276 | */ |
| 277 | struct sde_lm_sub_blks { |
| 278 | u32 maxwidth; |
| 279 | u32 maxblendstages; |
| 280 | u32 blendstage_base[MAX_BLOCKS]; |
| 281 | }; |
| 282 | |
| 283 | struct sde_dspp_sub_blks { |
| 284 | struct sde_pp_blk igc; |
| 285 | struct sde_pp_blk pcc; |
| 286 | struct sde_pp_blk gc; |
| 287 | struct sde_pp_blk pa; |
| 288 | struct sde_pp_blk gamut; |
| 289 | struct sde_pp_blk dither; |
| 290 | struct sde_pp_blk hist; |
| 291 | }; |
| 292 | |
| 293 | struct sde_pingpong_sub_blks { |
| 294 | struct sde_pp_blk te; |
| 295 | struct sde_pp_blk te2; |
| 296 | struct sde_pp_blk dsc; |
| 297 | }; |
| 298 | |
| 299 | struct sde_wb_sub_blocks { |
| 300 | u32 maxlinewidth; |
| 301 | }; |
| 302 | |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 303 | struct sde_mdss_base_cfg { |
| 304 | SDE_HW_BLK_INFO; |
| 305 | }; |
| 306 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 307 | /* struct sde_mdp_cfg : MDP TOP-BLK instance info |
| 308 | * @id: index identifying this block |
| 309 | * @base: register base offset to mdss |
| 310 | * @features bit mask identifying sub-blocks/features |
| 311 | * @highest_bank_bit: UBWC parameter |
| 312 | */ |
| 313 | struct sde_mdp_cfg { |
| 314 | SDE_HW_BLK_INFO; |
| 315 | u32 highest_bank_bit; |
| 316 | }; |
| 317 | |
| 318 | /* struct sde_mdp_cfg : MDP TOP-BLK instance info |
| 319 | * @id: index identifying this block |
| 320 | * @base: register base offset to mdss |
| 321 | * @features bit mask identifying sub-blocks/features |
| 322 | */ |
| 323 | struct sde_ctl_cfg { |
| 324 | SDE_HW_BLK_INFO; |
| 325 | }; |
| 326 | |
| 327 | /** |
| 328 | * struct sde_sspp_cfg - information of source pipes |
| 329 | * @id: index identifying this block |
| 330 | * @base register offset of this block |
| 331 | * @features bit mask identifying sub-blocks/features |
| 332 | * @sblk: Sub-blocks of SSPP |
| 333 | */ |
| 334 | struct sde_sspp_cfg { |
| 335 | SDE_HW_BLK_INFO; |
| 336 | const struct sde_sspp_sub_blks *sblk; |
| 337 | }; |
| 338 | |
| 339 | /** |
| 340 | * struct sde_lm_cfg - information of layer mixer blocks |
| 341 | * @id: index identifying this block |
| 342 | * @base register offset of this block |
| 343 | * @features bit mask identifying sub-blocks/features |
| 344 | * @sblk: Sub-blocks of SSPP |
| 345 | */ |
| 346 | struct sde_lm_cfg { |
| 347 | SDE_HW_BLK_INFO; |
| 348 | const struct sde_lm_sub_blks *sblk; |
| 349 | }; |
| 350 | |
| 351 | /** |
| 352 | * struct sde_dspp_cfg - information of DSPP blocks |
| 353 | * @id enum identifying this block |
| 354 | * @base register offset of this block |
| 355 | * @features bit mask identifying sub-blocks/features |
| 356 | * supported by this block |
| 357 | * @sblk sub-blocks information |
| 358 | */ |
| 359 | struct sde_dspp_cfg { |
| 360 | SDE_HW_BLK_INFO; |
| 361 | const struct sde_dspp_sub_blks *sblk; |
| 362 | }; |
| 363 | |
| 364 | /** |
| 365 | * struct sde_pingpong_cfg - information of PING-PONG blocks |
| 366 | * @id enum identifying this block |
| 367 | * @base register offset of this block |
| 368 | * @features bit mask identifying sub-blocks/features |
| 369 | * @sblk sub-blocks information |
| 370 | */ |
| 371 | struct sde_pingpong_cfg { |
| 372 | SDE_HW_BLK_INFO; |
| 373 | const struct sde_pingpong_sub_blks *sblk; |
| 374 | }; |
| 375 | |
| 376 | /** |
| 377 | * struct sde_cdm_cfg - information of chroma down blocks |
| 378 | * @id enum identifying this block |
| 379 | * @base register offset of this block |
| 380 | * @features bit mask identifying sub-blocks/features |
| 381 | * @intf_connect Connects to which interfaces |
| 382 | * @wb_connect: Connects to which writebacks |
| 383 | */ |
| 384 | struct sde_cdm_cfg { |
| 385 | SDE_HW_BLK_INFO; |
| 386 | u32 intf_connect[MAX_BLOCKS]; |
| 387 | u32 wb_connect[MAX_BLOCKS]; |
| 388 | }; |
| 389 | |
| 390 | /** |
| 391 | * struct sde_intf_cfg - information of timing engine blocks |
| 392 | * @id enum identifying this block |
| 393 | * @base register offset of this block |
| 394 | * @features bit mask identifying sub-blocks/features |
| 395 | * @type: Interface type(DSI, DP, HDMI) |
Lloyd Atkinson | 2d4e766 | 2015-11-05 15:52:07 -0500 | [diff] [blame] | 396 | * @controller_id: Controller Instance ID in case of multiple of intf type |
Lloyd Atkinson | f30546e | 2016-06-26 10:08:25 -0400 | [diff] [blame] | 397 | * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 398 | */ |
| 399 | struct sde_intf_cfg { |
| 400 | SDE_HW_BLK_INFO; |
| 401 | u32 type; /* interface type*/ |
Lloyd Atkinson | 2d4e766 | 2015-11-05 15:52:07 -0500 | [diff] [blame] | 402 | u32 controller_id; |
Lloyd Atkinson | f30546e | 2016-06-26 10:08:25 -0400 | [diff] [blame] | 403 | u32 prog_fetch_lines_worst_case; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 404 | }; |
| 405 | |
| 406 | /** |
| 407 | * struct sde_wb_cfg - information of writeback blocks |
| 408 | * @id enum identifying this block |
| 409 | * @base register offset of this block |
| 410 | * @features bit mask identifying sub-blocks/features |
| 411 | */ |
| 412 | struct sde_wb_cfg { |
| 413 | SDE_HW_BLK_INFO; |
| 414 | struct sde_wb_sub_blocks *sblk; |
| 415 | }; |
| 416 | |
| 417 | /** |
| 418 | * struct sde_ad_cfg - information of Assertive Display blocks |
| 419 | * @id enum identifying this block |
| 420 | * @base register offset of this block |
| 421 | * @features bit mask identifying sub-blocks/features |
| 422 | */ |
| 423 | struct sde_ad_cfg { |
| 424 | SDE_HW_BLK_INFO; |
| 425 | }; |
| 426 | |
| 427 | /** |
| 428 | * struct sde_mdss_cfg - information of MDSS HW |
| 429 | * This is the main catalog data structure representing |
| 430 | * this HW version. Contains number of instances, |
| 431 | * register offsets, capabilities of the all MDSS HW sub-blocks. |
| 432 | */ |
| 433 | struct sde_mdss_cfg { |
| 434 | u32 hwversion; |
| 435 | |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 436 | u32 mdss_count; |
| 437 | struct sde_mdss_base_cfg mdss[MAX_BLOCKS]; |
| 438 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 439 | u32 mdp_count; |
| 440 | struct sde_mdp_cfg mdp[MAX_BLOCKS]; |
| 441 | |
| 442 | u32 ctl_count; |
| 443 | struct sde_ctl_cfg ctl[MAX_BLOCKS]; |
| 444 | |
| 445 | u32 sspp_count; |
| 446 | struct sde_sspp_cfg sspp[MAX_LAYERS]; |
| 447 | |
| 448 | u32 mixer_count; |
| 449 | struct sde_lm_cfg mixer[MAX_BLOCKS]; |
| 450 | |
| 451 | u32 dspp_count; |
| 452 | struct sde_dspp_cfg dspp[MAX_BLOCKS]; |
| 453 | |
| 454 | u32 pingpong_count; |
| 455 | struct sde_pingpong_cfg pingpong[MAX_BLOCKS]; |
| 456 | |
| 457 | u32 cdm_count; |
| 458 | struct sde_cdm_cfg cdm[MAX_BLOCKS]; |
| 459 | |
| 460 | u32 intf_count; |
| 461 | struct sde_intf_cfg intf[MAX_BLOCKS]; |
| 462 | |
| 463 | u32 wb_count; |
| 464 | struct sde_wb_cfg wb[MAX_BLOCKS]; |
| 465 | |
| 466 | u32 ad_count; |
| 467 | struct sde_ad_cfg ad[MAX_BLOCKS]; |
| 468 | /* Add additional block data structures here */ |
| 469 | }; |
| 470 | |
| 471 | struct sde_mdss_hw_cfg_handler { |
| 472 | u32 major; |
| 473 | u32 minor; |
| 474 | struct sde_mdss_cfg* (*cfg_init)(u32); |
| 475 | }; |
| 476 | |
| 477 | /* |
| 478 | * Access Macros |
| 479 | */ |
| 480 | #define BLK_MDP(s) ((s)->mdp) |
| 481 | #define BLK_CTL(s) ((s)->ctl) |
| 482 | #define BLK_VIG(s) ((s)->vig) |
| 483 | #define BLK_RGB(s) ((s)->rgb) |
| 484 | #define BLK_DMA(s) ((s)->dma) |
| 485 | #define BLK_CURSOR(s) ((s)->cursor) |
| 486 | #define BLK_MIXER(s) ((s)->mixer) |
| 487 | #define BLK_DSPP(s) ((s)->dspp) |
| 488 | #define BLK_PINGPONG(s) ((s)->pingpong) |
| 489 | #define BLK_CDM(s) ((s)->cdm) |
| 490 | #define BLK_INTF(s) ((s)->intf) |
| 491 | #define BLK_WB(s) ((s)->wb) |
| 492 | #define BLK_AD(s) ((s)->ad) |
| 493 | |
| 494 | struct sde_mdss_cfg *sde_mdss_cfg_170_init(u32 step); |
| 495 | struct sde_mdss_cfg *sde_hw_catalog_init(u32 major, u32 minor, u32 step); |
| 496 | |
| 497 | #endif /* _SDE_HW_CATALOG_H */ |