blob: 7e0cb1da92e68be66b9f8c0839a42ea0e6a95e99 [file] [log] [blame]
Dave Airlie0d6aa602006-01-02 20:14:23 +11001/*
Dave Airliebc54fd12005-06-23 22:46:46 +10002 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110025 */
Dave Airliebc54fd12005-06-23 22:46:46 +100026
Linus Torvalds1da177e2005-04-16 15:20:36 -070027#ifndef _I915_DRM_H_
28#define _I915_DRM_H_
29
30/* Please note that modifications to all structs defined here are
31 * subject to backwards-compatibility constraints.
32 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +010033#include <linux/types.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070034#include "drm.h"
35
36/* Each region is a minimum of 16k, and there are at most 255 of them.
37 */
38#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
39 * of chars for next/prev indices */
40#define I915_LOG_MIN_TEX_REGION_SIZE 14
41
42typedef struct _drm_i915_init {
43 enum {
44 I915_INIT_DMA = 0x01,
45 I915_CLEANUP_DMA = 0x02,
46 I915_RESUME_DMA = 0x03
47 } func;
48 unsigned int mmio_offset;
49 int sarea_priv_offset;
50 unsigned int ring_start;
51 unsigned int ring_end;
52 unsigned int ring_size;
53 unsigned int front_offset;
54 unsigned int back_offset;
55 unsigned int depth_offset;
56 unsigned int w;
57 unsigned int h;
58 unsigned int pitch;
59 unsigned int pitch_bits;
60 unsigned int back_pitch;
61 unsigned int depth_pitch;
62 unsigned int cpp;
63 unsigned int chipset;
64} drm_i915_init_t;
65
66typedef struct _drm_i915_sarea {
Dave Airliec60ce622007-07-11 15:27:12 +100067 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
Linus Torvalds1da177e2005-04-16 15:20:36 -070068 int last_upload; /* last time texture was uploaded */
69 int last_enqueue; /* last time a buffer was enqueued */
70 int last_dispatch; /* age of the most recently dispatched buffer */
71 int ctxOwner; /* last context to upload state */
72 int texAge;
73 int pf_enabled; /* is pageflipping allowed? */
74 int pf_active;
75 int pf_current_page; /* which buffer is being displayed? */
76 int perf_boxes; /* performance boxes to be displayed */
Dave Airliede227f52006-01-25 15:31:43 +110077 int width, height; /* screen size in pixels */
78
79 drm_handle_t front_handle;
80 int front_offset;
81 int front_size;
82
83 drm_handle_t back_handle;
84 int back_offset;
85 int back_size;
86
87 drm_handle_t depth_handle;
88 int depth_offset;
89 int depth_size;
90
91 drm_handle_t tex_handle;
92 int tex_offset;
93 int tex_size;
94 int log_tex_granularity;
95 int pitch;
96 int rotation; /* 0, 90, 180 or 270 */
97 int rotated_offset;
98 int rotated_size;
99 int rotated_pitch;
100 int virtualX, virtualY;
Alan Hourihanec29b6692006-08-12 16:29:24 +1000101
102 unsigned int front_tiled;
103 unsigned int back_tiled;
104 unsigned int depth_tiled;
105 unsigned int rotated_tiled;
106 unsigned int rotated2_tiled;
=?utf-8?q?Michel_D=C3=A4nzer?=376642c2006-10-25 00:09:35 +1000107
Dave Airlieaf6061a2008-05-07 12:15:39 +1000108 int pipeA_x;
109 int pipeA_y;
110 int pipeA_w;
111 int pipeA_h;
112 int pipeB_x;
113 int pipeB_y;
114 int pipeB_w;
115 int pipeB_h;
Dave Airliedfef2452008-12-19 15:07:46 +1000116
117 /* fill out some space for old userspace triple buffer */
118 drm_handle_t unused_handle;
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100119 __u32 unused1, unused2, unused3;
Dave Airliedfef2452008-12-19 15:07:46 +1000120
121 /* buffer object handles for static buffers. May change
122 * over the lifetime of the client.
123 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100124 __u32 front_bo_handle;
125 __u32 back_bo_handle;
126 __u32 unused_bo_handle;
127 __u32 depth_bo_handle;
Dave Airliedfef2452008-12-19 15:07:46 +1000128
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129} drm_i915_sarea_t;
130
Dave Airliedfef2452008-12-19 15:07:46 +1000131/* due to userspace building against these headers we need some compat here */
132#define planeA_x pipeA_x
133#define planeA_y pipeA_y
134#define planeA_w pipeA_w
135#define planeA_h pipeA_h
136#define planeB_x pipeB_x
137#define planeB_y pipeB_y
138#define planeB_w pipeB_w
139#define planeB_h pipeB_h
140
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141/* Flags for perf_boxes
142 */
143#define I915_BOX_RING_EMPTY 0x1
144#define I915_BOX_FLIP 0x2
145#define I915_BOX_WAIT 0x4
146#define I915_BOX_TEXTURE_LOAD 0x8
147#define I915_BOX_LOST_CONTEXT 0x10
148
149/* I915 specific ioctls
150 * The device specific ioctl range is 0x40 to 0x79.
151 */
152#define DRM_I915_INIT 0x00
153#define DRM_I915_FLUSH 0x01
154#define DRM_I915_FLIP 0x02
155#define DRM_I915_BATCHBUFFER 0x03
156#define DRM_I915_IRQ_EMIT 0x04
157#define DRM_I915_IRQ_WAIT 0x05
158#define DRM_I915_GETPARAM 0x06
159#define DRM_I915_SETPARAM 0x07
160#define DRM_I915_ALLOC 0x08
161#define DRM_I915_FREE 0x09
162#define DRM_I915_INIT_HEAP 0x0a
163#define DRM_I915_CMDBUFFER 0x0b
Dave Airliede227f52006-01-25 15:31:43 +1100164#define DRM_I915_DESTROY_HEAP 0x0c
Dave Airlie702880f2006-06-24 17:07:34 +1000165#define DRM_I915_SET_VBLANK_PIPE 0x0d
166#define DRM_I915_GET_VBLANK_PIPE 0x0e
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000167#define DRM_I915_VBLANK_SWAP 0x0f
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000168#define DRM_I915_HWS_ADDR 0x11
Eric Anholt673a3942008-07-30 12:06:12 -0700169#define DRM_I915_GEM_INIT 0x13
170#define DRM_I915_GEM_EXECBUFFER 0x14
171#define DRM_I915_GEM_PIN 0x15
172#define DRM_I915_GEM_UNPIN 0x16
173#define DRM_I915_GEM_BUSY 0x17
174#define DRM_I915_GEM_THROTTLE 0x18
175#define DRM_I915_GEM_ENTERVT 0x19
176#define DRM_I915_GEM_LEAVEVT 0x1a
177#define DRM_I915_GEM_CREATE 0x1b
178#define DRM_I915_GEM_PREAD 0x1c
179#define DRM_I915_GEM_PWRITE 0x1d
180#define DRM_I915_GEM_MMAP 0x1e
181#define DRM_I915_GEM_SET_DOMAIN 0x1f
182#define DRM_I915_GEM_SW_FINISH 0x20
183#define DRM_I915_GEM_SET_TILING 0x21
184#define DRM_I915_GEM_GET_TILING 0x22
Eric Anholt5a125c32008-10-22 21:40:13 -0700185#define DRM_I915_GEM_GET_APERTURE 0x23
Jesse Barnesde151cf2008-11-12 10:03:55 -0800186#define DRM_I915_GEM_MMAP_GTT 0x24
Carl Worth08d7b3d2009-04-29 14:43:54 -0700187#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
Chris Wilson3ef94da2009-09-14 16:50:29 +0100188#define DRM_I915_GEM_MADVISE 0x26
Linus Torvalds1da177e2005-04-16 15:20:36 -0700189
190#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
191#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
Dave Airlieaf6061a2008-05-07 12:15:39 +1000192#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700193#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
194#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
195#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
196#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
197#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
198#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
199#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
200#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
201#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
Dave Airliede227f52006-01-25 15:31:43 +1100202#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
Dave Airlie702880f2006-06-24 17:07:34 +1000203#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
204#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
=?utf-8?q?Michel_D=C3=A4nzer?=541f29a2006-10-24 23:38:54 +1000205#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
Eric Anholt8d391aa2008-12-17 22:32:14 -0800206#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
207#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
Eric Anholt673a3942008-07-30 12:06:12 -0700208#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
209#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
210#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
211#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
212#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
213#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
214#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
215#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
216#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
217#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
Jesse Barnesde151cf2008-11-12 10:03:55 -0800218#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
Eric Anholt673a3942008-07-30 12:06:12 -0700219#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
220#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
221#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
222#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
Eric Anholt5a125c32008-10-22 21:40:13 -0700223#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
Carl Worth08d7b3d2009-04-29 14:43:54 -0700224#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_intel_get_pipe_from_crtc_id)
Chris Wilson3ef94da2009-09-14 16:50:29 +0100225#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700226
227/* Allow drivers to submit batchbuffers directly to hardware, relying
228 * on the security mechanisms provided by hardware.
229 */
Jesse Barnes79e53942008-11-07 14:24:08 -0800230typedef struct drm_i915_batchbuffer {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231 int start; /* agp offset */
232 int used; /* nr bytes in use */
233 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
234 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
235 int num_cliprects; /* mulitpass with multiple cliprects? */
Dave Airliec60ce622007-07-11 15:27:12 +1000236 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237} drm_i915_batchbuffer_t;
238
239/* As above, but pass a pointer to userspace buffer which can be
240 * validated by the kernel prior to sending to hardware.
241 */
242typedef struct _drm_i915_cmdbuffer {
243 char __user *buf; /* pointer to userspace command buffer */
244 int sz; /* nr bytes in buf */
245 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
246 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
247 int num_cliprects; /* mulitpass with multiple cliprects? */
Dave Airliec60ce622007-07-11 15:27:12 +1000248 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700249} drm_i915_cmdbuffer_t;
250
251/* Userspace can request & wait on irq's:
252 */
253typedef struct drm_i915_irq_emit {
254 int __user *irq_seq;
255} drm_i915_irq_emit_t;
256
257typedef struct drm_i915_irq_wait {
258 int irq_seq;
259} drm_i915_irq_wait_t;
260
261/* Ioctl to query kernel params:
262 */
263#define I915_PARAM_IRQ_ACTIVE 1
264#define I915_PARAM_ALLOW_BATCHBUFFER 2
Dave Airlie0d6aa602006-01-02 20:14:23 +1100265#define I915_PARAM_LAST_DISPATCH 3
Kristian Høgsberged4c9c42008-08-20 11:08:52 -0400266#define I915_PARAM_CHIPSET_ID 4
Eric Anholt673a3942008-07-30 12:06:12 -0700267#define I915_PARAM_HAS_GEM 5
Jesse Barnes0f973f22009-01-26 17:10:45 -0800268#define I915_PARAM_NUM_FENCES_AVAIL 6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269
270typedef struct drm_i915_getparam {
271 int param;
272 int __user *value;
273} drm_i915_getparam_t;
274
275/* Ioctl to set kernel params:
276 */
277#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
278#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
279#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
Jesse Barnes0f973f22009-01-26 17:10:45 -0800280#define I915_SETPARAM_NUM_USED_FENCES 4
Linus Torvalds1da177e2005-04-16 15:20:36 -0700281
282typedef struct drm_i915_setparam {
283 int param;
284 int value;
285} drm_i915_setparam_t;
286
287/* A memory manager for regions of shared memory:
288 */
289#define I915_MEM_REGION_AGP 1
290
291typedef struct drm_i915_mem_alloc {
292 int region;
293 int alignment;
294 int size;
295 int __user *region_offset; /* offset from start of fb or agp */
296} drm_i915_mem_alloc_t;
297
298typedef struct drm_i915_mem_free {
299 int region;
300 int region_offset;
301} drm_i915_mem_free_t;
302
303typedef struct drm_i915_mem_init_heap {
304 int region;
305 int size;
306 int start;
307} drm_i915_mem_init_heap_t;
308
Dave Airliede227f52006-01-25 15:31:43 +1100309/* Allow memory manager to be torn down and re-initialized (eg on
310 * rotate):
311 */
312typedef struct drm_i915_mem_destroy_heap {
313 int region;
314} drm_i915_mem_destroy_heap_t;
315
Dave Airlie702880f2006-06-24 17:07:34 +1000316/* Allow X server to configure which pipes to monitor for vblank signals
317 */
318#define DRM_I915_VBLANK_PIPE_A 1
319#define DRM_I915_VBLANK_PIPE_B 2
320
321typedef struct drm_i915_vblank_pipe {
322 int pipe;
323} drm_i915_vblank_pipe_t;
324
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000325/* Schedule buffer swap at given vertical blank:
326 */
327typedef struct drm_i915_vblank_swap {
328 drm_drawable_t drawable;
Dave Airliec60ce622007-07-11 15:27:12 +1000329 enum drm_vblank_seq_type seqtype;
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000330 unsigned int sequence;
331} drm_i915_vblank_swap_t;
332
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000333typedef struct drm_i915_hws_addr {
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100334 __u64 addr;
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000335} drm_i915_hws_addr_t;
336
Eric Anholt673a3942008-07-30 12:06:12 -0700337struct drm_i915_gem_init {
338 /**
339 * Beginning offset in the GTT to be managed by the DRM memory
340 * manager.
341 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100342 __u64 gtt_start;
Eric Anholt673a3942008-07-30 12:06:12 -0700343 /**
344 * Ending offset in the GTT to be managed by the DRM memory
345 * manager.
346 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100347 __u64 gtt_end;
Eric Anholt673a3942008-07-30 12:06:12 -0700348};
349
350struct drm_i915_gem_create {
351 /**
352 * Requested size for the object.
353 *
354 * The (page-aligned) allocated size for the object will be returned.
355 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100356 __u64 size;
Eric Anholt673a3942008-07-30 12:06:12 -0700357 /**
358 * Returned handle for the object.
359 *
360 * Object handles are nonzero.
361 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100362 __u32 handle;
363 __u32 pad;
Eric Anholt673a3942008-07-30 12:06:12 -0700364};
365
366struct drm_i915_gem_pread {
367 /** Handle for the object being read. */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100368 __u32 handle;
369 __u32 pad;
Eric Anholt673a3942008-07-30 12:06:12 -0700370 /** Offset into the object to read from */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100371 __u64 offset;
Eric Anholt673a3942008-07-30 12:06:12 -0700372 /** Length of data to read */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100373 __u64 size;
Eric Anholt673a3942008-07-30 12:06:12 -0700374 /**
375 * Pointer to write the data into.
376 *
377 * This is a fixed-size type for 32/64 compatibility.
378 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100379 __u64 data_ptr;
Eric Anholt673a3942008-07-30 12:06:12 -0700380};
381
382struct drm_i915_gem_pwrite {
383 /** Handle for the object being written to. */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100384 __u32 handle;
385 __u32 pad;
Eric Anholt673a3942008-07-30 12:06:12 -0700386 /** Offset into the object to write to */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100387 __u64 offset;
Eric Anholt673a3942008-07-30 12:06:12 -0700388 /** Length of data to write */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100389 __u64 size;
Eric Anholt673a3942008-07-30 12:06:12 -0700390 /**
391 * Pointer to read the data from.
392 *
393 * This is a fixed-size type for 32/64 compatibility.
394 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100395 __u64 data_ptr;
Eric Anholt673a3942008-07-30 12:06:12 -0700396};
397
398struct drm_i915_gem_mmap {
399 /** Handle for the object being mapped. */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100400 __u32 handle;
401 __u32 pad;
Eric Anholt673a3942008-07-30 12:06:12 -0700402 /** Offset in the object to map. */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100403 __u64 offset;
Eric Anholt673a3942008-07-30 12:06:12 -0700404 /**
405 * Length of data to map.
406 *
407 * The value will be page-aligned.
408 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100409 __u64 size;
Eric Anholt673a3942008-07-30 12:06:12 -0700410 /**
411 * Returned pointer the data was mapped at.
412 *
413 * This is a fixed-size type for 32/64 compatibility.
414 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100415 __u64 addr_ptr;
Eric Anholt673a3942008-07-30 12:06:12 -0700416};
417
Jesse Barnesde151cf2008-11-12 10:03:55 -0800418struct drm_i915_gem_mmap_gtt {
419 /** Handle for the object being mapped. */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100420 __u32 handle;
421 __u32 pad;
Jesse Barnesde151cf2008-11-12 10:03:55 -0800422 /**
423 * Fake offset to use for subsequent mmap call
424 *
425 * This is a fixed-size type for 32/64 compatibility.
426 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100427 __u64 offset;
Jesse Barnesde151cf2008-11-12 10:03:55 -0800428};
429
Eric Anholt673a3942008-07-30 12:06:12 -0700430struct drm_i915_gem_set_domain {
431 /** Handle for the object */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100432 __u32 handle;
Eric Anholt673a3942008-07-30 12:06:12 -0700433
434 /** New read domains */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100435 __u32 read_domains;
Eric Anholt673a3942008-07-30 12:06:12 -0700436
437 /** New write domain */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100438 __u32 write_domain;
Eric Anholt673a3942008-07-30 12:06:12 -0700439};
440
441struct drm_i915_gem_sw_finish {
442 /** Handle for the object */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100443 __u32 handle;
Eric Anholt673a3942008-07-30 12:06:12 -0700444};
445
446struct drm_i915_gem_relocation_entry {
447 /**
448 * Handle of the buffer being pointed to by this relocation entry.
449 *
450 * It's appealing to make this be an index into the mm_validate_entry
451 * list to refer to the buffer, but this allows the driver to create
452 * a relocation list for state buffers and not re-write it per
453 * exec using the buffer.
454 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100455 __u32 target_handle;
Eric Anholt673a3942008-07-30 12:06:12 -0700456
457 /**
458 * Value to be added to the offset of the target buffer to make up
459 * the relocation entry.
460 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100461 __u32 delta;
Eric Anholt673a3942008-07-30 12:06:12 -0700462
463 /** Offset in the buffer the relocation entry will be written into */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100464 __u64 offset;
Eric Anholt673a3942008-07-30 12:06:12 -0700465
466 /**
467 * Offset value of the target buffer that the relocation entry was last
468 * written as.
469 *
470 * If the buffer has the same offset as last time, we can skip syncing
471 * and writing the relocation. This value is written back out by
472 * the execbuffer ioctl when the relocation is written.
473 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100474 __u64 presumed_offset;
Eric Anholt673a3942008-07-30 12:06:12 -0700475
476 /**
477 * Target memory domains read by this operation.
478 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100479 __u32 read_domains;
Eric Anholt673a3942008-07-30 12:06:12 -0700480
481 /**
482 * Target memory domains written by this operation.
483 *
484 * Note that only one domain may be written by the whole
485 * execbuffer operation, so that where there are conflicts,
486 * the application will get -EINVAL back.
487 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100488 __u32 write_domain;
Eric Anholt673a3942008-07-30 12:06:12 -0700489};
490
491/** @{
492 * Intel memory domains
493 *
494 * Most of these just align with the various caches in
495 * the system and are used to flush and invalidate as
496 * objects end up cached in different domains.
497 */
498/** CPU cache */
499#define I915_GEM_DOMAIN_CPU 0x00000001
500/** Render cache, used by 2D and 3D drawing */
501#define I915_GEM_DOMAIN_RENDER 0x00000002
502/** Sampler cache, used by texture engine */
503#define I915_GEM_DOMAIN_SAMPLER 0x00000004
504/** Command queue, used to load batch buffers */
505#define I915_GEM_DOMAIN_COMMAND 0x00000008
506/** Instruction cache, used by shader programs */
507#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
508/** Vertex address cache */
509#define I915_GEM_DOMAIN_VERTEX 0x00000020
510/** GTT domain - aperture and scanout */
511#define I915_GEM_DOMAIN_GTT 0x00000040
512/** @} */
513
514struct drm_i915_gem_exec_object {
515 /**
516 * User's handle for a buffer to be bound into the GTT for this
517 * operation.
518 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100519 __u32 handle;
Eric Anholt673a3942008-07-30 12:06:12 -0700520
521 /** Number of relocations to be performed on this buffer */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100522 __u32 relocation_count;
Eric Anholt673a3942008-07-30 12:06:12 -0700523 /**
524 * Pointer to array of struct drm_i915_gem_relocation_entry containing
525 * the relocations to be performed in this buffer.
526 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100527 __u64 relocs_ptr;
Eric Anholt673a3942008-07-30 12:06:12 -0700528
529 /** Required alignment in graphics aperture */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100530 __u64 alignment;
Eric Anholt673a3942008-07-30 12:06:12 -0700531
532 /**
533 * Returned value of the updated offset of the object, for future
534 * presumed_offset writes.
535 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100536 __u64 offset;
Eric Anholt673a3942008-07-30 12:06:12 -0700537};
538
539struct drm_i915_gem_execbuffer {
540 /**
541 * List of buffers to be validated with their relocations to be
542 * performend on them.
543 *
544 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
545 *
546 * These buffers must be listed in an order such that all relocations
547 * a buffer is performing refer to buffers that have already appeared
548 * in the validate list.
549 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100550 __u64 buffers_ptr;
551 __u32 buffer_count;
Eric Anholt673a3942008-07-30 12:06:12 -0700552
553 /** Offset in the batchbuffer to start execution from. */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100554 __u32 batch_start_offset;
Eric Anholt673a3942008-07-30 12:06:12 -0700555 /** Bytes used in batchbuffer from batch_start_offset */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100556 __u32 batch_len;
557 __u32 DR1;
558 __u32 DR4;
559 __u32 num_cliprects;
Eric Anholt673a3942008-07-30 12:06:12 -0700560 /** This is a struct drm_clip_rect *cliprects */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100561 __u64 cliprects_ptr;
Eric Anholt673a3942008-07-30 12:06:12 -0700562};
563
564struct drm_i915_gem_pin {
565 /** Handle of the buffer to be pinned. */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100566 __u32 handle;
567 __u32 pad;
Eric Anholt673a3942008-07-30 12:06:12 -0700568
569 /** alignment required within the aperture */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100570 __u64 alignment;
Eric Anholt673a3942008-07-30 12:06:12 -0700571
572 /** Returned GTT offset of the buffer. */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100573 __u64 offset;
Eric Anholt673a3942008-07-30 12:06:12 -0700574};
575
576struct drm_i915_gem_unpin {
577 /** Handle of the buffer to be unpinned. */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100578 __u32 handle;
579 __u32 pad;
Eric Anholt673a3942008-07-30 12:06:12 -0700580};
581
582struct drm_i915_gem_busy {
583 /** Handle of the buffer to check for busy */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100584 __u32 handle;
Eric Anholt673a3942008-07-30 12:06:12 -0700585
586 /** Return busy status (1 if busy, 0 if idle) */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100587 __u32 busy;
Eric Anholt673a3942008-07-30 12:06:12 -0700588};
589
590#define I915_TILING_NONE 0
591#define I915_TILING_X 1
592#define I915_TILING_Y 2
593
594#define I915_BIT_6_SWIZZLE_NONE 0
595#define I915_BIT_6_SWIZZLE_9 1
596#define I915_BIT_6_SWIZZLE_9_10 2
597#define I915_BIT_6_SWIZZLE_9_11 3
598#define I915_BIT_6_SWIZZLE_9_10_11 4
599/* Not seen by userland */
600#define I915_BIT_6_SWIZZLE_UNKNOWN 5
Eric Anholt280b7132009-03-12 16:56:27 -0700601/* Seen by userland. */
602#define I915_BIT_6_SWIZZLE_9_17 6
603#define I915_BIT_6_SWIZZLE_9_10_17 7
Eric Anholt673a3942008-07-30 12:06:12 -0700604
605struct drm_i915_gem_set_tiling {
606 /** Handle of the buffer to have its tiling state updated */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100607 __u32 handle;
Eric Anholt673a3942008-07-30 12:06:12 -0700608
609 /**
610 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
611 * I915_TILING_Y).
612 *
613 * This value is to be set on request, and will be updated by the
614 * kernel on successful return with the actual chosen tiling layout.
615 *
616 * The tiling mode may be demoted to I915_TILING_NONE when the system
617 * has bit 6 swizzling that can't be managed correctly by GEM.
618 *
619 * Buffer contents become undefined when changing tiling_mode.
620 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100621 __u32 tiling_mode;
Eric Anholt673a3942008-07-30 12:06:12 -0700622
623 /**
624 * Stride in bytes for the object when in I915_TILING_X or
625 * I915_TILING_Y.
626 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100627 __u32 stride;
Eric Anholt673a3942008-07-30 12:06:12 -0700628
629 /**
630 * Returned address bit 6 swizzling required for CPU access through
631 * mmap mapping.
632 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100633 __u32 swizzle_mode;
Eric Anholt673a3942008-07-30 12:06:12 -0700634};
635
636struct drm_i915_gem_get_tiling {
637 /** Handle of the buffer to get tiling state for. */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100638 __u32 handle;
Eric Anholt673a3942008-07-30 12:06:12 -0700639
640 /**
641 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
642 * I915_TILING_Y).
643 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100644 __u32 tiling_mode;
Eric Anholt673a3942008-07-30 12:06:12 -0700645
646 /**
647 * Returned address bit 6 swizzling required for CPU access through
648 * mmap mapping.
649 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100650 __u32 swizzle_mode;
Eric Anholt673a3942008-07-30 12:06:12 -0700651};
652
Eric Anholt5a125c32008-10-22 21:40:13 -0700653struct drm_i915_gem_get_aperture {
654 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100655 __u64 aper_size;
Eric Anholt5a125c32008-10-22 21:40:13 -0700656
657 /**
658 * Available space in the aperture used by i915_gem_execbuffer, in
659 * bytes
660 */
Arnd Bergmann1d7f83d2009-02-26 00:51:42 +0100661 __u64 aper_available_size;
Eric Anholt5a125c32008-10-22 21:40:13 -0700662};
663
Carl Worth08d7b3d2009-04-29 14:43:54 -0700664struct drm_i915_get_pipe_from_crtc_id {
665 /** ID of CRTC being requested **/
666 __u32 crtc_id;
667
668 /** pipe of requested CRTC **/
669 __u32 pipe;
670};
671
Chris Wilson3ef94da2009-09-14 16:50:29 +0100672#define I915_MADV_WILLNEED 0
673#define I915_MADV_DONTNEED 1
Chris Wilsonbb6baf72009-09-22 14:24:13 +0100674#define __I915_MADV_PURGED 2 /* internal state */
Chris Wilson3ef94da2009-09-14 16:50:29 +0100675
676struct drm_i915_gem_madvise {
677 /** Handle of the buffer to change the backing store advice */
678 __u32 handle;
679
680 /* Advice: either the buffer will be needed again in the near future,
681 * or wont be and could be discarded under memory pressure.
682 */
683 __u32 madv;
684
685 /** Whether the backing store still exists. */
686 __u32 retained;
687};
688
Linus Torvalds1da177e2005-04-16 15:20:36 -0700689#endif /* _I915_DRM_H_ */