Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1 | /* |
| 2 | * linux/drivers/video/omap2/dss/dsi.c |
| 3 | * |
| 4 | * Copyright (C) 2009 Nokia Corporation |
| 5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License version 2 as published by |
| 9 | * the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 14 | * more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License along with |
| 17 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #define DSS_SUBSYS_NAME "DSI" |
| 21 | |
| 22 | #include <linux/kernel.h> |
| 23 | #include <linux/io.h> |
| 24 | #include <linux/clk.h> |
| 25 | #include <linux/device.h> |
| 26 | #include <linux/err.h> |
| 27 | #include <linux/interrupt.h> |
| 28 | #include <linux/delay.h> |
| 29 | #include <linux/mutex.h> |
Tomi Valkeinen | b9eb5d7 | 2010-01-11 16:33:56 +0200 | [diff] [blame] | 30 | #include <linux/semaphore.h> |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 31 | #include <linux/seq_file.h> |
| 32 | #include <linux/platform_device.h> |
| 33 | #include <linux/regulator/consumer.h> |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 34 | #include <linux/wait.h> |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 35 | #include <linux/workqueue.h> |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 36 | |
| 37 | #include <plat/display.h> |
| 38 | #include <plat/clock.h> |
| 39 | |
| 40 | #include "dss.h" |
| 41 | |
| 42 | /*#define VERBOSE_IRQ*/ |
| 43 | #define DSI_CATCH_MISSING_TE |
| 44 | |
| 45 | #define DSI_BASE 0x4804FC00 |
| 46 | |
| 47 | struct dsi_reg { u16 idx; }; |
| 48 | |
| 49 | #define DSI_REG(idx) ((const struct dsi_reg) { idx }) |
| 50 | |
| 51 | #define DSI_SZ_REGS SZ_1K |
| 52 | /* DSI Protocol Engine */ |
| 53 | |
| 54 | #define DSI_REVISION DSI_REG(0x0000) |
| 55 | #define DSI_SYSCONFIG DSI_REG(0x0010) |
| 56 | #define DSI_SYSSTATUS DSI_REG(0x0014) |
| 57 | #define DSI_IRQSTATUS DSI_REG(0x0018) |
| 58 | #define DSI_IRQENABLE DSI_REG(0x001C) |
| 59 | #define DSI_CTRL DSI_REG(0x0040) |
| 60 | #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048) |
| 61 | #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C) |
| 62 | #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050) |
| 63 | #define DSI_CLK_CTRL DSI_REG(0x0054) |
| 64 | #define DSI_TIMING1 DSI_REG(0x0058) |
| 65 | #define DSI_TIMING2 DSI_REG(0x005C) |
| 66 | #define DSI_VM_TIMING1 DSI_REG(0x0060) |
| 67 | #define DSI_VM_TIMING2 DSI_REG(0x0064) |
| 68 | #define DSI_VM_TIMING3 DSI_REG(0x0068) |
| 69 | #define DSI_CLK_TIMING DSI_REG(0x006C) |
| 70 | #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070) |
| 71 | #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074) |
| 72 | #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078) |
| 73 | #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C) |
| 74 | #define DSI_VM_TIMING4 DSI_REG(0x0080) |
| 75 | #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084) |
| 76 | #define DSI_VM_TIMING5 DSI_REG(0x0088) |
| 77 | #define DSI_VM_TIMING6 DSI_REG(0x008C) |
| 78 | #define DSI_VM_TIMING7 DSI_REG(0x0090) |
| 79 | #define DSI_STOPCLK_TIMING DSI_REG(0x0094) |
| 80 | #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20)) |
| 81 | #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20)) |
| 82 | #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20)) |
| 83 | #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20)) |
| 84 | #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20)) |
| 85 | #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20)) |
| 86 | #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20)) |
| 87 | |
| 88 | /* DSIPHY_SCP */ |
| 89 | |
| 90 | #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000) |
| 91 | #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004) |
| 92 | #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008) |
| 93 | #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014) |
| 94 | |
| 95 | /* DSI_PLL_CTRL_SCP */ |
| 96 | |
| 97 | #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000) |
| 98 | #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004) |
| 99 | #define DSI_PLL_GO DSI_REG(0x300 + 0x0008) |
| 100 | #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C) |
| 101 | #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010) |
| 102 | |
| 103 | #define REG_GET(idx, start, end) \ |
| 104 | FLD_GET(dsi_read_reg(idx), start, end) |
| 105 | |
| 106 | #define REG_FLD_MOD(idx, val, start, end) \ |
| 107 | dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end)) |
| 108 | |
| 109 | /* Global interrupts */ |
| 110 | #define DSI_IRQ_VC0 (1 << 0) |
| 111 | #define DSI_IRQ_VC1 (1 << 1) |
| 112 | #define DSI_IRQ_VC2 (1 << 2) |
| 113 | #define DSI_IRQ_VC3 (1 << 3) |
| 114 | #define DSI_IRQ_WAKEUP (1 << 4) |
| 115 | #define DSI_IRQ_RESYNC (1 << 5) |
| 116 | #define DSI_IRQ_PLL_LOCK (1 << 7) |
| 117 | #define DSI_IRQ_PLL_UNLOCK (1 << 8) |
| 118 | #define DSI_IRQ_PLL_RECALL (1 << 9) |
| 119 | #define DSI_IRQ_COMPLEXIO_ERR (1 << 10) |
| 120 | #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14) |
| 121 | #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15) |
| 122 | #define DSI_IRQ_TE_TRIGGER (1 << 16) |
| 123 | #define DSI_IRQ_ACK_TRIGGER (1 << 17) |
| 124 | #define DSI_IRQ_SYNC_LOST (1 << 18) |
| 125 | #define DSI_IRQ_LDO_POWER_GOOD (1 << 19) |
| 126 | #define DSI_IRQ_TA_TIMEOUT (1 << 20) |
| 127 | #define DSI_IRQ_ERROR_MASK \ |
| 128 | (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \ |
| 129 | DSI_IRQ_TA_TIMEOUT) |
| 130 | #define DSI_IRQ_CHANNEL_MASK 0xf |
| 131 | |
| 132 | /* Virtual channel interrupts */ |
| 133 | #define DSI_VC_IRQ_CS (1 << 0) |
| 134 | #define DSI_VC_IRQ_ECC_CORR (1 << 1) |
| 135 | #define DSI_VC_IRQ_PACKET_SENT (1 << 2) |
| 136 | #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3) |
| 137 | #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4) |
| 138 | #define DSI_VC_IRQ_BTA (1 << 5) |
| 139 | #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6) |
| 140 | #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7) |
| 141 | #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8) |
| 142 | #define DSI_VC_IRQ_ERROR_MASK \ |
| 143 | (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \ |
| 144 | DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \ |
| 145 | DSI_VC_IRQ_FIFO_TX_UDF) |
| 146 | |
| 147 | /* ComplexIO interrupts */ |
| 148 | #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0) |
| 149 | #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1) |
| 150 | #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2) |
| 151 | #define DSI_CIO_IRQ_ERRESC1 (1 << 5) |
| 152 | #define DSI_CIO_IRQ_ERRESC2 (1 << 6) |
| 153 | #define DSI_CIO_IRQ_ERRESC3 (1 << 7) |
| 154 | #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10) |
| 155 | #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11) |
| 156 | #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12) |
| 157 | #define DSI_CIO_IRQ_STATEULPS1 (1 << 15) |
| 158 | #define DSI_CIO_IRQ_STATEULPS2 (1 << 16) |
| 159 | #define DSI_CIO_IRQ_STATEULPS3 (1 << 17) |
| 160 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20) |
| 161 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21) |
| 162 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22) |
| 163 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23) |
| 164 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24) |
| 165 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25) |
| 166 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30) |
| 167 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31) |
Tomi Valkeinen | bbecb50 | 2010-05-10 14:35:33 +0300 | [diff] [blame^] | 168 | #define DSI_CIO_IRQ_ERROR_MASK \ |
| 169 | (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \ |
| 170 | DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \ |
| 171 | DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRCONTROL1 | \ |
| 172 | DSI_CIO_IRQ_ERRCONTROL2 | DSI_CIO_IRQ_ERRCONTROL3 | \ |
| 173 | DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \ |
| 174 | DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \ |
| 175 | DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 176 | |
| 177 | #define DSI_DT_DCS_SHORT_WRITE_0 0x05 |
| 178 | #define DSI_DT_DCS_SHORT_WRITE_1 0x15 |
| 179 | #define DSI_DT_DCS_READ 0x06 |
| 180 | #define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37 |
| 181 | #define DSI_DT_NULL_PACKET 0x09 |
| 182 | #define DSI_DT_DCS_LONG_WRITE 0x39 |
| 183 | |
| 184 | #define DSI_DT_RX_ACK_WITH_ERR 0x02 |
| 185 | #define DSI_DT_RX_DCS_LONG_READ 0x1c |
| 186 | #define DSI_DT_RX_SHORT_READ_1 0x21 |
| 187 | #define DSI_DT_RX_SHORT_READ_2 0x22 |
| 188 | |
| 189 | #define FINT_MAX 2100000 |
| 190 | #define FINT_MIN 750000 |
| 191 | #define REGN_MAX (1 << 7) |
| 192 | #define REGM_MAX ((1 << 11) - 1) |
| 193 | #define REGM3_MAX (1 << 4) |
| 194 | #define REGM4_MAX (1 << 4) |
| 195 | #define LP_DIV_MAX ((1 << 13) - 1) |
| 196 | |
| 197 | enum fifo_size { |
| 198 | DSI_FIFO_SIZE_0 = 0, |
| 199 | DSI_FIFO_SIZE_32 = 1, |
| 200 | DSI_FIFO_SIZE_64 = 2, |
| 201 | DSI_FIFO_SIZE_96 = 3, |
| 202 | DSI_FIFO_SIZE_128 = 4, |
| 203 | }; |
| 204 | |
| 205 | enum dsi_vc_mode { |
| 206 | DSI_VC_MODE_L4 = 0, |
| 207 | DSI_VC_MODE_VP, |
| 208 | }; |
| 209 | |
| 210 | struct dsi_update_region { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 211 | u16 x, y, w, h; |
| 212 | struct omap_dss_device *device; |
| 213 | }; |
| 214 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 215 | struct dsi_irq_stats { |
| 216 | unsigned long last_reset; |
| 217 | unsigned irq_count; |
| 218 | unsigned dsi_irqs[32]; |
| 219 | unsigned vc_irqs[4][32]; |
| 220 | unsigned cio_irqs[32]; |
| 221 | }; |
| 222 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 223 | static struct |
| 224 | { |
| 225 | void __iomem *base; |
| 226 | |
| 227 | struct dsi_clock_info current_cinfo; |
| 228 | |
| 229 | struct regulator *vdds_dsi_reg; |
| 230 | |
| 231 | struct { |
| 232 | enum dsi_vc_mode mode; |
| 233 | struct omap_dss_device *dssdev; |
| 234 | enum fifo_size fifo_size; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 235 | } vc[4]; |
| 236 | |
| 237 | struct mutex lock; |
Tomi Valkeinen | b9eb5d7 | 2010-01-11 16:33:56 +0200 | [diff] [blame] | 238 | struct semaphore bus_lock; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 239 | |
| 240 | unsigned pll_locked; |
| 241 | |
| 242 | struct completion bta_completion; |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 243 | void (*bta_callback)(void); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 244 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 245 | int update_channel; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 246 | struct dsi_update_region update_region; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 247 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 248 | bool te_enabled; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 249 | |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 250 | struct workqueue_struct *workqueue; |
| 251 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 252 | void (*framedone_callback)(int, void *); |
| 253 | void *framedone_data; |
| 254 | |
| 255 | struct delayed_work framedone_timeout_work; |
| 256 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 257 | #ifdef DSI_CATCH_MISSING_TE |
| 258 | struct timer_list te_timer; |
| 259 | #endif |
| 260 | |
| 261 | unsigned long cache_req_pck; |
| 262 | unsigned long cache_clk_freq; |
| 263 | struct dsi_clock_info cache_cinfo; |
| 264 | |
| 265 | u32 errors; |
| 266 | spinlock_t errors_lock; |
| 267 | #ifdef DEBUG |
| 268 | ktime_t perf_setup_time; |
| 269 | ktime_t perf_start_time; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 270 | #endif |
| 271 | int debug_read; |
| 272 | int debug_write; |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 273 | |
| 274 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 275 | spinlock_t irq_stats_lock; |
| 276 | struct dsi_irq_stats irq_stats; |
| 277 | #endif |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 278 | } dsi; |
| 279 | |
| 280 | #ifdef DEBUG |
| 281 | static unsigned int dsi_perf; |
| 282 | module_param_named(dsi_perf, dsi_perf, bool, 0644); |
| 283 | #endif |
| 284 | |
| 285 | static inline void dsi_write_reg(const struct dsi_reg idx, u32 val) |
| 286 | { |
| 287 | __raw_writel(val, dsi.base + idx.idx); |
| 288 | } |
| 289 | |
| 290 | static inline u32 dsi_read_reg(const struct dsi_reg idx) |
| 291 | { |
| 292 | return __raw_readl(dsi.base + idx.idx); |
| 293 | } |
| 294 | |
| 295 | |
| 296 | void dsi_save_context(void) |
| 297 | { |
| 298 | } |
| 299 | |
| 300 | void dsi_restore_context(void) |
| 301 | { |
| 302 | } |
| 303 | |
| 304 | void dsi_bus_lock(void) |
| 305 | { |
Tomi Valkeinen | b9eb5d7 | 2010-01-11 16:33:56 +0200 | [diff] [blame] | 306 | down(&dsi.bus_lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 307 | } |
| 308 | EXPORT_SYMBOL(dsi_bus_lock); |
| 309 | |
| 310 | void dsi_bus_unlock(void) |
| 311 | { |
Tomi Valkeinen | b9eb5d7 | 2010-01-11 16:33:56 +0200 | [diff] [blame] | 312 | up(&dsi.bus_lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 313 | } |
| 314 | EXPORT_SYMBOL(dsi_bus_unlock); |
| 315 | |
Tomi Valkeinen | 4f76502 | 2010-01-18 16:27:52 +0200 | [diff] [blame] | 316 | static bool dsi_bus_is_locked(void) |
| 317 | { |
Tomi Valkeinen | b9eb5d7 | 2010-01-11 16:33:56 +0200 | [diff] [blame] | 318 | return dsi.bus_lock.count == 0; |
Tomi Valkeinen | 4f76502 | 2010-01-18 16:27:52 +0200 | [diff] [blame] | 319 | } |
| 320 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 321 | static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum, |
| 322 | int value) |
| 323 | { |
| 324 | int t = 100000; |
| 325 | |
| 326 | while (REG_GET(idx, bitnum, bitnum) != value) { |
| 327 | if (--t == 0) |
| 328 | return !value; |
| 329 | } |
| 330 | |
| 331 | return value; |
| 332 | } |
| 333 | |
| 334 | #ifdef DEBUG |
| 335 | static void dsi_perf_mark_setup(void) |
| 336 | { |
| 337 | dsi.perf_setup_time = ktime_get(); |
| 338 | } |
| 339 | |
| 340 | static void dsi_perf_mark_start(void) |
| 341 | { |
| 342 | dsi.perf_start_time = ktime_get(); |
| 343 | } |
| 344 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 345 | static void dsi_perf_show(const char *name) |
| 346 | { |
| 347 | ktime_t t, setup_time, trans_time; |
| 348 | u32 total_bytes; |
| 349 | u32 setup_us, trans_us, total_us; |
| 350 | |
| 351 | if (!dsi_perf) |
| 352 | return; |
| 353 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 354 | t = ktime_get(); |
| 355 | |
| 356 | setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time); |
| 357 | setup_us = (u32)ktime_to_us(setup_time); |
| 358 | if (setup_us == 0) |
| 359 | setup_us = 1; |
| 360 | |
| 361 | trans_time = ktime_sub(t, dsi.perf_start_time); |
| 362 | trans_us = (u32)ktime_to_us(trans_time); |
| 363 | if (trans_us == 0) |
| 364 | trans_us = 1; |
| 365 | |
| 366 | total_us = setup_us + trans_us; |
| 367 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 368 | total_bytes = dsi.update_region.w * |
| 369 | dsi.update_region.h * |
| 370 | dsi.update_region.device->ctrl.pixel_size / 8; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 371 | |
Tomi Valkeinen | 1bbb275 | 2010-01-11 16:41:10 +0200 | [diff] [blame] | 372 | printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), " |
| 373 | "%u bytes, %u kbytes/sec\n", |
| 374 | name, |
| 375 | setup_us, |
| 376 | trans_us, |
| 377 | total_us, |
| 378 | 1000*1000 / total_us, |
| 379 | total_bytes, |
| 380 | total_bytes * 1000 / total_us); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 381 | } |
| 382 | #else |
| 383 | #define dsi_perf_mark_setup() |
| 384 | #define dsi_perf_mark_start() |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 385 | #define dsi_perf_show(x) |
| 386 | #endif |
| 387 | |
| 388 | static void print_irq_status(u32 status) |
| 389 | { |
| 390 | #ifndef VERBOSE_IRQ |
| 391 | if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0) |
| 392 | return; |
| 393 | #endif |
| 394 | printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status); |
| 395 | |
| 396 | #define PIS(x) \ |
| 397 | if (status & DSI_IRQ_##x) \ |
| 398 | printk(#x " "); |
| 399 | #ifdef VERBOSE_IRQ |
| 400 | PIS(VC0); |
| 401 | PIS(VC1); |
| 402 | PIS(VC2); |
| 403 | PIS(VC3); |
| 404 | #endif |
| 405 | PIS(WAKEUP); |
| 406 | PIS(RESYNC); |
| 407 | PIS(PLL_LOCK); |
| 408 | PIS(PLL_UNLOCK); |
| 409 | PIS(PLL_RECALL); |
| 410 | PIS(COMPLEXIO_ERR); |
| 411 | PIS(HS_TX_TIMEOUT); |
| 412 | PIS(LP_RX_TIMEOUT); |
| 413 | PIS(TE_TRIGGER); |
| 414 | PIS(ACK_TRIGGER); |
| 415 | PIS(SYNC_LOST); |
| 416 | PIS(LDO_POWER_GOOD); |
| 417 | PIS(TA_TIMEOUT); |
| 418 | #undef PIS |
| 419 | |
| 420 | printk("\n"); |
| 421 | } |
| 422 | |
| 423 | static void print_irq_status_vc(int channel, u32 status) |
| 424 | { |
| 425 | #ifndef VERBOSE_IRQ |
| 426 | if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0) |
| 427 | return; |
| 428 | #endif |
| 429 | printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status); |
| 430 | |
| 431 | #define PIS(x) \ |
| 432 | if (status & DSI_VC_IRQ_##x) \ |
| 433 | printk(#x " "); |
| 434 | PIS(CS); |
| 435 | PIS(ECC_CORR); |
| 436 | #ifdef VERBOSE_IRQ |
| 437 | PIS(PACKET_SENT); |
| 438 | #endif |
| 439 | PIS(FIFO_TX_OVF); |
| 440 | PIS(FIFO_RX_OVF); |
| 441 | PIS(BTA); |
| 442 | PIS(ECC_NO_CORR); |
| 443 | PIS(FIFO_TX_UDF); |
| 444 | PIS(PP_BUSY_CHANGE); |
| 445 | #undef PIS |
| 446 | printk("\n"); |
| 447 | } |
| 448 | |
| 449 | static void print_irq_status_cio(u32 status) |
| 450 | { |
| 451 | printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status); |
| 452 | |
| 453 | #define PIS(x) \ |
| 454 | if (status & DSI_CIO_IRQ_##x) \ |
| 455 | printk(#x " "); |
| 456 | PIS(ERRSYNCESC1); |
| 457 | PIS(ERRSYNCESC2); |
| 458 | PIS(ERRSYNCESC3); |
| 459 | PIS(ERRESC1); |
| 460 | PIS(ERRESC2); |
| 461 | PIS(ERRESC3); |
| 462 | PIS(ERRCONTROL1); |
| 463 | PIS(ERRCONTROL2); |
| 464 | PIS(ERRCONTROL3); |
| 465 | PIS(STATEULPS1); |
| 466 | PIS(STATEULPS2); |
| 467 | PIS(STATEULPS3); |
| 468 | PIS(ERRCONTENTIONLP0_1); |
| 469 | PIS(ERRCONTENTIONLP1_1); |
| 470 | PIS(ERRCONTENTIONLP0_2); |
| 471 | PIS(ERRCONTENTIONLP1_2); |
| 472 | PIS(ERRCONTENTIONLP0_3); |
| 473 | PIS(ERRCONTENTIONLP1_3); |
| 474 | PIS(ULPSACTIVENOT_ALL0); |
| 475 | PIS(ULPSACTIVENOT_ALL1); |
| 476 | #undef PIS |
| 477 | |
| 478 | printk("\n"); |
| 479 | } |
| 480 | |
| 481 | static int debug_irq; |
| 482 | |
| 483 | /* called from dss */ |
| 484 | void dsi_irq_handler(void) |
| 485 | { |
| 486 | u32 irqstatus, vcstatus, ciostatus; |
| 487 | int i; |
| 488 | |
| 489 | irqstatus = dsi_read_reg(DSI_IRQSTATUS); |
| 490 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 491 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 492 | spin_lock(&dsi.irq_stats_lock); |
| 493 | dsi.irq_stats.irq_count++; |
| 494 | dss_collect_irq_stats(irqstatus, dsi.irq_stats.dsi_irqs); |
| 495 | #endif |
| 496 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 497 | if (irqstatus & DSI_IRQ_ERROR_MASK) { |
| 498 | DSSERR("DSI error, irqstatus %x\n", irqstatus); |
| 499 | print_irq_status(irqstatus); |
| 500 | spin_lock(&dsi.errors_lock); |
| 501 | dsi.errors |= irqstatus & DSI_IRQ_ERROR_MASK; |
| 502 | spin_unlock(&dsi.errors_lock); |
| 503 | } else if (debug_irq) { |
| 504 | print_irq_status(irqstatus); |
| 505 | } |
| 506 | |
| 507 | #ifdef DSI_CATCH_MISSING_TE |
| 508 | if (irqstatus & DSI_IRQ_TE_TRIGGER) |
| 509 | del_timer(&dsi.te_timer); |
| 510 | #endif |
| 511 | |
| 512 | for (i = 0; i < 4; ++i) { |
| 513 | if ((irqstatus & (1<<i)) == 0) |
| 514 | continue; |
| 515 | |
| 516 | vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i)); |
| 517 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 518 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 519 | dss_collect_irq_stats(vcstatus, dsi.irq_stats.vc_irqs[i]); |
| 520 | #endif |
| 521 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 522 | if (vcstatus & DSI_VC_IRQ_BTA) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 523 | complete(&dsi.bta_completion); |
| 524 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 525 | if (dsi.bta_callback) |
| 526 | dsi.bta_callback(); |
| 527 | } |
| 528 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 529 | if (vcstatus & DSI_VC_IRQ_ERROR_MASK) { |
| 530 | DSSERR("DSI VC(%d) error, vc irqstatus %x\n", |
| 531 | i, vcstatus); |
| 532 | print_irq_status_vc(i, vcstatus); |
| 533 | } else if (debug_irq) { |
| 534 | print_irq_status_vc(i, vcstatus); |
| 535 | } |
| 536 | |
| 537 | dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus); |
| 538 | /* flush posted write */ |
| 539 | dsi_read_reg(DSI_VC_IRQSTATUS(i)); |
| 540 | } |
| 541 | |
| 542 | if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) { |
| 543 | ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS); |
| 544 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 545 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 546 | dss_collect_irq_stats(ciostatus, dsi.irq_stats.cio_irqs); |
| 547 | #endif |
| 548 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 549 | dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus); |
| 550 | /* flush posted write */ |
| 551 | dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS); |
| 552 | |
Tomi Valkeinen | bbecb50 | 2010-05-10 14:35:33 +0300 | [diff] [blame^] | 553 | if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) { |
| 554 | DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); |
| 555 | print_irq_status_cio(ciostatus); |
| 556 | } else if (debug_irq) { |
| 557 | print_irq_status_cio(ciostatus); |
| 558 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 559 | } |
| 560 | |
| 561 | dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); |
| 562 | /* flush posted write */ |
| 563 | dsi_read_reg(DSI_IRQSTATUS); |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 564 | |
| 565 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 566 | spin_unlock(&dsi.irq_stats_lock); |
| 567 | #endif |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 568 | } |
| 569 | |
| 570 | |
| 571 | static void _dsi_initialize_irq(void) |
| 572 | { |
| 573 | u32 l; |
| 574 | int i; |
| 575 | |
| 576 | /* disable all interrupts */ |
| 577 | dsi_write_reg(DSI_IRQENABLE, 0); |
| 578 | for (i = 0; i < 4; ++i) |
| 579 | dsi_write_reg(DSI_VC_IRQENABLE(i), 0); |
| 580 | dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0); |
| 581 | |
| 582 | /* clear interrupt status */ |
| 583 | l = dsi_read_reg(DSI_IRQSTATUS); |
| 584 | dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK); |
| 585 | |
| 586 | for (i = 0; i < 4; ++i) { |
| 587 | l = dsi_read_reg(DSI_VC_IRQSTATUS(i)); |
| 588 | dsi_write_reg(DSI_VC_IRQSTATUS(i), l); |
| 589 | } |
| 590 | |
| 591 | l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS); |
| 592 | dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l); |
| 593 | |
| 594 | /* enable error irqs */ |
| 595 | l = DSI_IRQ_ERROR_MASK; |
| 596 | #ifdef DSI_CATCH_MISSING_TE |
| 597 | l |= DSI_IRQ_TE_TRIGGER; |
| 598 | #endif |
| 599 | dsi_write_reg(DSI_IRQENABLE, l); |
| 600 | |
| 601 | l = DSI_VC_IRQ_ERROR_MASK; |
| 602 | for (i = 0; i < 4; ++i) |
| 603 | dsi_write_reg(DSI_VC_IRQENABLE(i), l); |
| 604 | |
Tomi Valkeinen | bbecb50 | 2010-05-10 14:35:33 +0300 | [diff] [blame^] | 605 | l = DSI_CIO_IRQ_ERROR_MASK; |
| 606 | dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, l); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 607 | } |
| 608 | |
| 609 | static u32 dsi_get_errors(void) |
| 610 | { |
| 611 | unsigned long flags; |
| 612 | u32 e; |
| 613 | spin_lock_irqsave(&dsi.errors_lock, flags); |
| 614 | e = dsi.errors; |
| 615 | dsi.errors = 0; |
| 616 | spin_unlock_irqrestore(&dsi.errors_lock, flags); |
| 617 | return e; |
| 618 | } |
| 619 | |
| 620 | static void dsi_vc_enable_bta_irq(int channel) |
| 621 | { |
| 622 | u32 l; |
| 623 | |
| 624 | dsi_write_reg(DSI_VC_IRQSTATUS(channel), DSI_VC_IRQ_BTA); |
| 625 | |
| 626 | l = dsi_read_reg(DSI_VC_IRQENABLE(channel)); |
| 627 | l |= DSI_VC_IRQ_BTA; |
| 628 | dsi_write_reg(DSI_VC_IRQENABLE(channel), l); |
| 629 | } |
| 630 | |
| 631 | static void dsi_vc_disable_bta_irq(int channel) |
| 632 | { |
| 633 | u32 l; |
| 634 | |
| 635 | l = dsi_read_reg(DSI_VC_IRQENABLE(channel)); |
| 636 | l &= ~DSI_VC_IRQ_BTA; |
| 637 | dsi_write_reg(DSI_VC_IRQENABLE(channel), l); |
| 638 | } |
| 639 | |
| 640 | /* DSI func clock. this could also be DSI2_PLL_FCLK */ |
| 641 | static inline void enable_clocks(bool enable) |
| 642 | { |
| 643 | if (enable) |
| 644 | dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); |
| 645 | else |
| 646 | dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); |
| 647 | } |
| 648 | |
| 649 | /* source clock for DSI PLL. this could also be PCLKFREE */ |
| 650 | static inline void dsi_enable_pll_clock(bool enable) |
| 651 | { |
| 652 | if (enable) |
| 653 | dss_clk_enable(DSS_CLK_FCK2); |
| 654 | else |
| 655 | dss_clk_disable(DSS_CLK_FCK2); |
| 656 | |
| 657 | if (enable && dsi.pll_locked) { |
| 658 | if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) |
| 659 | DSSERR("cannot lock PLL when enabling clocks\n"); |
| 660 | } |
| 661 | } |
| 662 | |
| 663 | #ifdef DEBUG |
| 664 | static void _dsi_print_reset_status(void) |
| 665 | { |
| 666 | u32 l; |
| 667 | |
| 668 | if (!dss_debug) |
| 669 | return; |
| 670 | |
| 671 | /* A dummy read using the SCP interface to any DSIPHY register is |
| 672 | * required after DSIPHY reset to complete the reset of the DSI complex |
| 673 | * I/O. */ |
| 674 | l = dsi_read_reg(DSI_DSIPHY_CFG5); |
| 675 | |
| 676 | printk(KERN_DEBUG "DSI resets: "); |
| 677 | |
| 678 | l = dsi_read_reg(DSI_PLL_STATUS); |
| 679 | printk("PLL (%d) ", FLD_GET(l, 0, 0)); |
| 680 | |
| 681 | l = dsi_read_reg(DSI_COMPLEXIO_CFG1); |
| 682 | printk("CIO (%d) ", FLD_GET(l, 29, 29)); |
| 683 | |
| 684 | l = dsi_read_reg(DSI_DSIPHY_CFG5); |
| 685 | printk("PHY (%x, %d, %d, %d)\n", |
| 686 | FLD_GET(l, 28, 26), |
| 687 | FLD_GET(l, 29, 29), |
| 688 | FLD_GET(l, 30, 30), |
| 689 | FLD_GET(l, 31, 31)); |
| 690 | } |
| 691 | #else |
| 692 | #define _dsi_print_reset_status() |
| 693 | #endif |
| 694 | |
| 695 | static inline int dsi_if_enable(bool enable) |
| 696 | { |
| 697 | DSSDBG("dsi_if_enable(%d)\n", enable); |
| 698 | |
| 699 | enable = enable ? 1 : 0; |
| 700 | REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */ |
| 701 | |
| 702 | if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) { |
| 703 | DSSERR("Failed to set dsi_if_enable to %d\n", enable); |
| 704 | return -EIO; |
| 705 | } |
| 706 | |
| 707 | return 0; |
| 708 | } |
| 709 | |
| 710 | unsigned long dsi_get_dsi1_pll_rate(void) |
| 711 | { |
| 712 | return dsi.current_cinfo.dsi1_pll_fclk; |
| 713 | } |
| 714 | |
| 715 | static unsigned long dsi_get_dsi2_pll_rate(void) |
| 716 | { |
| 717 | return dsi.current_cinfo.dsi2_pll_fclk; |
| 718 | } |
| 719 | |
| 720 | static unsigned long dsi_get_txbyteclkhs(void) |
| 721 | { |
| 722 | return dsi.current_cinfo.clkin4ddr / 16; |
| 723 | } |
| 724 | |
| 725 | static unsigned long dsi_fclk_rate(void) |
| 726 | { |
| 727 | unsigned long r; |
| 728 | |
Tomi Valkeinen | 63cf28a | 2010-02-23 17:40:00 +0200 | [diff] [blame] | 729 | if (dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 730 | /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */ |
| 731 | r = dss_clk_get_rate(DSS_CLK_FCK1); |
| 732 | } else { |
| 733 | /* DSI FCLK source is DSI2_PLL_FCLK */ |
| 734 | r = dsi_get_dsi2_pll_rate(); |
| 735 | } |
| 736 | |
| 737 | return r; |
| 738 | } |
| 739 | |
| 740 | static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev) |
| 741 | { |
| 742 | unsigned long dsi_fclk; |
| 743 | unsigned lp_clk_div; |
| 744 | unsigned long lp_clk; |
| 745 | |
| 746 | lp_clk_div = dssdev->phy.dsi.div.lp_clk_div; |
| 747 | |
| 748 | if (lp_clk_div == 0 || lp_clk_div > LP_DIV_MAX) |
| 749 | return -EINVAL; |
| 750 | |
| 751 | dsi_fclk = dsi_fclk_rate(); |
| 752 | |
| 753 | lp_clk = dsi_fclk / 2 / lp_clk_div; |
| 754 | |
| 755 | DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk); |
| 756 | dsi.current_cinfo.lp_clk = lp_clk; |
| 757 | dsi.current_cinfo.lp_clk_div = lp_clk_div; |
| 758 | |
| 759 | REG_FLD_MOD(DSI_CLK_CTRL, lp_clk_div, 12, 0); /* LP_CLK_DIVISOR */ |
| 760 | |
| 761 | REG_FLD_MOD(DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, |
| 762 | 21, 21); /* LP_RX_SYNCHRO_ENABLE */ |
| 763 | |
| 764 | return 0; |
| 765 | } |
| 766 | |
| 767 | |
| 768 | enum dsi_pll_power_state { |
| 769 | DSI_PLL_POWER_OFF = 0x0, |
| 770 | DSI_PLL_POWER_ON_HSCLK = 0x1, |
| 771 | DSI_PLL_POWER_ON_ALL = 0x2, |
| 772 | DSI_PLL_POWER_ON_DIV = 0x3, |
| 773 | }; |
| 774 | |
| 775 | static int dsi_pll_power(enum dsi_pll_power_state state) |
| 776 | { |
| 777 | int t = 0; |
| 778 | |
| 779 | REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */ |
| 780 | |
| 781 | /* PLL_PWR_STATUS */ |
| 782 | while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) { |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 783 | if (++t > 1000) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 784 | DSSERR("Failed to set DSI PLL power mode to %d\n", |
| 785 | state); |
| 786 | return -ENODEV; |
| 787 | } |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 788 | udelay(1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 789 | } |
| 790 | |
| 791 | return 0; |
| 792 | } |
| 793 | |
| 794 | /* calculate clock rates using dividers in cinfo */ |
| 795 | static int dsi_calc_clock_rates(struct dsi_clock_info *cinfo) |
| 796 | { |
| 797 | if (cinfo->regn == 0 || cinfo->regn > REGN_MAX) |
| 798 | return -EINVAL; |
| 799 | |
| 800 | if (cinfo->regm == 0 || cinfo->regm > REGM_MAX) |
| 801 | return -EINVAL; |
| 802 | |
| 803 | if (cinfo->regm3 > REGM3_MAX) |
| 804 | return -EINVAL; |
| 805 | |
| 806 | if (cinfo->regm4 > REGM4_MAX) |
| 807 | return -EINVAL; |
| 808 | |
| 809 | if (cinfo->use_dss2_fck) { |
| 810 | cinfo->clkin = dss_clk_get_rate(DSS_CLK_FCK2); |
| 811 | /* XXX it is unclear if highfreq should be used |
| 812 | * with DSS2_FCK source also */ |
| 813 | cinfo->highfreq = 0; |
| 814 | } else { |
| 815 | cinfo->clkin = dispc_pclk_rate(); |
| 816 | |
| 817 | if (cinfo->clkin < 32000000) |
| 818 | cinfo->highfreq = 0; |
| 819 | else |
| 820 | cinfo->highfreq = 1; |
| 821 | } |
| 822 | |
| 823 | cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1)); |
| 824 | |
| 825 | if (cinfo->fint > FINT_MAX || cinfo->fint < FINT_MIN) |
| 826 | return -EINVAL; |
| 827 | |
| 828 | cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint; |
| 829 | |
| 830 | if (cinfo->clkin4ddr > 1800 * 1000 * 1000) |
| 831 | return -EINVAL; |
| 832 | |
| 833 | if (cinfo->regm3 > 0) |
| 834 | cinfo->dsi1_pll_fclk = cinfo->clkin4ddr / cinfo->regm3; |
| 835 | else |
| 836 | cinfo->dsi1_pll_fclk = 0; |
| 837 | |
| 838 | if (cinfo->regm4 > 0) |
| 839 | cinfo->dsi2_pll_fclk = cinfo->clkin4ddr / cinfo->regm4; |
| 840 | else |
| 841 | cinfo->dsi2_pll_fclk = 0; |
| 842 | |
| 843 | return 0; |
| 844 | } |
| 845 | |
| 846 | int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck, |
| 847 | struct dsi_clock_info *dsi_cinfo, |
| 848 | struct dispc_clock_info *dispc_cinfo) |
| 849 | { |
| 850 | struct dsi_clock_info cur, best; |
| 851 | struct dispc_clock_info best_dispc; |
| 852 | int min_fck_per_pck; |
| 853 | int match = 0; |
| 854 | unsigned long dss_clk_fck2; |
| 855 | |
| 856 | dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_FCK2); |
| 857 | |
| 858 | if (req_pck == dsi.cache_req_pck && |
| 859 | dsi.cache_cinfo.clkin == dss_clk_fck2) { |
| 860 | DSSDBG("DSI clock info found from cache\n"); |
| 861 | *dsi_cinfo = dsi.cache_cinfo; |
| 862 | dispc_find_clk_divs(is_tft, req_pck, dsi_cinfo->dsi1_pll_fclk, |
| 863 | dispc_cinfo); |
| 864 | return 0; |
| 865 | } |
| 866 | |
| 867 | min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; |
| 868 | |
| 869 | if (min_fck_per_pck && |
| 870 | req_pck * min_fck_per_pck > DISPC_MAX_FCK) { |
| 871 | DSSERR("Requested pixel clock not possible with the current " |
| 872 | "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " |
| 873 | "the constraint off.\n"); |
| 874 | min_fck_per_pck = 0; |
| 875 | } |
| 876 | |
| 877 | DSSDBG("dsi_pll_calc\n"); |
| 878 | |
| 879 | retry: |
| 880 | memset(&best, 0, sizeof(best)); |
| 881 | memset(&best_dispc, 0, sizeof(best_dispc)); |
| 882 | |
| 883 | memset(&cur, 0, sizeof(cur)); |
| 884 | cur.clkin = dss_clk_fck2; |
| 885 | cur.use_dss2_fck = 1; |
| 886 | cur.highfreq = 0; |
| 887 | |
| 888 | /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */ |
| 889 | /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */ |
| 890 | /* To reduce PLL lock time, keep Fint high (around 2 MHz) */ |
| 891 | for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) { |
| 892 | if (cur.highfreq == 0) |
| 893 | cur.fint = cur.clkin / cur.regn; |
| 894 | else |
| 895 | cur.fint = cur.clkin / (2 * cur.regn); |
| 896 | |
| 897 | if (cur.fint > FINT_MAX || cur.fint < FINT_MIN) |
| 898 | continue; |
| 899 | |
| 900 | /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */ |
| 901 | for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) { |
| 902 | unsigned long a, b; |
| 903 | |
| 904 | a = 2 * cur.regm * (cur.clkin/1000); |
| 905 | b = cur.regn * (cur.highfreq + 1); |
| 906 | cur.clkin4ddr = a / b * 1000; |
| 907 | |
| 908 | if (cur.clkin4ddr > 1800 * 1000 * 1000) |
| 909 | break; |
| 910 | |
| 911 | /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */ |
| 912 | for (cur.regm3 = 1; cur.regm3 < REGM3_MAX; |
| 913 | ++cur.regm3) { |
| 914 | struct dispc_clock_info cur_dispc; |
| 915 | cur.dsi1_pll_fclk = cur.clkin4ddr / cur.regm3; |
| 916 | |
| 917 | /* this will narrow down the search a bit, |
| 918 | * but still give pixclocks below what was |
| 919 | * requested */ |
| 920 | if (cur.dsi1_pll_fclk < req_pck) |
| 921 | break; |
| 922 | |
| 923 | if (cur.dsi1_pll_fclk > DISPC_MAX_FCK) |
| 924 | continue; |
| 925 | |
| 926 | if (min_fck_per_pck && |
| 927 | cur.dsi1_pll_fclk < |
| 928 | req_pck * min_fck_per_pck) |
| 929 | continue; |
| 930 | |
| 931 | match = 1; |
| 932 | |
| 933 | dispc_find_clk_divs(is_tft, req_pck, |
| 934 | cur.dsi1_pll_fclk, |
| 935 | &cur_dispc); |
| 936 | |
| 937 | if (abs(cur_dispc.pck - req_pck) < |
| 938 | abs(best_dispc.pck - req_pck)) { |
| 939 | best = cur; |
| 940 | best_dispc = cur_dispc; |
| 941 | |
| 942 | if (cur_dispc.pck == req_pck) |
| 943 | goto found; |
| 944 | } |
| 945 | } |
| 946 | } |
| 947 | } |
| 948 | found: |
| 949 | if (!match) { |
| 950 | if (min_fck_per_pck) { |
| 951 | DSSERR("Could not find suitable clock settings.\n" |
| 952 | "Turning FCK/PCK constraint off and" |
| 953 | "trying again.\n"); |
| 954 | min_fck_per_pck = 0; |
| 955 | goto retry; |
| 956 | } |
| 957 | |
| 958 | DSSERR("Could not find suitable clock settings.\n"); |
| 959 | |
| 960 | return -EINVAL; |
| 961 | } |
| 962 | |
| 963 | /* DSI2_PLL_FCLK (regm4) is not used */ |
| 964 | best.regm4 = 0; |
| 965 | best.dsi2_pll_fclk = 0; |
| 966 | |
| 967 | if (dsi_cinfo) |
| 968 | *dsi_cinfo = best; |
| 969 | if (dispc_cinfo) |
| 970 | *dispc_cinfo = best_dispc; |
| 971 | |
| 972 | dsi.cache_req_pck = req_pck; |
| 973 | dsi.cache_clk_freq = 0; |
| 974 | dsi.cache_cinfo = best; |
| 975 | |
| 976 | return 0; |
| 977 | } |
| 978 | |
| 979 | int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo) |
| 980 | { |
| 981 | int r = 0; |
| 982 | u32 l; |
| 983 | int f; |
| 984 | |
| 985 | DSSDBGF(); |
| 986 | |
| 987 | dsi.current_cinfo.fint = cinfo->fint; |
| 988 | dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr; |
| 989 | dsi.current_cinfo.dsi1_pll_fclk = cinfo->dsi1_pll_fclk; |
| 990 | dsi.current_cinfo.dsi2_pll_fclk = cinfo->dsi2_pll_fclk; |
| 991 | |
| 992 | dsi.current_cinfo.regn = cinfo->regn; |
| 993 | dsi.current_cinfo.regm = cinfo->regm; |
| 994 | dsi.current_cinfo.regm3 = cinfo->regm3; |
| 995 | dsi.current_cinfo.regm4 = cinfo->regm4; |
| 996 | |
| 997 | DSSDBG("DSI Fint %ld\n", cinfo->fint); |
| 998 | |
| 999 | DSSDBG("clkin (%s) rate %ld, highfreq %d\n", |
| 1000 | cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree", |
| 1001 | cinfo->clkin, |
| 1002 | cinfo->highfreq); |
| 1003 | |
| 1004 | /* DSIPHY == CLKIN4DDR */ |
| 1005 | DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n", |
| 1006 | cinfo->regm, |
| 1007 | cinfo->regn, |
| 1008 | cinfo->clkin, |
| 1009 | cinfo->highfreq + 1, |
| 1010 | cinfo->clkin4ddr); |
| 1011 | |
| 1012 | DSSDBG("Data rate on 1 DSI lane %ld Mbps\n", |
| 1013 | cinfo->clkin4ddr / 1000 / 1000 / 2); |
| 1014 | |
| 1015 | DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4); |
| 1016 | |
| 1017 | DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n", |
| 1018 | cinfo->regm3, cinfo->dsi1_pll_fclk); |
| 1019 | DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n", |
| 1020 | cinfo->regm4, cinfo->dsi2_pll_fclk); |
| 1021 | |
| 1022 | REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */ |
| 1023 | |
| 1024 | l = dsi_read_reg(DSI_PLL_CONFIGURATION1); |
| 1025 | l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */ |
| 1026 | l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */ |
| 1027 | l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */ |
| 1028 | l = FLD_MOD(l, cinfo->regm3 > 0 ? cinfo->regm3 - 1 : 0, |
| 1029 | 22, 19); /* DSI_CLOCK_DIV */ |
| 1030 | l = FLD_MOD(l, cinfo->regm4 > 0 ? cinfo->regm4 - 1 : 0, |
| 1031 | 26, 23); /* DSIPROTO_CLOCK_DIV */ |
| 1032 | dsi_write_reg(DSI_PLL_CONFIGURATION1, l); |
| 1033 | |
| 1034 | BUG_ON(cinfo->fint < 750000 || cinfo->fint > 2100000); |
| 1035 | if (cinfo->fint < 1000000) |
| 1036 | f = 0x3; |
| 1037 | else if (cinfo->fint < 1250000) |
| 1038 | f = 0x4; |
| 1039 | else if (cinfo->fint < 1500000) |
| 1040 | f = 0x5; |
| 1041 | else if (cinfo->fint < 1750000) |
| 1042 | f = 0x6; |
| 1043 | else |
| 1044 | f = 0x7; |
| 1045 | |
| 1046 | l = dsi_read_reg(DSI_PLL_CONFIGURATION2); |
| 1047 | l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */ |
| 1048 | l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1, |
| 1049 | 11, 11); /* DSI_PLL_CLKSEL */ |
| 1050 | l = FLD_MOD(l, cinfo->highfreq, |
| 1051 | 12, 12); /* DSI_PLL_HIGHFREQ */ |
| 1052 | l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ |
| 1053 | l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */ |
| 1054 | l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */ |
| 1055 | dsi_write_reg(DSI_PLL_CONFIGURATION2, l); |
| 1056 | |
| 1057 | REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */ |
| 1058 | |
| 1059 | if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) { |
| 1060 | DSSERR("dsi pll go bit not going down.\n"); |
| 1061 | r = -EIO; |
| 1062 | goto err; |
| 1063 | } |
| 1064 | |
| 1065 | if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) { |
| 1066 | DSSERR("cannot lock PLL\n"); |
| 1067 | r = -EIO; |
| 1068 | goto err; |
| 1069 | } |
| 1070 | |
| 1071 | dsi.pll_locked = 1; |
| 1072 | |
| 1073 | l = dsi_read_reg(DSI_PLL_CONFIGURATION2); |
| 1074 | l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */ |
| 1075 | l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */ |
| 1076 | l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */ |
| 1077 | l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */ |
| 1078 | l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */ |
| 1079 | l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */ |
| 1080 | l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ |
| 1081 | l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */ |
| 1082 | l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */ |
| 1083 | l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */ |
| 1084 | l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */ |
| 1085 | l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */ |
| 1086 | l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */ |
| 1087 | l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */ |
| 1088 | dsi_write_reg(DSI_PLL_CONFIGURATION2, l); |
| 1089 | |
| 1090 | DSSDBG("PLL config done\n"); |
| 1091 | err: |
| 1092 | return r; |
| 1093 | } |
| 1094 | |
| 1095 | int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk, |
| 1096 | bool enable_hsdiv) |
| 1097 | { |
| 1098 | int r = 0; |
| 1099 | enum dsi_pll_power_state pwstate; |
| 1100 | |
| 1101 | DSSDBG("PLL init\n"); |
| 1102 | |
| 1103 | enable_clocks(1); |
| 1104 | dsi_enable_pll_clock(1); |
| 1105 | |
| 1106 | r = regulator_enable(dsi.vdds_dsi_reg); |
| 1107 | if (r) |
| 1108 | goto err0; |
| 1109 | |
| 1110 | /* XXX PLL does not come out of reset without this... */ |
| 1111 | dispc_pck_free_enable(1); |
| 1112 | |
| 1113 | if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) { |
| 1114 | DSSERR("PLL not coming out of reset.\n"); |
| 1115 | r = -ENODEV; |
Ville Syrjälä | 481dfa0 | 2010-04-22 22:50:04 +0200 | [diff] [blame] | 1116 | dispc_pck_free_enable(0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1117 | goto err1; |
| 1118 | } |
| 1119 | |
| 1120 | /* XXX ... but if left on, we get problems when planes do not |
| 1121 | * fill the whole display. No idea about this */ |
| 1122 | dispc_pck_free_enable(0); |
| 1123 | |
| 1124 | if (enable_hsclk && enable_hsdiv) |
| 1125 | pwstate = DSI_PLL_POWER_ON_ALL; |
| 1126 | else if (enable_hsclk) |
| 1127 | pwstate = DSI_PLL_POWER_ON_HSCLK; |
| 1128 | else if (enable_hsdiv) |
| 1129 | pwstate = DSI_PLL_POWER_ON_DIV; |
| 1130 | else |
| 1131 | pwstate = DSI_PLL_POWER_OFF; |
| 1132 | |
| 1133 | r = dsi_pll_power(pwstate); |
| 1134 | |
| 1135 | if (r) |
| 1136 | goto err1; |
| 1137 | |
| 1138 | DSSDBG("PLL init done\n"); |
| 1139 | |
| 1140 | return 0; |
| 1141 | err1: |
| 1142 | regulator_disable(dsi.vdds_dsi_reg); |
| 1143 | err0: |
| 1144 | enable_clocks(0); |
| 1145 | dsi_enable_pll_clock(0); |
| 1146 | return r; |
| 1147 | } |
| 1148 | |
| 1149 | void dsi_pll_uninit(void) |
| 1150 | { |
| 1151 | enable_clocks(0); |
| 1152 | dsi_enable_pll_clock(0); |
| 1153 | |
| 1154 | dsi.pll_locked = 0; |
| 1155 | dsi_pll_power(DSI_PLL_POWER_OFF); |
| 1156 | regulator_disable(dsi.vdds_dsi_reg); |
| 1157 | DSSDBG("PLL uninit done\n"); |
| 1158 | } |
| 1159 | |
| 1160 | void dsi_dump_clocks(struct seq_file *s) |
| 1161 | { |
| 1162 | int clksel; |
| 1163 | struct dsi_clock_info *cinfo = &dsi.current_cinfo; |
| 1164 | |
| 1165 | enable_clocks(1); |
| 1166 | |
| 1167 | clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11); |
| 1168 | |
| 1169 | seq_printf(s, "- DSI PLL -\n"); |
| 1170 | |
| 1171 | seq_printf(s, "dsi pll source = %s\n", |
| 1172 | clksel == 0 ? |
| 1173 | "dss2_alwon_fclk" : "pclkfree"); |
| 1174 | |
| 1175 | seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn); |
| 1176 | |
| 1177 | seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n", |
| 1178 | cinfo->clkin4ddr, cinfo->regm); |
| 1179 | |
| 1180 | seq_printf(s, "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n", |
| 1181 | cinfo->dsi1_pll_fclk, |
| 1182 | cinfo->regm3, |
Tomi Valkeinen | 63cf28a | 2010-02-23 17:40:00 +0200 | [diff] [blame] | 1183 | dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ? |
| 1184 | "off" : "on"); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1185 | |
| 1186 | seq_printf(s, "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n", |
| 1187 | cinfo->dsi2_pll_fclk, |
| 1188 | cinfo->regm4, |
Tomi Valkeinen | 63cf28a | 2010-02-23 17:40:00 +0200 | [diff] [blame] | 1189 | dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ? |
| 1190 | "off" : "on"); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1191 | |
| 1192 | seq_printf(s, "- DSI -\n"); |
| 1193 | |
| 1194 | seq_printf(s, "dsi fclk source = %s\n", |
Tomi Valkeinen | 63cf28a | 2010-02-23 17:40:00 +0200 | [diff] [blame] | 1195 | dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ? |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1196 | "dss1_alwon_fclk" : "dsi2_pll_fclk"); |
| 1197 | |
| 1198 | seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate()); |
| 1199 | |
| 1200 | seq_printf(s, "DDR_CLK\t\t%lu\n", |
| 1201 | cinfo->clkin4ddr / 4); |
| 1202 | |
| 1203 | seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs()); |
| 1204 | |
| 1205 | seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk); |
| 1206 | |
| 1207 | seq_printf(s, "VP_CLK\t\t%lu\n" |
| 1208 | "VP_PCLK\t\t%lu\n", |
| 1209 | dispc_lclk_rate(), |
| 1210 | dispc_pclk_rate()); |
| 1211 | |
| 1212 | enable_clocks(0); |
| 1213 | } |
| 1214 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 1215 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 1216 | void dsi_dump_irqs(struct seq_file *s) |
| 1217 | { |
| 1218 | unsigned long flags; |
| 1219 | struct dsi_irq_stats stats; |
| 1220 | |
| 1221 | spin_lock_irqsave(&dsi.irq_stats_lock, flags); |
| 1222 | |
| 1223 | stats = dsi.irq_stats; |
| 1224 | memset(&dsi.irq_stats, 0, sizeof(dsi.irq_stats)); |
| 1225 | dsi.irq_stats.last_reset = jiffies; |
| 1226 | |
| 1227 | spin_unlock_irqrestore(&dsi.irq_stats_lock, flags); |
| 1228 | |
| 1229 | seq_printf(s, "period %u ms\n", |
| 1230 | jiffies_to_msecs(jiffies - stats.last_reset)); |
| 1231 | |
| 1232 | seq_printf(s, "irqs %d\n", stats.irq_count); |
| 1233 | #define PIS(x) \ |
| 1234 | seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]); |
| 1235 | |
| 1236 | seq_printf(s, "-- DSI interrupts --\n"); |
| 1237 | PIS(VC0); |
| 1238 | PIS(VC1); |
| 1239 | PIS(VC2); |
| 1240 | PIS(VC3); |
| 1241 | PIS(WAKEUP); |
| 1242 | PIS(RESYNC); |
| 1243 | PIS(PLL_LOCK); |
| 1244 | PIS(PLL_UNLOCK); |
| 1245 | PIS(PLL_RECALL); |
| 1246 | PIS(COMPLEXIO_ERR); |
| 1247 | PIS(HS_TX_TIMEOUT); |
| 1248 | PIS(LP_RX_TIMEOUT); |
| 1249 | PIS(TE_TRIGGER); |
| 1250 | PIS(ACK_TRIGGER); |
| 1251 | PIS(SYNC_LOST); |
| 1252 | PIS(LDO_POWER_GOOD); |
| 1253 | PIS(TA_TIMEOUT); |
| 1254 | #undef PIS |
| 1255 | |
| 1256 | #define PIS(x) \ |
| 1257 | seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \ |
| 1258 | stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \ |
| 1259 | stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \ |
| 1260 | stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \ |
| 1261 | stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]); |
| 1262 | |
| 1263 | seq_printf(s, "-- VC interrupts --\n"); |
| 1264 | PIS(CS); |
| 1265 | PIS(ECC_CORR); |
| 1266 | PIS(PACKET_SENT); |
| 1267 | PIS(FIFO_TX_OVF); |
| 1268 | PIS(FIFO_RX_OVF); |
| 1269 | PIS(BTA); |
| 1270 | PIS(ECC_NO_CORR); |
| 1271 | PIS(FIFO_TX_UDF); |
| 1272 | PIS(PP_BUSY_CHANGE); |
| 1273 | #undef PIS |
| 1274 | |
| 1275 | #define PIS(x) \ |
| 1276 | seq_printf(s, "%-20s %10d\n", #x, \ |
| 1277 | stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]); |
| 1278 | |
| 1279 | seq_printf(s, "-- CIO interrupts --\n"); |
| 1280 | PIS(ERRSYNCESC1); |
| 1281 | PIS(ERRSYNCESC2); |
| 1282 | PIS(ERRSYNCESC3); |
| 1283 | PIS(ERRESC1); |
| 1284 | PIS(ERRESC2); |
| 1285 | PIS(ERRESC3); |
| 1286 | PIS(ERRCONTROL1); |
| 1287 | PIS(ERRCONTROL2); |
| 1288 | PIS(ERRCONTROL3); |
| 1289 | PIS(STATEULPS1); |
| 1290 | PIS(STATEULPS2); |
| 1291 | PIS(STATEULPS3); |
| 1292 | PIS(ERRCONTENTIONLP0_1); |
| 1293 | PIS(ERRCONTENTIONLP1_1); |
| 1294 | PIS(ERRCONTENTIONLP0_2); |
| 1295 | PIS(ERRCONTENTIONLP1_2); |
| 1296 | PIS(ERRCONTENTIONLP0_3); |
| 1297 | PIS(ERRCONTENTIONLP1_3); |
| 1298 | PIS(ULPSACTIVENOT_ALL0); |
| 1299 | PIS(ULPSACTIVENOT_ALL1); |
| 1300 | #undef PIS |
| 1301 | } |
| 1302 | #endif |
| 1303 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1304 | void dsi_dump_regs(struct seq_file *s) |
| 1305 | { |
| 1306 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r)) |
| 1307 | |
| 1308 | dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); |
| 1309 | |
| 1310 | DUMPREG(DSI_REVISION); |
| 1311 | DUMPREG(DSI_SYSCONFIG); |
| 1312 | DUMPREG(DSI_SYSSTATUS); |
| 1313 | DUMPREG(DSI_IRQSTATUS); |
| 1314 | DUMPREG(DSI_IRQENABLE); |
| 1315 | DUMPREG(DSI_CTRL); |
| 1316 | DUMPREG(DSI_COMPLEXIO_CFG1); |
| 1317 | DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); |
| 1318 | DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); |
| 1319 | DUMPREG(DSI_CLK_CTRL); |
| 1320 | DUMPREG(DSI_TIMING1); |
| 1321 | DUMPREG(DSI_TIMING2); |
| 1322 | DUMPREG(DSI_VM_TIMING1); |
| 1323 | DUMPREG(DSI_VM_TIMING2); |
| 1324 | DUMPREG(DSI_VM_TIMING3); |
| 1325 | DUMPREG(DSI_CLK_TIMING); |
| 1326 | DUMPREG(DSI_TX_FIFO_VC_SIZE); |
| 1327 | DUMPREG(DSI_RX_FIFO_VC_SIZE); |
| 1328 | DUMPREG(DSI_COMPLEXIO_CFG2); |
| 1329 | DUMPREG(DSI_RX_FIFO_VC_FULLNESS); |
| 1330 | DUMPREG(DSI_VM_TIMING4); |
| 1331 | DUMPREG(DSI_TX_FIFO_VC_EMPTINESS); |
| 1332 | DUMPREG(DSI_VM_TIMING5); |
| 1333 | DUMPREG(DSI_VM_TIMING6); |
| 1334 | DUMPREG(DSI_VM_TIMING7); |
| 1335 | DUMPREG(DSI_STOPCLK_TIMING); |
| 1336 | |
| 1337 | DUMPREG(DSI_VC_CTRL(0)); |
| 1338 | DUMPREG(DSI_VC_TE(0)); |
| 1339 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(0)); |
| 1340 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0)); |
| 1341 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0)); |
| 1342 | DUMPREG(DSI_VC_IRQSTATUS(0)); |
| 1343 | DUMPREG(DSI_VC_IRQENABLE(0)); |
| 1344 | |
| 1345 | DUMPREG(DSI_VC_CTRL(1)); |
| 1346 | DUMPREG(DSI_VC_TE(1)); |
| 1347 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(1)); |
| 1348 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1)); |
| 1349 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1)); |
| 1350 | DUMPREG(DSI_VC_IRQSTATUS(1)); |
| 1351 | DUMPREG(DSI_VC_IRQENABLE(1)); |
| 1352 | |
| 1353 | DUMPREG(DSI_VC_CTRL(2)); |
| 1354 | DUMPREG(DSI_VC_TE(2)); |
| 1355 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(2)); |
| 1356 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2)); |
| 1357 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2)); |
| 1358 | DUMPREG(DSI_VC_IRQSTATUS(2)); |
| 1359 | DUMPREG(DSI_VC_IRQENABLE(2)); |
| 1360 | |
| 1361 | DUMPREG(DSI_VC_CTRL(3)); |
| 1362 | DUMPREG(DSI_VC_TE(3)); |
| 1363 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(3)); |
| 1364 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3)); |
| 1365 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3)); |
| 1366 | DUMPREG(DSI_VC_IRQSTATUS(3)); |
| 1367 | DUMPREG(DSI_VC_IRQENABLE(3)); |
| 1368 | |
| 1369 | DUMPREG(DSI_DSIPHY_CFG0); |
| 1370 | DUMPREG(DSI_DSIPHY_CFG1); |
| 1371 | DUMPREG(DSI_DSIPHY_CFG2); |
| 1372 | DUMPREG(DSI_DSIPHY_CFG5); |
| 1373 | |
| 1374 | DUMPREG(DSI_PLL_CONTROL); |
| 1375 | DUMPREG(DSI_PLL_STATUS); |
| 1376 | DUMPREG(DSI_PLL_GO); |
| 1377 | DUMPREG(DSI_PLL_CONFIGURATION1); |
| 1378 | DUMPREG(DSI_PLL_CONFIGURATION2); |
| 1379 | |
| 1380 | dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); |
| 1381 | #undef DUMPREG |
| 1382 | } |
| 1383 | |
| 1384 | enum dsi_complexio_power_state { |
| 1385 | DSI_COMPLEXIO_POWER_OFF = 0x0, |
| 1386 | DSI_COMPLEXIO_POWER_ON = 0x1, |
| 1387 | DSI_COMPLEXIO_POWER_ULPS = 0x2, |
| 1388 | }; |
| 1389 | |
| 1390 | static int dsi_complexio_power(enum dsi_complexio_power_state state) |
| 1391 | { |
| 1392 | int t = 0; |
| 1393 | |
| 1394 | /* PWR_CMD */ |
| 1395 | REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27); |
| 1396 | |
| 1397 | /* PWR_STATUS */ |
| 1398 | while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) { |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 1399 | if (++t > 1000) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1400 | DSSERR("failed to set complexio power state to " |
| 1401 | "%d\n", state); |
| 1402 | return -ENODEV; |
| 1403 | } |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 1404 | udelay(1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1405 | } |
| 1406 | |
| 1407 | return 0; |
| 1408 | } |
| 1409 | |
| 1410 | static void dsi_complexio_config(struct omap_dss_device *dssdev) |
| 1411 | { |
| 1412 | u32 r; |
| 1413 | |
| 1414 | int clk_lane = dssdev->phy.dsi.clk_lane; |
| 1415 | int data1_lane = dssdev->phy.dsi.data1_lane; |
| 1416 | int data2_lane = dssdev->phy.dsi.data2_lane; |
| 1417 | int clk_pol = dssdev->phy.dsi.clk_pol; |
| 1418 | int data1_pol = dssdev->phy.dsi.data1_pol; |
| 1419 | int data2_pol = dssdev->phy.dsi.data2_pol; |
| 1420 | |
| 1421 | r = dsi_read_reg(DSI_COMPLEXIO_CFG1); |
| 1422 | r = FLD_MOD(r, clk_lane, 2, 0); |
| 1423 | r = FLD_MOD(r, clk_pol, 3, 3); |
| 1424 | r = FLD_MOD(r, data1_lane, 6, 4); |
| 1425 | r = FLD_MOD(r, data1_pol, 7, 7); |
| 1426 | r = FLD_MOD(r, data2_lane, 10, 8); |
| 1427 | r = FLD_MOD(r, data2_pol, 11, 11); |
| 1428 | dsi_write_reg(DSI_COMPLEXIO_CFG1, r); |
| 1429 | |
| 1430 | /* The configuration of the DSI complex I/O (number of data lanes, |
| 1431 | position, differential order) should not be changed while |
| 1432 | DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for |
| 1433 | the hardware to take into account a new configuration of the complex |
| 1434 | I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to |
| 1435 | follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, |
| 1436 | then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set |
| 1437 | DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the |
| 1438 | DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the |
| 1439 | DSI complex I/O configuration is unknown. */ |
| 1440 | |
| 1441 | /* |
| 1442 | REG_FLD_MOD(DSI_CTRL, 1, 0, 0); |
| 1443 | REG_FLD_MOD(DSI_CTRL, 0, 0, 0); |
| 1444 | REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); |
| 1445 | REG_FLD_MOD(DSI_CTRL, 1, 0, 0); |
| 1446 | */ |
| 1447 | } |
| 1448 | |
| 1449 | static inline unsigned ns2ddr(unsigned ns) |
| 1450 | { |
| 1451 | /* convert time in ns to ddr ticks, rounding up */ |
| 1452 | unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4; |
| 1453 | return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000; |
| 1454 | } |
| 1455 | |
| 1456 | static inline unsigned ddr2ns(unsigned ddr) |
| 1457 | { |
| 1458 | unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4; |
| 1459 | return ddr * 1000 * 1000 / (ddr_clk / 1000); |
| 1460 | } |
| 1461 | |
| 1462 | static void dsi_complexio_timings(void) |
| 1463 | { |
| 1464 | u32 r; |
| 1465 | u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; |
| 1466 | u32 tlpx_half, tclk_trail, tclk_zero; |
| 1467 | u32 tclk_prepare; |
| 1468 | |
| 1469 | /* calculate timings */ |
| 1470 | |
| 1471 | /* 1 * DDR_CLK = 2 * UI */ |
| 1472 | |
| 1473 | /* min 40ns + 4*UI max 85ns + 6*UI */ |
| 1474 | ths_prepare = ns2ddr(70) + 2; |
| 1475 | |
| 1476 | /* min 145ns + 10*UI */ |
| 1477 | ths_prepare_ths_zero = ns2ddr(175) + 2; |
| 1478 | |
| 1479 | /* min max(8*UI, 60ns+4*UI) */ |
| 1480 | ths_trail = ns2ddr(60) + 5; |
| 1481 | |
| 1482 | /* min 100ns */ |
| 1483 | ths_exit = ns2ddr(145); |
| 1484 | |
| 1485 | /* tlpx min 50n */ |
| 1486 | tlpx_half = ns2ddr(25); |
| 1487 | |
| 1488 | /* min 60ns */ |
| 1489 | tclk_trail = ns2ddr(60) + 2; |
| 1490 | |
| 1491 | /* min 38ns, max 95ns */ |
| 1492 | tclk_prepare = ns2ddr(65); |
| 1493 | |
| 1494 | /* min tclk-prepare + tclk-zero = 300ns */ |
| 1495 | tclk_zero = ns2ddr(260); |
| 1496 | |
| 1497 | DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n", |
| 1498 | ths_prepare, ddr2ns(ths_prepare), |
| 1499 | ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero)); |
| 1500 | DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n", |
| 1501 | ths_trail, ddr2ns(ths_trail), |
| 1502 | ths_exit, ddr2ns(ths_exit)); |
| 1503 | |
| 1504 | DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), " |
| 1505 | "tclk_zero %u (%uns)\n", |
| 1506 | tlpx_half, ddr2ns(tlpx_half), |
| 1507 | tclk_trail, ddr2ns(tclk_trail), |
| 1508 | tclk_zero, ddr2ns(tclk_zero)); |
| 1509 | DSSDBG("tclk_prepare %u (%uns)\n", |
| 1510 | tclk_prepare, ddr2ns(tclk_prepare)); |
| 1511 | |
| 1512 | /* program timings */ |
| 1513 | |
| 1514 | r = dsi_read_reg(DSI_DSIPHY_CFG0); |
| 1515 | r = FLD_MOD(r, ths_prepare, 31, 24); |
| 1516 | r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); |
| 1517 | r = FLD_MOD(r, ths_trail, 15, 8); |
| 1518 | r = FLD_MOD(r, ths_exit, 7, 0); |
| 1519 | dsi_write_reg(DSI_DSIPHY_CFG0, r); |
| 1520 | |
| 1521 | r = dsi_read_reg(DSI_DSIPHY_CFG1); |
| 1522 | r = FLD_MOD(r, tlpx_half, 22, 16); |
| 1523 | r = FLD_MOD(r, tclk_trail, 15, 8); |
| 1524 | r = FLD_MOD(r, tclk_zero, 7, 0); |
| 1525 | dsi_write_reg(DSI_DSIPHY_CFG1, r); |
| 1526 | |
| 1527 | r = dsi_read_reg(DSI_DSIPHY_CFG2); |
| 1528 | r = FLD_MOD(r, tclk_prepare, 7, 0); |
| 1529 | dsi_write_reg(DSI_DSIPHY_CFG2, r); |
| 1530 | } |
| 1531 | |
| 1532 | |
| 1533 | static int dsi_complexio_init(struct omap_dss_device *dssdev) |
| 1534 | { |
| 1535 | int r = 0; |
| 1536 | |
| 1537 | DSSDBG("dsi_complexio_init\n"); |
| 1538 | |
| 1539 | /* CIO_CLK_ICG, enable L3 clk to CIO */ |
| 1540 | REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14); |
| 1541 | |
| 1542 | /* A dummy read using the SCP interface to any DSIPHY register is |
| 1543 | * required after DSIPHY reset to complete the reset of the DSI complex |
| 1544 | * I/O. */ |
| 1545 | dsi_read_reg(DSI_DSIPHY_CFG5); |
| 1546 | |
| 1547 | if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) { |
| 1548 | DSSERR("ComplexIO PHY not coming out of reset.\n"); |
| 1549 | r = -ENODEV; |
| 1550 | goto err; |
| 1551 | } |
| 1552 | |
| 1553 | dsi_complexio_config(dssdev); |
| 1554 | |
| 1555 | r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON); |
| 1556 | |
| 1557 | if (r) |
| 1558 | goto err; |
| 1559 | |
| 1560 | if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) { |
| 1561 | DSSERR("ComplexIO not coming out of reset.\n"); |
| 1562 | r = -ENODEV; |
| 1563 | goto err; |
| 1564 | } |
| 1565 | |
| 1566 | if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) { |
| 1567 | DSSERR("ComplexIO LDO power down.\n"); |
| 1568 | r = -ENODEV; |
| 1569 | goto err; |
| 1570 | } |
| 1571 | |
| 1572 | dsi_complexio_timings(); |
| 1573 | |
| 1574 | /* |
| 1575 | The configuration of the DSI complex I/O (number of data lanes, |
| 1576 | position, differential order) should not be changed while |
| 1577 | DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the |
| 1578 | hardware to recognize a new configuration of the complex I/O (done |
| 1579 | in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow |
| 1580 | this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next |
| 1581 | reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20] |
| 1582 | LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN |
| 1583 | bit to 1. If the sequence is not followed, the DSi complex I/O |
| 1584 | configuration is undetermined. |
| 1585 | */ |
| 1586 | dsi_if_enable(1); |
| 1587 | dsi_if_enable(0); |
| 1588 | REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ |
| 1589 | dsi_if_enable(1); |
| 1590 | dsi_if_enable(0); |
| 1591 | |
| 1592 | DSSDBG("CIO init done\n"); |
| 1593 | err: |
| 1594 | return r; |
| 1595 | } |
| 1596 | |
| 1597 | static void dsi_complexio_uninit(void) |
| 1598 | { |
| 1599 | dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF); |
| 1600 | } |
| 1601 | |
| 1602 | static int _dsi_wait_reset(void) |
| 1603 | { |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 1604 | int t = 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1605 | |
| 1606 | while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) { |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 1607 | if (++t > 5) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1608 | DSSERR("soft reset failed\n"); |
| 1609 | return -ENODEV; |
| 1610 | } |
| 1611 | udelay(1); |
| 1612 | } |
| 1613 | |
| 1614 | return 0; |
| 1615 | } |
| 1616 | |
| 1617 | static int _dsi_reset(void) |
| 1618 | { |
| 1619 | /* Soft reset */ |
| 1620 | REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1); |
| 1621 | return _dsi_wait_reset(); |
| 1622 | } |
| 1623 | |
| 1624 | static void dsi_reset_tx_fifo(int channel) |
| 1625 | { |
| 1626 | u32 mask; |
| 1627 | u32 l; |
| 1628 | |
| 1629 | /* set fifosize of the channel to 0, then return the old size */ |
| 1630 | l = dsi_read_reg(DSI_TX_FIFO_VC_SIZE); |
| 1631 | |
| 1632 | mask = FLD_MASK((8 * channel) + 7, (8 * channel) + 4); |
| 1633 | dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l & ~mask); |
| 1634 | |
| 1635 | dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l); |
| 1636 | } |
| 1637 | |
| 1638 | static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2, |
| 1639 | enum fifo_size size3, enum fifo_size size4) |
| 1640 | { |
| 1641 | u32 r = 0; |
| 1642 | int add = 0; |
| 1643 | int i; |
| 1644 | |
| 1645 | dsi.vc[0].fifo_size = size1; |
| 1646 | dsi.vc[1].fifo_size = size2; |
| 1647 | dsi.vc[2].fifo_size = size3; |
| 1648 | dsi.vc[3].fifo_size = size4; |
| 1649 | |
| 1650 | for (i = 0; i < 4; i++) { |
| 1651 | u8 v; |
| 1652 | int size = dsi.vc[i].fifo_size; |
| 1653 | |
| 1654 | if (add + size > 4) { |
| 1655 | DSSERR("Illegal FIFO configuration\n"); |
| 1656 | BUG(); |
| 1657 | } |
| 1658 | |
| 1659 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); |
| 1660 | r |= v << (8 * i); |
| 1661 | /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */ |
| 1662 | add += size; |
| 1663 | } |
| 1664 | |
| 1665 | dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r); |
| 1666 | } |
| 1667 | |
| 1668 | static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2, |
| 1669 | enum fifo_size size3, enum fifo_size size4) |
| 1670 | { |
| 1671 | u32 r = 0; |
| 1672 | int add = 0; |
| 1673 | int i; |
| 1674 | |
| 1675 | dsi.vc[0].fifo_size = size1; |
| 1676 | dsi.vc[1].fifo_size = size2; |
| 1677 | dsi.vc[2].fifo_size = size3; |
| 1678 | dsi.vc[3].fifo_size = size4; |
| 1679 | |
| 1680 | for (i = 0; i < 4; i++) { |
| 1681 | u8 v; |
| 1682 | int size = dsi.vc[i].fifo_size; |
| 1683 | |
| 1684 | if (add + size > 4) { |
| 1685 | DSSERR("Illegal FIFO configuration\n"); |
| 1686 | BUG(); |
| 1687 | } |
| 1688 | |
| 1689 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); |
| 1690 | r |= v << (8 * i); |
| 1691 | /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */ |
| 1692 | add += size; |
| 1693 | } |
| 1694 | |
| 1695 | dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r); |
| 1696 | } |
| 1697 | |
| 1698 | static int dsi_force_tx_stop_mode_io(void) |
| 1699 | { |
| 1700 | u32 r; |
| 1701 | |
| 1702 | r = dsi_read_reg(DSI_TIMING1); |
| 1703 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
| 1704 | dsi_write_reg(DSI_TIMING1, r); |
| 1705 | |
| 1706 | if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) { |
| 1707 | DSSERR("TX_STOP bit not going down\n"); |
| 1708 | return -EIO; |
| 1709 | } |
| 1710 | |
| 1711 | return 0; |
| 1712 | } |
| 1713 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1714 | static int dsi_vc_enable(int channel, bool enable) |
| 1715 | { |
Tomi Valkeinen | 446f7bf | 2010-01-11 16:12:31 +0200 | [diff] [blame] | 1716 | DSSDBG("dsi_vc_enable channel %d, enable %d\n", |
| 1717 | channel, enable); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1718 | |
| 1719 | enable = enable ? 1 : 0; |
| 1720 | |
| 1721 | REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0); |
| 1722 | |
| 1723 | if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) { |
| 1724 | DSSERR("Failed to set dsi_vc_enable to %d\n", enable); |
| 1725 | return -EIO; |
| 1726 | } |
| 1727 | |
| 1728 | return 0; |
| 1729 | } |
| 1730 | |
| 1731 | static void dsi_vc_initial_config(int channel) |
| 1732 | { |
| 1733 | u32 r; |
| 1734 | |
| 1735 | DSSDBGF("%d", channel); |
| 1736 | |
| 1737 | r = dsi_read_reg(DSI_VC_CTRL(channel)); |
| 1738 | |
| 1739 | if (FLD_GET(r, 15, 15)) /* VC_BUSY */ |
| 1740 | DSSERR("VC(%d) busy when trying to configure it!\n", |
| 1741 | channel); |
| 1742 | |
| 1743 | r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ |
| 1744 | r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ |
| 1745 | r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ |
| 1746 | r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ |
| 1747 | r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ |
| 1748 | r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ |
| 1749 | r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ |
| 1750 | |
| 1751 | r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ |
| 1752 | r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ |
| 1753 | |
| 1754 | dsi_write_reg(DSI_VC_CTRL(channel), r); |
| 1755 | |
| 1756 | dsi.vc[channel].mode = DSI_VC_MODE_L4; |
| 1757 | } |
| 1758 | |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 1759 | static int dsi_vc_config_l4(int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1760 | { |
| 1761 | if (dsi.vc[channel].mode == DSI_VC_MODE_L4) |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 1762 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1763 | |
| 1764 | DSSDBGF("%d", channel); |
| 1765 | |
| 1766 | dsi_vc_enable(channel, 0); |
| 1767 | |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 1768 | /* VC_BUSY */ |
| 1769 | if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1770 | DSSERR("vc(%d) busy when trying to config for L4\n", channel); |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 1771 | return -EIO; |
| 1772 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1773 | |
| 1774 | REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */ |
| 1775 | |
| 1776 | dsi_vc_enable(channel, 1); |
| 1777 | |
| 1778 | dsi.vc[channel].mode = DSI_VC_MODE_L4; |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 1779 | |
| 1780 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1781 | } |
| 1782 | |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 1783 | static int dsi_vc_config_vp(int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1784 | { |
| 1785 | if (dsi.vc[channel].mode == DSI_VC_MODE_VP) |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 1786 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1787 | |
| 1788 | DSSDBGF("%d", channel); |
| 1789 | |
| 1790 | dsi_vc_enable(channel, 0); |
| 1791 | |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 1792 | /* VC_BUSY */ |
| 1793 | if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1794 | DSSERR("vc(%d) busy when trying to config for VP\n", channel); |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 1795 | return -EIO; |
| 1796 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1797 | |
| 1798 | REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */ |
| 1799 | |
| 1800 | dsi_vc_enable(channel, 1); |
| 1801 | |
| 1802 | dsi.vc[channel].mode = DSI_VC_MODE_VP; |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 1803 | |
| 1804 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1805 | } |
| 1806 | |
| 1807 | |
Tomi Valkeinen | 61140c9 | 2010-01-12 16:00:30 +0200 | [diff] [blame] | 1808 | void omapdss_dsi_vc_enable_hs(int channel, bool enable) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1809 | { |
| 1810 | DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable); |
| 1811 | |
Tomi Valkeinen | 61140c9 | 2010-01-12 16:00:30 +0200 | [diff] [blame] | 1812 | WARN_ON(!dsi_bus_is_locked()); |
| 1813 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1814 | dsi_vc_enable(channel, 0); |
| 1815 | dsi_if_enable(0); |
| 1816 | |
| 1817 | REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9); |
| 1818 | |
| 1819 | dsi_vc_enable(channel, 1); |
| 1820 | dsi_if_enable(1); |
| 1821 | |
| 1822 | dsi_force_tx_stop_mode_io(); |
| 1823 | } |
Tomi Valkeinen | 61140c9 | 2010-01-12 16:00:30 +0200 | [diff] [blame] | 1824 | EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1825 | |
| 1826 | static void dsi_vc_flush_long_data(int channel) |
| 1827 | { |
| 1828 | while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { |
| 1829 | u32 val; |
| 1830 | val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); |
| 1831 | DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", |
| 1832 | (val >> 0) & 0xff, |
| 1833 | (val >> 8) & 0xff, |
| 1834 | (val >> 16) & 0xff, |
| 1835 | (val >> 24) & 0xff); |
| 1836 | } |
| 1837 | } |
| 1838 | |
| 1839 | static void dsi_show_rx_ack_with_err(u16 err) |
| 1840 | { |
| 1841 | DSSERR("\tACK with ERROR (%#x):\n", err); |
| 1842 | if (err & (1 << 0)) |
| 1843 | DSSERR("\t\tSoT Error\n"); |
| 1844 | if (err & (1 << 1)) |
| 1845 | DSSERR("\t\tSoT Sync Error\n"); |
| 1846 | if (err & (1 << 2)) |
| 1847 | DSSERR("\t\tEoT Sync Error\n"); |
| 1848 | if (err & (1 << 3)) |
| 1849 | DSSERR("\t\tEscape Mode Entry Command Error\n"); |
| 1850 | if (err & (1 << 4)) |
| 1851 | DSSERR("\t\tLP Transmit Sync Error\n"); |
| 1852 | if (err & (1 << 5)) |
| 1853 | DSSERR("\t\tHS Receive Timeout Error\n"); |
| 1854 | if (err & (1 << 6)) |
| 1855 | DSSERR("\t\tFalse Control Error\n"); |
| 1856 | if (err & (1 << 7)) |
| 1857 | DSSERR("\t\t(reserved7)\n"); |
| 1858 | if (err & (1 << 8)) |
| 1859 | DSSERR("\t\tECC Error, single-bit (corrected)\n"); |
| 1860 | if (err & (1 << 9)) |
| 1861 | DSSERR("\t\tECC Error, multi-bit (not corrected)\n"); |
| 1862 | if (err & (1 << 10)) |
| 1863 | DSSERR("\t\tChecksum Error\n"); |
| 1864 | if (err & (1 << 11)) |
| 1865 | DSSERR("\t\tData type not recognized\n"); |
| 1866 | if (err & (1 << 12)) |
| 1867 | DSSERR("\t\tInvalid VC ID\n"); |
| 1868 | if (err & (1 << 13)) |
| 1869 | DSSERR("\t\tInvalid Transmission Length\n"); |
| 1870 | if (err & (1 << 14)) |
| 1871 | DSSERR("\t\t(reserved14)\n"); |
| 1872 | if (err & (1 << 15)) |
| 1873 | DSSERR("\t\tDSI Protocol Violation\n"); |
| 1874 | } |
| 1875 | |
| 1876 | static u16 dsi_vc_flush_receive_data(int channel) |
| 1877 | { |
| 1878 | /* RX_FIFO_NOT_EMPTY */ |
| 1879 | while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { |
| 1880 | u32 val; |
| 1881 | u8 dt; |
| 1882 | val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); |
Tomi Valkeinen | 86a7867 | 2010-03-16 16:19:06 +0200 | [diff] [blame] | 1883 | DSSERR("\trawval %#08x\n", val); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1884 | dt = FLD_GET(val, 5, 0); |
| 1885 | if (dt == DSI_DT_RX_ACK_WITH_ERR) { |
| 1886 | u16 err = FLD_GET(val, 23, 8); |
| 1887 | dsi_show_rx_ack_with_err(err); |
| 1888 | } else if (dt == DSI_DT_RX_SHORT_READ_1) { |
Tomi Valkeinen | 86a7867 | 2010-03-16 16:19:06 +0200 | [diff] [blame] | 1889 | DSSERR("\tDCS short response, 1 byte: %#x\n", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1890 | FLD_GET(val, 23, 8)); |
| 1891 | } else if (dt == DSI_DT_RX_SHORT_READ_2) { |
Tomi Valkeinen | 86a7867 | 2010-03-16 16:19:06 +0200 | [diff] [blame] | 1892 | DSSERR("\tDCS short response, 2 byte: %#x\n", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1893 | FLD_GET(val, 23, 8)); |
| 1894 | } else if (dt == DSI_DT_RX_DCS_LONG_READ) { |
Tomi Valkeinen | 86a7867 | 2010-03-16 16:19:06 +0200 | [diff] [blame] | 1895 | DSSERR("\tDCS long response, len %d\n", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1896 | FLD_GET(val, 23, 8)); |
| 1897 | dsi_vc_flush_long_data(channel); |
| 1898 | } else { |
| 1899 | DSSERR("\tunknown datatype 0x%02x\n", dt); |
| 1900 | } |
| 1901 | } |
| 1902 | return 0; |
| 1903 | } |
| 1904 | |
| 1905 | static int dsi_vc_send_bta(int channel) |
| 1906 | { |
Tomi Valkeinen | 446f7bf | 2010-01-11 16:12:31 +0200 | [diff] [blame] | 1907 | if (dsi.debug_write || dsi.debug_read) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1908 | DSSDBG("dsi_vc_send_bta %d\n", channel); |
| 1909 | |
Tomi Valkeinen | 4f76502 | 2010-01-18 16:27:52 +0200 | [diff] [blame] | 1910 | WARN_ON(!dsi_bus_is_locked()); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1911 | |
| 1912 | if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */ |
| 1913 | DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); |
| 1914 | dsi_vc_flush_receive_data(channel); |
| 1915 | } |
| 1916 | |
| 1917 | REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ |
| 1918 | |
| 1919 | return 0; |
| 1920 | } |
| 1921 | |
| 1922 | int dsi_vc_send_bta_sync(int channel) |
| 1923 | { |
| 1924 | int r = 0; |
| 1925 | u32 err; |
| 1926 | |
| 1927 | INIT_COMPLETION(dsi.bta_completion); |
| 1928 | |
| 1929 | dsi_vc_enable_bta_irq(channel); |
| 1930 | |
| 1931 | r = dsi_vc_send_bta(channel); |
| 1932 | if (r) |
| 1933 | goto err; |
| 1934 | |
| 1935 | if (wait_for_completion_timeout(&dsi.bta_completion, |
| 1936 | msecs_to_jiffies(500)) == 0) { |
| 1937 | DSSERR("Failed to receive BTA\n"); |
| 1938 | r = -EIO; |
| 1939 | goto err; |
| 1940 | } |
| 1941 | |
| 1942 | err = dsi_get_errors(); |
| 1943 | if (err) { |
| 1944 | DSSERR("Error while sending BTA: %x\n", err); |
| 1945 | r = -EIO; |
| 1946 | goto err; |
| 1947 | } |
| 1948 | err: |
| 1949 | dsi_vc_disable_bta_irq(channel); |
| 1950 | |
| 1951 | return r; |
| 1952 | } |
| 1953 | EXPORT_SYMBOL(dsi_vc_send_bta_sync); |
| 1954 | |
| 1955 | static inline void dsi_vc_write_long_header(int channel, u8 data_type, |
| 1956 | u16 len, u8 ecc) |
| 1957 | { |
| 1958 | u32 val; |
| 1959 | u8 data_id; |
| 1960 | |
Tomi Valkeinen | 4f76502 | 2010-01-18 16:27:52 +0200 | [diff] [blame] | 1961 | WARN_ON(!dsi_bus_is_locked()); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1962 | |
Tomi Valkeinen | dd8079d | 2009-12-16 16:49:03 +0200 | [diff] [blame] | 1963 | data_id = data_type | channel << 6; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1964 | |
| 1965 | val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | |
| 1966 | FLD_VAL(ecc, 31, 24); |
| 1967 | |
| 1968 | dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val); |
| 1969 | } |
| 1970 | |
| 1971 | static inline void dsi_vc_write_long_payload(int channel, |
| 1972 | u8 b1, u8 b2, u8 b3, u8 b4) |
| 1973 | { |
| 1974 | u32 val; |
| 1975 | |
| 1976 | val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; |
| 1977 | |
| 1978 | /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", |
| 1979 | b1, b2, b3, b4, val); */ |
| 1980 | |
| 1981 | dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val); |
| 1982 | } |
| 1983 | |
| 1984 | static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len, |
| 1985 | u8 ecc) |
| 1986 | { |
| 1987 | /*u32 val; */ |
| 1988 | int i; |
| 1989 | u8 *p; |
| 1990 | int r = 0; |
| 1991 | u8 b1, b2, b3, b4; |
| 1992 | |
| 1993 | if (dsi.debug_write) |
| 1994 | DSSDBG("dsi_vc_send_long, %d bytes\n", len); |
| 1995 | |
| 1996 | /* len + header */ |
| 1997 | if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) { |
| 1998 | DSSERR("unable to send long packet: packet too long.\n"); |
| 1999 | return -EINVAL; |
| 2000 | } |
| 2001 | |
| 2002 | dsi_vc_config_l4(channel); |
| 2003 | |
| 2004 | dsi_vc_write_long_header(channel, data_type, len, ecc); |
| 2005 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2006 | p = data; |
| 2007 | for (i = 0; i < len >> 2; i++) { |
| 2008 | if (dsi.debug_write) |
| 2009 | DSSDBG("\tsending full packet %d\n", i); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2010 | |
| 2011 | b1 = *p++; |
| 2012 | b2 = *p++; |
| 2013 | b3 = *p++; |
| 2014 | b4 = *p++; |
| 2015 | |
| 2016 | dsi_vc_write_long_payload(channel, b1, b2, b3, b4); |
| 2017 | } |
| 2018 | |
| 2019 | i = len % 4; |
| 2020 | if (i) { |
| 2021 | b1 = 0; b2 = 0; b3 = 0; |
| 2022 | |
| 2023 | if (dsi.debug_write) |
| 2024 | DSSDBG("\tsending remainder bytes %d\n", i); |
| 2025 | |
| 2026 | switch (i) { |
| 2027 | case 3: |
| 2028 | b1 = *p++; |
| 2029 | b2 = *p++; |
| 2030 | b3 = *p++; |
| 2031 | break; |
| 2032 | case 2: |
| 2033 | b1 = *p++; |
| 2034 | b2 = *p++; |
| 2035 | break; |
| 2036 | case 1: |
| 2037 | b1 = *p++; |
| 2038 | break; |
| 2039 | } |
| 2040 | |
| 2041 | dsi_vc_write_long_payload(channel, b1, b2, b3, 0); |
| 2042 | } |
| 2043 | |
| 2044 | return r; |
| 2045 | } |
| 2046 | |
| 2047 | static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc) |
| 2048 | { |
| 2049 | u32 r; |
| 2050 | u8 data_id; |
| 2051 | |
Tomi Valkeinen | 4f76502 | 2010-01-18 16:27:52 +0200 | [diff] [blame] | 2052 | WARN_ON(!dsi_bus_is_locked()); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2053 | |
| 2054 | if (dsi.debug_write) |
| 2055 | DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n", |
| 2056 | channel, |
| 2057 | data_type, data & 0xff, (data >> 8) & 0xff); |
| 2058 | |
| 2059 | dsi_vc_config_l4(channel); |
| 2060 | |
| 2061 | if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) { |
| 2062 | DSSERR("ERROR FIFO FULL, aborting transfer\n"); |
| 2063 | return -EINVAL; |
| 2064 | } |
| 2065 | |
Tomi Valkeinen | dd8079d | 2009-12-16 16:49:03 +0200 | [diff] [blame] | 2066 | data_id = data_type | channel << 6; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2067 | |
| 2068 | r = (data_id << 0) | (data << 8) | (ecc << 24); |
| 2069 | |
| 2070 | dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r); |
| 2071 | |
| 2072 | return 0; |
| 2073 | } |
| 2074 | |
| 2075 | int dsi_vc_send_null(int channel) |
| 2076 | { |
| 2077 | u8 nullpkg[] = {0, 0, 0, 0}; |
Tomi Valkeinen | 397bb3c | 2009-12-03 13:37:31 +0200 | [diff] [blame] | 2078 | return dsi_vc_send_long(channel, DSI_DT_NULL_PACKET, nullpkg, 4, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2079 | } |
| 2080 | EXPORT_SYMBOL(dsi_vc_send_null); |
| 2081 | |
| 2082 | int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len) |
| 2083 | { |
| 2084 | int r; |
| 2085 | |
| 2086 | BUG_ON(len == 0); |
| 2087 | |
| 2088 | if (len == 1) { |
| 2089 | r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0, |
| 2090 | data[0], 0); |
| 2091 | } else if (len == 2) { |
| 2092 | r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1, |
| 2093 | data[0] | (data[1] << 8), 0); |
| 2094 | } else { |
| 2095 | /* 0x39 = DCS Long Write */ |
| 2096 | r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE, |
| 2097 | data, len, 0); |
| 2098 | } |
| 2099 | |
| 2100 | return r; |
| 2101 | } |
| 2102 | EXPORT_SYMBOL(dsi_vc_dcs_write_nosync); |
| 2103 | |
| 2104 | int dsi_vc_dcs_write(int channel, u8 *data, int len) |
| 2105 | { |
| 2106 | int r; |
| 2107 | |
| 2108 | r = dsi_vc_dcs_write_nosync(channel, data, len); |
| 2109 | if (r) |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2110 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2111 | |
| 2112 | r = dsi_vc_send_bta_sync(channel); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2113 | if (r) |
| 2114 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2115 | |
Tomi Valkeinen | b63ac1e | 2010-04-09 13:20:57 +0300 | [diff] [blame] | 2116 | if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */ |
| 2117 | DSSERR("rx fifo not empty after write, dumping data:\n"); |
| 2118 | dsi_vc_flush_receive_data(channel); |
| 2119 | r = -EIO; |
| 2120 | goto err; |
| 2121 | } |
| 2122 | |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2123 | return 0; |
| 2124 | err: |
| 2125 | DSSERR("dsi_vc_dcs_write(ch %d, cmd 0x%02x, len %d) failed\n", |
| 2126 | channel, data[0], len); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2127 | return r; |
| 2128 | } |
| 2129 | EXPORT_SYMBOL(dsi_vc_dcs_write); |
| 2130 | |
Tomi Valkeinen | 828c48f | 2009-12-16 14:53:15 +0200 | [diff] [blame] | 2131 | int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd) |
| 2132 | { |
| 2133 | return dsi_vc_dcs_write(channel, &dcs_cmd, 1); |
| 2134 | } |
| 2135 | EXPORT_SYMBOL(dsi_vc_dcs_write_0); |
| 2136 | |
| 2137 | int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param) |
| 2138 | { |
| 2139 | u8 buf[2]; |
| 2140 | buf[0] = dcs_cmd; |
| 2141 | buf[1] = param; |
| 2142 | return dsi_vc_dcs_write(channel, buf, 2); |
| 2143 | } |
| 2144 | EXPORT_SYMBOL(dsi_vc_dcs_write_1); |
| 2145 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2146 | int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen) |
| 2147 | { |
| 2148 | u32 val; |
| 2149 | u8 dt; |
| 2150 | int r; |
| 2151 | |
| 2152 | if (dsi.debug_read) |
Tomi Valkeinen | ff90a34 | 2009-12-03 13:38:04 +0200 | [diff] [blame] | 2153 | DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel, dcs_cmd); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2154 | |
| 2155 | r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0); |
| 2156 | if (r) |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2157 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2158 | |
| 2159 | r = dsi_vc_send_bta_sync(channel); |
| 2160 | if (r) |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2161 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2162 | |
| 2163 | /* RX_FIFO_NOT_EMPTY */ |
| 2164 | if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) { |
| 2165 | DSSERR("RX fifo empty when trying to read.\n"); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2166 | r = -EIO; |
| 2167 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2168 | } |
| 2169 | |
| 2170 | val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); |
| 2171 | if (dsi.debug_read) |
| 2172 | DSSDBG("\theader: %08x\n", val); |
| 2173 | dt = FLD_GET(val, 5, 0); |
| 2174 | if (dt == DSI_DT_RX_ACK_WITH_ERR) { |
| 2175 | u16 err = FLD_GET(val, 23, 8); |
| 2176 | dsi_show_rx_ack_with_err(err); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2177 | r = -EIO; |
| 2178 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2179 | |
| 2180 | } else if (dt == DSI_DT_RX_SHORT_READ_1) { |
| 2181 | u8 data = FLD_GET(val, 15, 8); |
| 2182 | if (dsi.debug_read) |
| 2183 | DSSDBG("\tDCS short response, 1 byte: %02x\n", data); |
| 2184 | |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2185 | if (buflen < 1) { |
| 2186 | r = -EIO; |
| 2187 | goto err; |
| 2188 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2189 | |
| 2190 | buf[0] = data; |
| 2191 | |
| 2192 | return 1; |
| 2193 | } else if (dt == DSI_DT_RX_SHORT_READ_2) { |
| 2194 | u16 data = FLD_GET(val, 23, 8); |
| 2195 | if (dsi.debug_read) |
| 2196 | DSSDBG("\tDCS short response, 2 byte: %04x\n", data); |
| 2197 | |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2198 | if (buflen < 2) { |
| 2199 | r = -EIO; |
| 2200 | goto err; |
| 2201 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2202 | |
| 2203 | buf[0] = data & 0xff; |
| 2204 | buf[1] = (data >> 8) & 0xff; |
| 2205 | |
| 2206 | return 2; |
| 2207 | } else if (dt == DSI_DT_RX_DCS_LONG_READ) { |
| 2208 | int w; |
| 2209 | int len = FLD_GET(val, 23, 8); |
| 2210 | if (dsi.debug_read) |
| 2211 | DSSDBG("\tDCS long response, len %d\n", len); |
| 2212 | |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2213 | if (len > buflen) { |
| 2214 | r = -EIO; |
| 2215 | goto err; |
| 2216 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2217 | |
| 2218 | /* two byte checksum ends the packet, not included in len */ |
| 2219 | for (w = 0; w < len + 2;) { |
| 2220 | int b; |
| 2221 | val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); |
| 2222 | if (dsi.debug_read) |
| 2223 | DSSDBG("\t\t%02x %02x %02x %02x\n", |
| 2224 | (val >> 0) & 0xff, |
| 2225 | (val >> 8) & 0xff, |
| 2226 | (val >> 16) & 0xff, |
| 2227 | (val >> 24) & 0xff); |
| 2228 | |
| 2229 | for (b = 0; b < 4; ++b) { |
| 2230 | if (w < len) |
| 2231 | buf[w] = (val >> (b * 8)) & 0xff; |
| 2232 | /* we discard the 2 byte checksum */ |
| 2233 | ++w; |
| 2234 | } |
| 2235 | } |
| 2236 | |
| 2237 | return len; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2238 | } else { |
| 2239 | DSSERR("\tunknown datatype 0x%02x\n", dt); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2240 | r = -EIO; |
| 2241 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2242 | } |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2243 | |
| 2244 | BUG(); |
| 2245 | err: |
| 2246 | DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", |
| 2247 | channel, dcs_cmd); |
| 2248 | return r; |
| 2249 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2250 | } |
| 2251 | EXPORT_SYMBOL(dsi_vc_dcs_read); |
| 2252 | |
Tomi Valkeinen | 828c48f | 2009-12-16 14:53:15 +0200 | [diff] [blame] | 2253 | int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data) |
| 2254 | { |
| 2255 | int r; |
| 2256 | |
| 2257 | r = dsi_vc_dcs_read(channel, dcs_cmd, data, 1); |
| 2258 | |
| 2259 | if (r < 0) |
| 2260 | return r; |
| 2261 | |
| 2262 | if (r != 1) |
| 2263 | return -EIO; |
| 2264 | |
| 2265 | return 0; |
| 2266 | } |
| 2267 | EXPORT_SYMBOL(dsi_vc_dcs_read_1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2268 | |
Tomi Valkeinen | 0c244f7 | 2010-06-09 15:19:29 +0300 | [diff] [blame] | 2269 | int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u8 *data1, u8 *data2) |
Tomi Valkeinen | 53055aa | 2010-02-25 11:38:13 +0200 | [diff] [blame] | 2270 | { |
Tomi Valkeinen | 0c244f7 | 2010-06-09 15:19:29 +0300 | [diff] [blame] | 2271 | u8 buf[2]; |
Tomi Valkeinen | 53055aa | 2010-02-25 11:38:13 +0200 | [diff] [blame] | 2272 | int r; |
| 2273 | |
Tomi Valkeinen | 0c244f7 | 2010-06-09 15:19:29 +0300 | [diff] [blame] | 2274 | r = dsi_vc_dcs_read(channel, dcs_cmd, buf, 2); |
Tomi Valkeinen | 53055aa | 2010-02-25 11:38:13 +0200 | [diff] [blame] | 2275 | |
| 2276 | if (r < 0) |
| 2277 | return r; |
| 2278 | |
| 2279 | if (r != 2) |
| 2280 | return -EIO; |
| 2281 | |
Tomi Valkeinen | 0c244f7 | 2010-06-09 15:19:29 +0300 | [diff] [blame] | 2282 | *data1 = buf[0]; |
| 2283 | *data2 = buf[1]; |
| 2284 | |
Tomi Valkeinen | 53055aa | 2010-02-25 11:38:13 +0200 | [diff] [blame] | 2285 | return 0; |
| 2286 | } |
| 2287 | EXPORT_SYMBOL(dsi_vc_dcs_read_2); |
| 2288 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2289 | int dsi_vc_set_max_rx_packet_size(int channel, u16 len) |
| 2290 | { |
Tomi Valkeinen | fa15c79 | 2010-05-14 17:42:07 +0300 | [diff] [blame] | 2291 | return dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2292 | len, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2293 | } |
| 2294 | EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size); |
| 2295 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2296 | static void dsi_set_lp_rx_timeout(unsigned ticks, bool x4, bool x16) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2297 | { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2298 | unsigned long fck; |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2299 | unsigned long total_ticks; |
| 2300 | u32 r; |
| 2301 | |
| 2302 | BUG_ON(ticks > 0x1fff); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2303 | |
| 2304 | /* ticks in DSI_FCK */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2305 | fck = dsi_fclk_rate(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2306 | |
| 2307 | r = dsi_read_reg(DSI_TIMING2); |
| 2308 | r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2309 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ |
| 2310 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2311 | r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ |
| 2312 | dsi_write_reg(DSI_TIMING2, r); |
| 2313 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2314 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
| 2315 | |
| 2316 | DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n", |
| 2317 | total_ticks, |
| 2318 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", |
| 2319 | (total_ticks * 1000) / (fck / 1000 / 1000)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2320 | } |
| 2321 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2322 | static void dsi_set_ta_timeout(unsigned ticks, bool x8, bool x16) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2323 | { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2324 | unsigned long fck; |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2325 | unsigned long total_ticks; |
| 2326 | u32 r; |
| 2327 | |
| 2328 | BUG_ON(ticks > 0x1fff); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2329 | |
| 2330 | /* ticks in DSI_FCK */ |
| 2331 | fck = dsi_fclk_rate(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2332 | |
| 2333 | r = dsi_read_reg(DSI_TIMING1); |
| 2334 | r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2335 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ |
| 2336 | r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2337 | r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ |
| 2338 | dsi_write_reg(DSI_TIMING1, r); |
| 2339 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2340 | total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1); |
| 2341 | |
| 2342 | DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n", |
| 2343 | total_ticks, |
| 2344 | ticks, x8 ? " x8" : "", x16 ? " x16" : "", |
| 2345 | (total_ticks * 1000) / (fck / 1000 / 1000)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2346 | } |
| 2347 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2348 | static void dsi_set_stop_state_counter(unsigned ticks, bool x4, bool x16) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2349 | { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2350 | unsigned long fck; |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2351 | unsigned long total_ticks; |
| 2352 | u32 r; |
| 2353 | |
| 2354 | BUG_ON(ticks > 0x1fff); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2355 | |
| 2356 | /* ticks in DSI_FCK */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2357 | fck = dsi_fclk_rate(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2358 | |
| 2359 | r = dsi_read_reg(DSI_TIMING1); |
| 2360 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2361 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ |
| 2362 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2363 | r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ |
| 2364 | dsi_write_reg(DSI_TIMING1, r); |
| 2365 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2366 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
| 2367 | |
| 2368 | DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n", |
| 2369 | total_ticks, |
| 2370 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", |
| 2371 | (total_ticks * 1000) / (fck / 1000 / 1000)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2372 | } |
| 2373 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2374 | static void dsi_set_hs_tx_timeout(unsigned ticks, bool x4, bool x16) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2375 | { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2376 | unsigned long fck; |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2377 | unsigned long total_ticks; |
| 2378 | u32 r; |
| 2379 | |
| 2380 | BUG_ON(ticks > 0x1fff); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2381 | |
| 2382 | /* ticks in TxByteClkHS */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2383 | fck = dsi_get_txbyteclkhs(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2384 | |
| 2385 | r = dsi_read_reg(DSI_TIMING2); |
| 2386 | r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2387 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ |
| 2388 | r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2389 | r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ |
| 2390 | dsi_write_reg(DSI_TIMING2, r); |
| 2391 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2392 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
| 2393 | |
| 2394 | DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n", |
| 2395 | total_ticks, |
| 2396 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", |
| 2397 | (total_ticks * 1000) / (fck / 1000 / 1000)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2398 | } |
| 2399 | static int dsi_proto_config(struct omap_dss_device *dssdev) |
| 2400 | { |
| 2401 | u32 r; |
| 2402 | int buswidth = 0; |
| 2403 | |
Tomi Valkeinen | dd8079d | 2009-12-16 16:49:03 +0200 | [diff] [blame] | 2404 | dsi_config_tx_fifo(DSI_FIFO_SIZE_32, |
| 2405 | DSI_FIFO_SIZE_32, |
| 2406 | DSI_FIFO_SIZE_32, |
| 2407 | DSI_FIFO_SIZE_32); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2408 | |
Tomi Valkeinen | dd8079d | 2009-12-16 16:49:03 +0200 | [diff] [blame] | 2409 | dsi_config_rx_fifo(DSI_FIFO_SIZE_32, |
| 2410 | DSI_FIFO_SIZE_32, |
| 2411 | DSI_FIFO_SIZE_32, |
| 2412 | DSI_FIFO_SIZE_32); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2413 | |
| 2414 | /* XXX what values for the timeouts? */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2415 | dsi_set_stop_state_counter(0x1000, false, false); |
| 2416 | dsi_set_ta_timeout(0x1fff, true, true); |
| 2417 | dsi_set_lp_rx_timeout(0x1fff, true, true); |
| 2418 | dsi_set_hs_tx_timeout(0x1fff, true, true); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2419 | |
| 2420 | switch (dssdev->ctrl.pixel_size) { |
| 2421 | case 16: |
| 2422 | buswidth = 0; |
| 2423 | break; |
| 2424 | case 18: |
| 2425 | buswidth = 1; |
| 2426 | break; |
| 2427 | case 24: |
| 2428 | buswidth = 2; |
| 2429 | break; |
| 2430 | default: |
| 2431 | BUG(); |
| 2432 | } |
| 2433 | |
| 2434 | r = dsi_read_reg(DSI_CTRL); |
| 2435 | r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ |
| 2436 | r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ |
| 2437 | r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ |
| 2438 | r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/ |
| 2439 | r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ |
| 2440 | r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ |
| 2441 | r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */ |
| 2442 | r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ |
| 2443 | r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ |
| 2444 | r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ |
| 2445 | r = FLD_MOD(r, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */ |
| 2446 | |
| 2447 | dsi_write_reg(DSI_CTRL, r); |
| 2448 | |
| 2449 | dsi_vc_initial_config(0); |
Tomi Valkeinen | dd8079d | 2009-12-16 16:49:03 +0200 | [diff] [blame] | 2450 | dsi_vc_initial_config(1); |
| 2451 | dsi_vc_initial_config(2); |
| 2452 | dsi_vc_initial_config(3); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2453 | |
| 2454 | return 0; |
| 2455 | } |
| 2456 | |
| 2457 | static void dsi_proto_timings(struct omap_dss_device *dssdev) |
| 2458 | { |
| 2459 | unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail; |
| 2460 | unsigned tclk_pre, tclk_post; |
| 2461 | unsigned ths_prepare, ths_prepare_ths_zero, ths_zero; |
| 2462 | unsigned ths_trail, ths_exit; |
| 2463 | unsigned ddr_clk_pre, ddr_clk_post; |
| 2464 | unsigned enter_hs_mode_lat, exit_hs_mode_lat; |
| 2465 | unsigned ths_eot; |
| 2466 | u32 r; |
| 2467 | |
| 2468 | r = dsi_read_reg(DSI_DSIPHY_CFG0); |
| 2469 | ths_prepare = FLD_GET(r, 31, 24); |
| 2470 | ths_prepare_ths_zero = FLD_GET(r, 23, 16); |
| 2471 | ths_zero = ths_prepare_ths_zero - ths_prepare; |
| 2472 | ths_trail = FLD_GET(r, 15, 8); |
| 2473 | ths_exit = FLD_GET(r, 7, 0); |
| 2474 | |
| 2475 | r = dsi_read_reg(DSI_DSIPHY_CFG1); |
| 2476 | tlpx = FLD_GET(r, 22, 16) * 2; |
| 2477 | tclk_trail = FLD_GET(r, 15, 8); |
| 2478 | tclk_zero = FLD_GET(r, 7, 0); |
| 2479 | |
| 2480 | r = dsi_read_reg(DSI_DSIPHY_CFG2); |
| 2481 | tclk_prepare = FLD_GET(r, 7, 0); |
| 2482 | |
| 2483 | /* min 8*UI */ |
| 2484 | tclk_pre = 20; |
| 2485 | /* min 60ns + 52*UI */ |
| 2486 | tclk_post = ns2ddr(60) + 26; |
| 2487 | |
| 2488 | /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */ |
| 2489 | if (dssdev->phy.dsi.data1_lane != 0 && |
| 2490 | dssdev->phy.dsi.data2_lane != 0) |
| 2491 | ths_eot = 2; |
| 2492 | else |
| 2493 | ths_eot = 4; |
| 2494 | |
| 2495 | ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare, |
| 2496 | 4); |
| 2497 | ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot; |
| 2498 | |
| 2499 | BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255); |
| 2500 | BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255); |
| 2501 | |
| 2502 | r = dsi_read_reg(DSI_CLK_TIMING); |
| 2503 | r = FLD_MOD(r, ddr_clk_pre, 15, 8); |
| 2504 | r = FLD_MOD(r, ddr_clk_post, 7, 0); |
| 2505 | dsi_write_reg(DSI_CLK_TIMING, r); |
| 2506 | |
| 2507 | DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n", |
| 2508 | ddr_clk_pre, |
| 2509 | ddr_clk_post); |
| 2510 | |
| 2511 | enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) + |
| 2512 | DIV_ROUND_UP(ths_prepare, 4) + |
| 2513 | DIV_ROUND_UP(ths_zero + 3, 4); |
| 2514 | |
| 2515 | exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot; |
| 2516 | |
| 2517 | r = FLD_VAL(enter_hs_mode_lat, 31, 16) | |
| 2518 | FLD_VAL(exit_hs_mode_lat, 15, 0); |
| 2519 | dsi_write_reg(DSI_VM_TIMING7, r); |
| 2520 | |
| 2521 | DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n", |
| 2522 | enter_hs_mode_lat, exit_hs_mode_lat); |
| 2523 | } |
| 2524 | |
| 2525 | |
| 2526 | #define DSI_DECL_VARS \ |
| 2527 | int __dsi_cb = 0; u32 __dsi_cv = 0; |
| 2528 | |
| 2529 | #define DSI_FLUSH(ch) \ |
| 2530 | if (__dsi_cb > 0) { \ |
| 2531 | /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \ |
| 2532 | dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \ |
| 2533 | __dsi_cb = __dsi_cv = 0; \ |
| 2534 | } |
| 2535 | |
| 2536 | #define DSI_PUSH(ch, data) \ |
| 2537 | do { \ |
| 2538 | __dsi_cv |= (data) << (__dsi_cb * 8); \ |
| 2539 | /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \ |
| 2540 | if (++__dsi_cb > 3) \ |
| 2541 | DSI_FLUSH(ch); \ |
| 2542 | } while (0) |
| 2543 | |
| 2544 | static int dsi_update_screen_l4(struct omap_dss_device *dssdev, |
| 2545 | int x, int y, int w, int h) |
| 2546 | { |
| 2547 | /* Note: supports only 24bit colors in 32bit container */ |
| 2548 | int first = 1; |
| 2549 | int fifo_stalls = 0; |
| 2550 | int max_dsi_packet_size; |
| 2551 | int max_data_per_packet; |
| 2552 | int max_pixels_per_packet; |
| 2553 | int pixels_left; |
| 2554 | int bytespp = dssdev->ctrl.pixel_size / 8; |
| 2555 | int scr_width; |
| 2556 | u32 __iomem *data; |
| 2557 | int start_offset; |
| 2558 | int horiz_inc; |
| 2559 | int current_x; |
| 2560 | struct omap_overlay *ovl; |
| 2561 | |
| 2562 | debug_irq = 0; |
| 2563 | |
| 2564 | DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n", |
| 2565 | x, y, w, h); |
| 2566 | |
| 2567 | ovl = dssdev->manager->overlays[0]; |
| 2568 | |
| 2569 | if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U) |
| 2570 | return -EINVAL; |
| 2571 | |
| 2572 | if (dssdev->ctrl.pixel_size != 24) |
| 2573 | return -EINVAL; |
| 2574 | |
| 2575 | scr_width = ovl->info.screen_width; |
| 2576 | data = ovl->info.vaddr; |
| 2577 | |
| 2578 | start_offset = scr_width * y + x; |
| 2579 | horiz_inc = scr_width - w; |
| 2580 | current_x = x; |
| 2581 | |
| 2582 | /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes |
| 2583 | * in fifo */ |
| 2584 | |
| 2585 | /* When using CPU, max long packet size is TX buffer size */ |
| 2586 | max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4; |
| 2587 | |
| 2588 | /* we seem to get better perf if we divide the tx fifo to half, |
| 2589 | and while the other half is being sent, we fill the other half |
| 2590 | max_dsi_packet_size /= 2; */ |
| 2591 | |
| 2592 | max_data_per_packet = max_dsi_packet_size - 4 - 1; |
| 2593 | |
| 2594 | max_pixels_per_packet = max_data_per_packet / bytespp; |
| 2595 | |
| 2596 | DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet); |
| 2597 | |
| 2598 | pixels_left = w * h; |
| 2599 | |
| 2600 | DSSDBG("total pixels %d\n", pixels_left); |
| 2601 | |
| 2602 | data += start_offset; |
| 2603 | |
| 2604 | while (pixels_left > 0) { |
| 2605 | /* 0x2c = write_memory_start */ |
| 2606 | /* 0x3c = write_memory_continue */ |
| 2607 | u8 dcs_cmd = first ? 0x2c : 0x3c; |
| 2608 | int pixels; |
| 2609 | DSI_DECL_VARS; |
| 2610 | first = 0; |
| 2611 | |
| 2612 | #if 1 |
| 2613 | /* using fifo not empty */ |
| 2614 | /* TX_FIFO_NOT_EMPTY */ |
| 2615 | while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2616 | fifo_stalls++; |
| 2617 | if (fifo_stalls > 0xfffff) { |
| 2618 | DSSERR("fifo stalls overflow, pixels left %d\n", |
| 2619 | pixels_left); |
| 2620 | dsi_if_enable(0); |
| 2621 | return -EIO; |
| 2622 | } |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 2623 | udelay(1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2624 | } |
| 2625 | #elif 1 |
| 2626 | /* using fifo emptiness */ |
| 2627 | while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 < |
| 2628 | max_dsi_packet_size) { |
| 2629 | fifo_stalls++; |
| 2630 | if (fifo_stalls > 0xfffff) { |
| 2631 | DSSERR("fifo stalls overflow, pixels left %d\n", |
| 2632 | pixels_left); |
| 2633 | dsi_if_enable(0); |
| 2634 | return -EIO; |
| 2635 | } |
| 2636 | } |
| 2637 | #else |
| 2638 | while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) { |
| 2639 | fifo_stalls++; |
| 2640 | if (fifo_stalls > 0xfffff) { |
| 2641 | DSSERR("fifo stalls overflow, pixels left %d\n", |
| 2642 | pixels_left); |
| 2643 | dsi_if_enable(0); |
| 2644 | return -EIO; |
| 2645 | } |
| 2646 | } |
| 2647 | #endif |
| 2648 | pixels = min(max_pixels_per_packet, pixels_left); |
| 2649 | |
| 2650 | pixels_left -= pixels; |
| 2651 | |
| 2652 | dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE, |
| 2653 | 1 + pixels * bytespp, 0); |
| 2654 | |
| 2655 | DSI_PUSH(0, dcs_cmd); |
| 2656 | |
| 2657 | while (pixels-- > 0) { |
| 2658 | u32 pix = __raw_readl(data++); |
| 2659 | |
| 2660 | DSI_PUSH(0, (pix >> 16) & 0xff); |
| 2661 | DSI_PUSH(0, (pix >> 8) & 0xff); |
| 2662 | DSI_PUSH(0, (pix >> 0) & 0xff); |
| 2663 | |
| 2664 | current_x++; |
| 2665 | if (current_x == x+w) { |
| 2666 | current_x = x; |
| 2667 | data += horiz_inc; |
| 2668 | } |
| 2669 | } |
| 2670 | |
| 2671 | DSI_FLUSH(0); |
| 2672 | } |
| 2673 | |
| 2674 | return 0; |
| 2675 | } |
| 2676 | |
| 2677 | static void dsi_update_screen_dispc(struct omap_dss_device *dssdev, |
| 2678 | u16 x, u16 y, u16 w, u16 h) |
| 2679 | { |
| 2680 | unsigned bytespp; |
| 2681 | unsigned bytespl; |
| 2682 | unsigned bytespf; |
| 2683 | unsigned total_len; |
| 2684 | unsigned packet_payload; |
| 2685 | unsigned packet_len; |
| 2686 | u32 l; |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 2687 | int r; |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2688 | const unsigned channel = dsi.update_channel; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2689 | /* line buffer is 1024 x 24bits */ |
| 2690 | /* XXX: for some reason using full buffer size causes considerable TX |
| 2691 | * slowdown with update sizes that fill the whole buffer */ |
| 2692 | const unsigned line_buf_size = 1023 * 3; |
| 2693 | |
Tomi Valkeinen | 446f7bf | 2010-01-11 16:12:31 +0200 | [diff] [blame] | 2694 | DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n", |
| 2695 | x, y, w, h); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2696 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2697 | dsi_vc_config_vp(channel); |
| 2698 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2699 | bytespp = dssdev->ctrl.pixel_size / 8; |
| 2700 | bytespl = w * bytespp; |
| 2701 | bytespf = bytespl * h; |
| 2702 | |
| 2703 | /* NOTE: packet_payload has to be equal to N * bytespl, where N is |
| 2704 | * number of lines in a packet. See errata about VP_CLK_RATIO */ |
| 2705 | |
| 2706 | if (bytespf < line_buf_size) |
| 2707 | packet_payload = bytespf; |
| 2708 | else |
| 2709 | packet_payload = (line_buf_size) / bytespl * bytespl; |
| 2710 | |
| 2711 | packet_len = packet_payload + 1; /* 1 byte for DCS cmd */ |
| 2712 | total_len = (bytespf / packet_payload) * packet_len; |
| 2713 | |
| 2714 | if (bytespf % packet_payload) |
| 2715 | total_len += (bytespf % packet_payload) + 1; |
| 2716 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2717 | l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ |
| 2718 | dsi_write_reg(DSI_VC_TE(channel), l); |
| 2719 | |
| 2720 | dsi_vc_write_long_header(channel, DSI_DT_DCS_LONG_WRITE, packet_len, 0); |
| 2721 | |
Tomi Valkeinen | 942a91a | 2010-02-10 17:27:39 +0200 | [diff] [blame] | 2722 | if (dsi.te_enabled) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2723 | l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ |
| 2724 | else |
| 2725 | l = FLD_MOD(l, 1, 31, 31); /* TE_START */ |
| 2726 | dsi_write_reg(DSI_VC_TE(channel), l); |
| 2727 | |
| 2728 | /* We put SIDLEMODE to no-idle for the duration of the transfer, |
| 2729 | * because DSS interrupts are not capable of waking up the CPU and the |
| 2730 | * framedone interrupt could be delayed for quite a long time. I think |
| 2731 | * the same goes for any DSS interrupts, but for some reason I have not |
| 2732 | * seen the problem anywhere else than here. |
| 2733 | */ |
| 2734 | dispc_disable_sidle(); |
| 2735 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2736 | dsi_perf_mark_start(); |
| 2737 | |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 2738 | r = queue_delayed_work(dsi.workqueue, &dsi.framedone_timeout_work, |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2739 | msecs_to_jiffies(250)); |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 2740 | BUG_ON(r == 0); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2741 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2742 | dss_start_update(dssdev); |
| 2743 | |
Tomi Valkeinen | 942a91a | 2010-02-10 17:27:39 +0200 | [diff] [blame] | 2744 | if (dsi.te_enabled) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2745 | /* disable LP_RX_TO, so that we can receive TE. Time to wait |
| 2746 | * for TE is longer than the timer allows */ |
| 2747 | REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ |
| 2748 | |
| 2749 | dsi_vc_send_bta(channel); |
| 2750 | |
| 2751 | #ifdef DSI_CATCH_MISSING_TE |
| 2752 | mod_timer(&dsi.te_timer, jiffies + msecs_to_jiffies(250)); |
| 2753 | #endif |
| 2754 | } |
| 2755 | } |
| 2756 | |
| 2757 | #ifdef DSI_CATCH_MISSING_TE |
| 2758 | static void dsi_te_timeout(unsigned long arg) |
| 2759 | { |
| 2760 | DSSERR("TE not received for 250ms!\n"); |
| 2761 | } |
| 2762 | #endif |
| 2763 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2764 | static void dsi_handle_framedone(int error) |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2765 | { |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2766 | const int channel = dsi.update_channel; |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2767 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2768 | cancel_delayed_work(&dsi.framedone_timeout_work); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2769 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2770 | dsi_vc_disable_bta_irq(channel); |
| 2771 | |
| 2772 | /* SIDLEMODE back to smart-idle */ |
| 2773 | dispc_enable_sidle(); |
| 2774 | |
| 2775 | dsi.bta_callback = NULL; |
| 2776 | |
| 2777 | if (dsi.te_enabled) { |
| 2778 | /* enable LP_RX_TO again after the TE */ |
| 2779 | REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ |
| 2780 | } |
| 2781 | |
| 2782 | /* RX_FIFO_NOT_EMPTY */ |
| 2783 | if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { |
| 2784 | DSSERR("Received error during frame transfer:\n"); |
| 2785 | dsi_vc_flush_receive_data(channel); |
| 2786 | if (!error) |
| 2787 | error = -EIO; |
| 2788 | } |
| 2789 | |
| 2790 | dsi.framedone_callback(error, dsi.framedone_data); |
| 2791 | |
| 2792 | if (!error) |
| 2793 | dsi_perf_show("DISPC"); |
| 2794 | } |
| 2795 | |
| 2796 | static void dsi_framedone_timeout_work_callback(struct work_struct *work) |
| 2797 | { |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 2798 | /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after |
| 2799 | * 250ms which would conflict with this timeout work. What should be |
| 2800 | * done is first cancel the transfer on the HW, and then cancel the |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2801 | * possibly scheduled framedone work. However, cancelling the transfer |
| 2802 | * on the HW is buggy, and would probably require resetting the whole |
| 2803 | * DSI */ |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 2804 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2805 | DSSERR("Framedone not received for 250ms!\n"); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2806 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2807 | dsi_handle_framedone(-ETIMEDOUT); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2808 | } |
| 2809 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2810 | static void dsi_framedone_bta_callback(void) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2811 | { |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2812 | dsi_handle_framedone(0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2813 | |
| 2814 | #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC |
| 2815 | dispc_fake_vsync_irq(); |
| 2816 | #endif |
| 2817 | } |
| 2818 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2819 | static void dsi_framedone_irq_callback(void *data, u32 mask) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2820 | { |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2821 | const int channel = dsi.update_channel; |
| 2822 | int r; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2823 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2824 | /* Note: We get FRAMEDONE when DISPC has finished sending pixels and |
| 2825 | * turns itself off. However, DSI still has the pixels in its buffers, |
| 2826 | * and is sending the data. |
| 2827 | */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2828 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2829 | if (dsi.te_enabled) { |
| 2830 | /* enable LP_RX_TO again after the TE */ |
| 2831 | REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ |
| 2832 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2833 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2834 | /* Send BTA after the frame. We need this for the TE to work, as TE |
| 2835 | * trigger is only sent for BTAs without preceding packet. Thus we need |
| 2836 | * to BTA after the pixel packets so that next BTA will cause TE |
| 2837 | * trigger. |
| 2838 | * |
| 2839 | * This is not needed when TE is not in use, but we do it anyway to |
| 2840 | * make sure that the transfer has been completed. It would be more |
| 2841 | * optimal, but more complex, to wait only just before starting next |
| 2842 | * transfer. |
| 2843 | * |
| 2844 | * Also, as there's no interrupt telling when the transfer has been |
| 2845 | * done and the channel could be reconfigured, the only way is to |
| 2846 | * busyloop until TE_SIZE is zero. With BTA we can do this |
| 2847 | * asynchronously. |
| 2848 | * */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2849 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2850 | dsi.bta_callback = dsi_framedone_bta_callback; |
| 2851 | |
| 2852 | barrier(); |
| 2853 | |
| 2854 | dsi_vc_enable_bta_irq(channel); |
| 2855 | |
| 2856 | r = dsi_vc_send_bta(channel); |
| 2857 | if (r) { |
| 2858 | DSSERR("BTA after framedone failed\n"); |
| 2859 | dsi_handle_framedone(-EIO); |
| 2860 | } |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2861 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2862 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2863 | int omap_dsi_prepare_update(struct omap_dss_device *dssdev, |
Tomi Valkeinen | 26a8c25 | 2010-06-09 15:31:34 +0300 | [diff] [blame] | 2864 | u16 *x, u16 *y, u16 *w, u16 *h, |
| 2865 | bool enlarge_update_area) |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2866 | { |
| 2867 | u16 dw, dh; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2868 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2869 | dssdev->driver->get_resolution(dssdev, &dw, &dh); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2870 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2871 | if (*x > dw || *y > dh) |
| 2872 | return -EINVAL; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2873 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2874 | if (*x + *w > dw) |
| 2875 | return -EINVAL; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2876 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2877 | if (*y + *h > dh) |
| 2878 | return -EINVAL; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2879 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2880 | if (*w == 1) |
| 2881 | return -EINVAL; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2882 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2883 | if (*w == 0 || *h == 0) |
| 2884 | return -EINVAL; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2885 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2886 | dsi_perf_mark_setup(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2887 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2888 | if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) { |
Tomi Valkeinen | 26a8c25 | 2010-06-09 15:31:34 +0300 | [diff] [blame] | 2889 | dss_setup_partial_planes(dssdev, x, y, w, h, |
| 2890 | enlarge_update_area); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2891 | dispc_set_lcd_size(*w, *h); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2892 | } |
| 2893 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2894 | return 0; |
| 2895 | } |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2896 | EXPORT_SYMBOL(omap_dsi_prepare_update); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2897 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2898 | int omap_dsi_update(struct omap_dss_device *dssdev, |
| 2899 | int channel, |
| 2900 | u16 x, u16 y, u16 w, u16 h, |
| 2901 | void (*callback)(int, void *), void *data) |
| 2902 | { |
| 2903 | dsi.update_channel = channel; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2904 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2905 | if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) { |
| 2906 | dsi.framedone_callback = callback; |
| 2907 | dsi.framedone_data = data; |
| 2908 | |
| 2909 | dsi.update_region.x = x; |
| 2910 | dsi.update_region.y = y; |
| 2911 | dsi.update_region.w = w; |
| 2912 | dsi.update_region.h = h; |
| 2913 | dsi.update_region.device = dssdev; |
| 2914 | |
| 2915 | dsi_update_screen_dispc(dssdev, x, y, w, h); |
| 2916 | } else { |
| 2917 | dsi_update_screen_l4(dssdev, x, y, w, h); |
| 2918 | dsi_perf_show("L4"); |
| 2919 | callback(0, data); |
| 2920 | } |
| 2921 | |
| 2922 | return 0; |
| 2923 | } |
| 2924 | EXPORT_SYMBOL(omap_dsi_update); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2925 | |
| 2926 | /* Display funcs */ |
| 2927 | |
| 2928 | static int dsi_display_init_dispc(struct omap_dss_device *dssdev) |
| 2929 | { |
| 2930 | int r; |
| 2931 | |
| 2932 | r = omap_dispc_register_isr(dsi_framedone_irq_callback, NULL, |
| 2933 | DISPC_IRQ_FRAMEDONE); |
| 2934 | if (r) { |
| 2935 | DSSERR("can't get FRAMEDONE irq\n"); |
| 2936 | return r; |
| 2937 | } |
| 2938 | |
| 2939 | dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT); |
| 2940 | |
| 2941 | dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_DSI); |
| 2942 | dispc_enable_fifohandcheck(1); |
| 2943 | |
| 2944 | dispc_set_tft_data_lines(dssdev->ctrl.pixel_size); |
| 2945 | |
| 2946 | { |
| 2947 | struct omap_video_timings timings = { |
| 2948 | .hsw = 1, |
| 2949 | .hfp = 1, |
| 2950 | .hbp = 1, |
| 2951 | .vsw = 1, |
| 2952 | .vfp = 0, |
| 2953 | .vbp = 0, |
| 2954 | }; |
| 2955 | |
| 2956 | dispc_set_lcd_timings(&timings); |
| 2957 | } |
| 2958 | |
| 2959 | return 0; |
| 2960 | } |
| 2961 | |
| 2962 | static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev) |
| 2963 | { |
| 2964 | omap_dispc_unregister_isr(dsi_framedone_irq_callback, NULL, |
| 2965 | DISPC_IRQ_FRAMEDONE); |
| 2966 | } |
| 2967 | |
| 2968 | static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev) |
| 2969 | { |
| 2970 | struct dsi_clock_info cinfo; |
| 2971 | int r; |
| 2972 | |
| 2973 | /* we always use DSS2_FCK as input clock */ |
| 2974 | cinfo.use_dss2_fck = true; |
| 2975 | cinfo.regn = dssdev->phy.dsi.div.regn; |
| 2976 | cinfo.regm = dssdev->phy.dsi.div.regm; |
| 2977 | cinfo.regm3 = dssdev->phy.dsi.div.regm3; |
| 2978 | cinfo.regm4 = dssdev->phy.dsi.div.regm4; |
| 2979 | r = dsi_calc_clock_rates(&cinfo); |
Ville Syrjälä | ebf0a3f | 2010-04-22 22:50:05 +0200 | [diff] [blame] | 2980 | if (r) { |
| 2981 | DSSERR("Failed to calc dsi clocks\n"); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2982 | return r; |
Ville Syrjälä | ebf0a3f | 2010-04-22 22:50:05 +0200 | [diff] [blame] | 2983 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2984 | |
| 2985 | r = dsi_pll_set_clock_div(&cinfo); |
| 2986 | if (r) { |
| 2987 | DSSERR("Failed to set dsi clocks\n"); |
| 2988 | return r; |
| 2989 | } |
| 2990 | |
| 2991 | return 0; |
| 2992 | } |
| 2993 | |
| 2994 | static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev) |
| 2995 | { |
| 2996 | struct dispc_clock_info dispc_cinfo; |
| 2997 | int r; |
| 2998 | unsigned long long fck; |
| 2999 | |
| 3000 | fck = dsi_get_dsi1_pll_rate(); |
| 3001 | |
| 3002 | dispc_cinfo.lck_div = dssdev->phy.dsi.div.lck_div; |
| 3003 | dispc_cinfo.pck_div = dssdev->phy.dsi.div.pck_div; |
| 3004 | |
| 3005 | r = dispc_calc_clock_rates(fck, &dispc_cinfo); |
| 3006 | if (r) { |
| 3007 | DSSERR("Failed to calc dispc clocks\n"); |
| 3008 | return r; |
| 3009 | } |
| 3010 | |
| 3011 | r = dispc_set_clock_div(&dispc_cinfo); |
| 3012 | if (r) { |
| 3013 | DSSERR("Failed to set dispc clocks\n"); |
| 3014 | return r; |
| 3015 | } |
| 3016 | |
| 3017 | return 0; |
| 3018 | } |
| 3019 | |
| 3020 | static int dsi_display_init_dsi(struct omap_dss_device *dssdev) |
| 3021 | { |
| 3022 | int r; |
| 3023 | |
| 3024 | _dsi_print_reset_status(); |
| 3025 | |
| 3026 | r = dsi_pll_init(dssdev, true, true); |
| 3027 | if (r) |
| 3028 | goto err0; |
| 3029 | |
| 3030 | r = dsi_configure_dsi_clocks(dssdev); |
| 3031 | if (r) |
| 3032 | goto err1; |
| 3033 | |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 3034 | dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK); |
| 3035 | dss_select_dsi_clk_source(DSS_SRC_DSI2_PLL_FCLK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3036 | |
| 3037 | DSSDBG("PLL OK\n"); |
| 3038 | |
| 3039 | r = dsi_configure_dispc_clocks(dssdev); |
| 3040 | if (r) |
| 3041 | goto err2; |
| 3042 | |
| 3043 | r = dsi_complexio_init(dssdev); |
| 3044 | if (r) |
| 3045 | goto err2; |
| 3046 | |
| 3047 | _dsi_print_reset_status(); |
| 3048 | |
| 3049 | dsi_proto_timings(dssdev); |
| 3050 | dsi_set_lp_clk_divisor(dssdev); |
| 3051 | |
| 3052 | if (1) |
| 3053 | _dsi_print_reset_status(); |
| 3054 | |
| 3055 | r = dsi_proto_config(dssdev); |
| 3056 | if (r) |
| 3057 | goto err3; |
| 3058 | |
| 3059 | /* enable interface */ |
| 3060 | dsi_vc_enable(0, 1); |
Tomi Valkeinen | dd8079d | 2009-12-16 16:49:03 +0200 | [diff] [blame] | 3061 | dsi_vc_enable(1, 1); |
| 3062 | dsi_vc_enable(2, 1); |
| 3063 | dsi_vc_enable(3, 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3064 | dsi_if_enable(1); |
| 3065 | dsi_force_tx_stop_mode_io(); |
| 3066 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3067 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3068 | err3: |
| 3069 | dsi_complexio_uninit(); |
| 3070 | err2: |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 3071 | dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK); |
| 3072 | dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3073 | err1: |
| 3074 | dsi_pll_uninit(); |
| 3075 | err0: |
| 3076 | return r; |
| 3077 | } |
| 3078 | |
| 3079 | static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev) |
| 3080 | { |
Ville Syrjälä | d737010 | 2010-04-22 22:50:09 +0200 | [diff] [blame] | 3081 | /* disable interface */ |
| 3082 | dsi_if_enable(0); |
| 3083 | dsi_vc_enable(0, 0); |
| 3084 | dsi_vc_enable(1, 0); |
| 3085 | dsi_vc_enable(2, 0); |
| 3086 | dsi_vc_enable(3, 0); |
| 3087 | |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 3088 | dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK); |
| 3089 | dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3090 | dsi_complexio_uninit(); |
| 3091 | dsi_pll_uninit(); |
| 3092 | } |
| 3093 | |
| 3094 | static int dsi_core_init(void) |
| 3095 | { |
| 3096 | /* Autoidle */ |
| 3097 | REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0); |
| 3098 | |
| 3099 | /* ENWAKEUP */ |
| 3100 | REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2); |
| 3101 | |
| 3102 | /* SIDLEMODE smart-idle */ |
| 3103 | REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3); |
| 3104 | |
| 3105 | _dsi_initialize_irq(); |
| 3106 | |
| 3107 | return 0; |
| 3108 | } |
| 3109 | |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3110 | int omapdss_dsi_display_enable(struct omap_dss_device *dssdev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3111 | { |
| 3112 | int r = 0; |
| 3113 | |
| 3114 | DSSDBG("dsi_display_enable\n"); |
| 3115 | |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3116 | WARN_ON(!dsi_bus_is_locked()); |
| 3117 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3118 | mutex_lock(&dsi.lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3119 | |
| 3120 | r = omap_dss_start_device(dssdev); |
| 3121 | if (r) { |
| 3122 | DSSERR("failed to start device\n"); |
| 3123 | goto err0; |
| 3124 | } |
| 3125 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3126 | enable_clocks(1); |
| 3127 | dsi_enable_pll_clock(1); |
| 3128 | |
| 3129 | r = _dsi_reset(); |
| 3130 | if (r) |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3131 | goto err1; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3132 | |
| 3133 | dsi_core_init(); |
| 3134 | |
| 3135 | r = dsi_display_init_dispc(dssdev); |
| 3136 | if (r) |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3137 | goto err1; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3138 | |
| 3139 | r = dsi_display_init_dsi(dssdev); |
| 3140 | if (r) |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3141 | goto err2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3142 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3143 | mutex_unlock(&dsi.lock); |
| 3144 | |
| 3145 | return 0; |
| 3146 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3147 | err2: |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3148 | dsi_display_uninit_dispc(dssdev); |
| 3149 | err1: |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3150 | enable_clocks(0); |
| 3151 | dsi_enable_pll_clock(0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3152 | omap_dss_stop_device(dssdev); |
| 3153 | err0: |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3154 | mutex_unlock(&dsi.lock); |
| 3155 | DSSDBG("dsi_display_enable FAILED\n"); |
| 3156 | return r; |
| 3157 | } |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3158 | EXPORT_SYMBOL(omapdss_dsi_display_enable); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3159 | |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3160 | void omapdss_dsi_display_disable(struct omap_dss_device *dssdev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3161 | { |
| 3162 | DSSDBG("dsi_display_disable\n"); |
| 3163 | |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3164 | WARN_ON(!dsi_bus_is_locked()); |
| 3165 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3166 | mutex_lock(&dsi.lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3167 | |
| 3168 | dsi_display_uninit_dispc(dssdev); |
| 3169 | |
| 3170 | dsi_display_uninit_dsi(dssdev); |
| 3171 | |
| 3172 | enable_clocks(0); |
| 3173 | dsi_enable_pll_clock(0); |
| 3174 | |
| 3175 | omap_dss_stop_device(dssdev); |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3176 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3177 | mutex_unlock(&dsi.lock); |
| 3178 | } |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3179 | EXPORT_SYMBOL(omapdss_dsi_display_disable); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3180 | |
Tomi Valkeinen | 225b650 | 2010-01-11 15:11:01 +0200 | [diff] [blame] | 3181 | int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3182 | { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3183 | dsi.te_enabled = enable; |
Tomi Valkeinen | 225b650 | 2010-01-11 15:11:01 +0200 | [diff] [blame] | 3184 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3185 | } |
Tomi Valkeinen | 225b650 | 2010-01-11 15:11:01 +0200 | [diff] [blame] | 3186 | EXPORT_SYMBOL(omapdss_dsi_enable_te); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3187 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3188 | void dsi_get_overlay_fifo_thresholds(enum omap_plane plane, |
| 3189 | u32 fifo_size, enum omap_burst_size *burst_size, |
| 3190 | u32 *fifo_low, u32 *fifo_high) |
| 3191 | { |
| 3192 | unsigned burst_size_bytes; |
| 3193 | |
| 3194 | *burst_size = OMAP_DSS_BURST_16x32; |
| 3195 | burst_size_bytes = 16 * 32 / 8; |
| 3196 | |
| 3197 | *fifo_high = fifo_size - burst_size_bytes; |
| 3198 | *fifo_low = fifo_size - burst_size_bytes * 8; |
| 3199 | } |
| 3200 | |
| 3201 | int dsi_init_display(struct omap_dss_device *dssdev) |
| 3202 | { |
| 3203 | DSSDBG("DSI init\n"); |
| 3204 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3205 | /* XXX these should be figured out dynamically */ |
| 3206 | dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE | |
| 3207 | OMAP_DSS_DISPLAY_CAP_TEAR_ELIM; |
| 3208 | |
| 3209 | dsi.vc[0].dssdev = dssdev; |
| 3210 | dsi.vc[1].dssdev = dssdev; |
| 3211 | |
| 3212 | return 0; |
| 3213 | } |
| 3214 | |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 3215 | void dsi_wait_dsi1_pll_active(void) |
| 3216 | { |
| 3217 | if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1) |
| 3218 | DSSERR("DSI1 PLL clock not active\n"); |
| 3219 | } |
| 3220 | |
| 3221 | void dsi_wait_dsi2_pll_active(void) |
| 3222 | { |
| 3223 | if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1) |
| 3224 | DSSERR("DSI2 PLL clock not active\n"); |
| 3225 | } |
| 3226 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3227 | int dsi_init(struct platform_device *pdev) |
| 3228 | { |
| 3229 | u32 rev; |
| 3230 | int r; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3231 | |
| 3232 | spin_lock_init(&dsi.errors_lock); |
| 3233 | dsi.errors = 0; |
| 3234 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 3235 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 3236 | spin_lock_init(&dsi.irq_stats_lock); |
| 3237 | dsi.irq_stats.last_reset = jiffies; |
| 3238 | #endif |
| 3239 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3240 | init_completion(&dsi.bta_completion); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3241 | |
| 3242 | mutex_init(&dsi.lock); |
Tomi Valkeinen | b9eb5d7 | 2010-01-11 16:33:56 +0200 | [diff] [blame] | 3243 | sema_init(&dsi.bus_lock, 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3244 | |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 3245 | dsi.workqueue = create_singlethread_workqueue("dsi"); |
| 3246 | if (dsi.workqueue == NULL) |
| 3247 | return -ENOMEM; |
| 3248 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3249 | INIT_DELAYED_WORK_DEFERRABLE(&dsi.framedone_timeout_work, |
| 3250 | dsi_framedone_timeout_work_callback); |
| 3251 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3252 | #ifdef DSI_CATCH_MISSING_TE |
| 3253 | init_timer(&dsi.te_timer); |
| 3254 | dsi.te_timer.function = dsi_te_timeout; |
| 3255 | dsi.te_timer.data = 0; |
| 3256 | #endif |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3257 | dsi.base = ioremap(DSI_BASE, DSI_SZ_REGS); |
| 3258 | if (!dsi.base) { |
| 3259 | DSSERR("can't ioremap DSI\n"); |
| 3260 | r = -ENOMEM; |
| 3261 | goto err1; |
| 3262 | } |
| 3263 | |
Tomi Valkeinen | 8a2cfea | 2010-02-04 17:03:41 +0200 | [diff] [blame] | 3264 | dsi.vdds_dsi_reg = dss_get_vdds_dsi(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3265 | if (IS_ERR(dsi.vdds_dsi_reg)) { |
| 3266 | iounmap(dsi.base); |
| 3267 | DSSERR("can't get VDDS_DSI regulator\n"); |
| 3268 | r = PTR_ERR(dsi.vdds_dsi_reg); |
| 3269 | goto err2; |
| 3270 | } |
| 3271 | |
| 3272 | enable_clocks(1); |
| 3273 | |
| 3274 | rev = dsi_read_reg(DSI_REVISION); |
| 3275 | printk(KERN_INFO "OMAP DSI rev %d.%d\n", |
| 3276 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); |
| 3277 | |
| 3278 | enable_clocks(0); |
| 3279 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3280 | return 0; |
| 3281 | err2: |
| 3282 | iounmap(dsi.base); |
| 3283 | err1: |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 3284 | destroy_workqueue(dsi.workqueue); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3285 | return r; |
| 3286 | } |
| 3287 | |
| 3288 | void dsi_exit(void) |
| 3289 | { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3290 | iounmap(dsi.base); |
| 3291 | |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 3292 | destroy_workqueue(dsi.workqueue); |
| 3293 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3294 | DSSDBG("omap_dsi_exit\n"); |
| 3295 | } |
| 3296 | |