Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 1 | /* |
| 2 | * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC |
Josh Wu | b32313c | 2013-11-06 18:01:12 +0800 | [diff] [blame] | 3 | * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 4 | * |
| 5 | * Copyright (C) 2013 Atmel, |
| 6 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> |
| 7 | * |
| 8 | * Licensed under GPLv2 or later. |
| 9 | */ |
| 10 | |
Jean-Christophe PLAGNIOL-VILLARD | 6db64d2 | 2013-05-15 01:21:50 +0800 | [diff] [blame] | 11 | #include "skeleton.dtsi" |
Ludovic Desroches | d4ae89c | 2013-05-30 18:08:22 +0200 | [diff] [blame] | 12 | #include <dt-bindings/dma/at91.h> |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 13 | #include <dt-bindings/pinctrl/at91.h> |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 14 | #include <dt-bindings/interrupt-controller/irq.h> |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 15 | #include <dt-bindings/gpio/gpio.h> |
Tushar Behera | 35d35aa | 2014-03-06 11:34:43 +0530 | [diff] [blame] | 16 | #include <dt-bindings/clock/at91.h> |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 17 | |
| 18 | / { |
| 19 | model = "Atmel SAMA5D3 family SoC"; |
| 20 | compatible = "atmel,sama5d3", "atmel,sama5"; |
| 21 | interrupt-parent = <&aic>; |
| 22 | |
| 23 | aliases { |
| 24 | serial0 = &dbgu; |
| 25 | serial1 = &usart0; |
| 26 | serial2 = &usart1; |
| 27 | serial3 = &usart2; |
| 28 | serial4 = &usart3; |
| 29 | gpio0 = &pioA; |
| 30 | gpio1 = &pioB; |
| 31 | gpio2 = &pioC; |
| 32 | gpio3 = &pioD; |
| 33 | gpio4 = &pioE; |
| 34 | tcb0 = &tcb0; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 35 | i2c0 = &i2c0; |
| 36 | i2c1 = &i2c1; |
| 37 | i2c2 = &i2c2; |
| 38 | ssc0 = &ssc0; |
| 39 | ssc1 = &ssc1; |
Bo Shen | f3ab052 | 2013-12-19 11:59:17 +0800 | [diff] [blame] | 40 | pwm0 = &pwm0; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 41 | }; |
| 42 | cpus { |
Arnd Bergmann | 8b2efa89 | 2013-06-10 16:48:36 +0200 | [diff] [blame] | 43 | #address-cells = <1>; |
| 44 | #size-cells = <0>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 45 | cpu@0 { |
Lorenzo Pieralisi | e757a6e | 2013-04-18 18:31:35 +0100 | [diff] [blame] | 46 | device_type = "cpu"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 47 | compatible = "arm,cortex-a5"; |
Lorenzo Pieralisi | e757a6e | 2013-04-18 18:31:35 +0100 | [diff] [blame] | 48 | reg = <0x0>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 49 | }; |
| 50 | }; |
| 51 | |
Alexandre Belloni | d9da977 | 2013-08-05 17:26:06 +0200 | [diff] [blame] | 52 | pmu { |
| 53 | compatible = "arm,cortex-a5-pmu"; |
| 54 | interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>; |
| 55 | }; |
| 56 | |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 57 | memory { |
| 58 | reg = <0x20000000 0x8000000>; |
| 59 | }; |
| 60 | |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 61 | clocks { |
Alexandre Belloni | 334394c | 2014-06-17 15:30:20 +0200 | [diff] [blame] | 62 | slow_xtal: slow_xtal { |
| 63 | compatible = "fixed-clock"; |
| 64 | #clock-cells = <0>; |
| 65 | clock-frequency = <0>; |
| 66 | }; |
| 67 | |
| 68 | main_xtal: main_xtal { |
| 69 | compatible = "fixed-clock"; |
| 70 | #clock-cells = <0>; |
| 71 | clock-frequency = <0>; |
| 72 | }; |
| 73 | |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 74 | adc_op_clk: adc_op_clk{ |
| 75 | compatible = "fixed-clock"; |
| 76 | #clock-cells = <0>; |
| 77 | clock-frequency = <20000000>; |
| 78 | }; |
| 79 | }; |
| 80 | |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 81 | ahb { |
| 82 | compatible = "simple-bus"; |
| 83 | #address-cells = <1>; |
| 84 | #size-cells = <1>; |
| 85 | ranges; |
| 86 | |
| 87 | apb { |
| 88 | compatible = "simple-bus"; |
| 89 | #address-cells = <1>; |
| 90 | #size-cells = <1>; |
| 91 | ranges; |
| 92 | |
| 93 | mmc0: mmc@f0000000 { |
| 94 | compatible = "atmel,hsmci"; |
| 95 | reg = <0xf0000000 0x600>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 96 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; |
Ludovic Desroches | d4ae89c | 2013-05-30 18:08:22 +0200 | [diff] [blame] | 97 | dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>; |
Ludovic Desroches | 05c1bc9 | 2013-04-16 15:03:10 +0200 | [diff] [blame] | 98 | dma-names = "rxtx"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 99 | pinctrl-names = "default"; |
| 100 | pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; |
| 101 | status = "disabled"; |
| 102 | #address-cells = <1>; |
| 103 | #size-cells = <0>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 104 | clocks = <&mci0_clk>; |
| 105 | clock-names = "mci_clk"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 106 | }; |
| 107 | |
| 108 | spi0: spi@f0004000 { |
| 109 | #address-cells = <1>; |
| 110 | #size-cells = <0>; |
Nicolas Ferre | b7ef678 | 2013-06-24 12:04:55 +0200 | [diff] [blame] | 111 | compatible = "atmel,at91rm9200-spi"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 112 | reg = <0xf0004000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 113 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; |
Nicolas Ferre | e543a73 | 2013-06-24 12:16:05 +0200 | [diff] [blame] | 114 | dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>, |
| 115 | <&dma0 2 AT91_DMA_CFG_PER_ID(2)>; |
| 116 | dma-names = "tx", "rx"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 117 | pinctrl-names = "default"; |
| 118 | pinctrl-0 = <&pinctrl_spi0>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 119 | clocks = <&spi0_clk>; |
| 120 | clock-names = "spi_clk"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 121 | status = "disabled"; |
| 122 | }; |
| 123 | |
| 124 | ssc0: ssc@f0008000 { |
| 125 | compatible = "atmel,at91sam9g45-ssc"; |
| 126 | reg = <0xf0008000 0x4000>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 127 | interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; |
Bo Shen | 58962b7 | 2014-03-17 17:45:34 +0800 | [diff] [blame] | 128 | dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>, |
| 129 | <&dma0 2 AT91_DMA_CFG_PER_ID(14)>; |
| 130 | dma-names = "tx", "rx"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 131 | pinctrl-names = "default"; |
| 132 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 133 | clocks = <&ssc0_clk>; |
| 134 | clock-names = "pclk"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 135 | status = "disabled"; |
| 136 | }; |
| 137 | |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 138 | tcb0: timer@f0010000 { |
| 139 | compatible = "atmel,at91sam9x5-tcb"; |
| 140 | reg = <0xf0010000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 141 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 142 | clocks = <&tcb0_clk>; |
| 143 | clock-names = "t0_clk"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 144 | }; |
| 145 | |
| 146 | i2c0: i2c@f0014000 { |
| 147 | compatible = "atmel,at91sam9x5-i2c"; |
| 148 | reg = <0xf0014000 0x4000>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 149 | interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>; |
Ludovic Desroches | d4ae89c | 2013-05-30 18:08:22 +0200 | [diff] [blame] | 150 | dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>, |
| 151 | <&dma0 2 AT91_DMA_CFG_PER_ID(8)>; |
Ludovic Desroches | d9a63a4 | 2013-04-16 15:03:08 +0200 | [diff] [blame] | 152 | dma-names = "tx", "rx"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 153 | pinctrl-names = "default"; |
| 154 | pinctrl-0 = <&pinctrl_i2c0>; |
| 155 | #address-cells = <1>; |
| 156 | #size-cells = <0>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 157 | clocks = <&twi0_clk>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 158 | status = "disabled"; |
| 159 | }; |
| 160 | |
| 161 | i2c1: i2c@f0018000 { |
| 162 | compatible = "atmel,at91sam9x5-i2c"; |
| 163 | reg = <0xf0018000 0x4000>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 164 | interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>; |
Ludovic Desroches | d4ae89c | 2013-05-30 18:08:22 +0200 | [diff] [blame] | 165 | dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>, |
| 166 | <&dma0 2 AT91_DMA_CFG_PER_ID(10)>; |
Ludovic Desroches | d9a63a4 | 2013-04-16 15:03:08 +0200 | [diff] [blame] | 167 | dma-names = "tx", "rx"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 168 | pinctrl-names = "default"; |
| 169 | pinctrl-0 = <&pinctrl_i2c1>; |
| 170 | #address-cells = <1>; |
| 171 | #size-cells = <0>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 172 | clocks = <&twi1_clk>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 173 | status = "disabled"; |
| 174 | }; |
| 175 | |
| 176 | usart0: serial@f001c000 { |
| 177 | compatible = "atmel,at91sam9260-usart"; |
| 178 | reg = <0xf001c000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 179 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; |
Ludovic Desroches | d24cd78 | 2014-08-12 16:37:57 +0200 | [diff] [blame] | 180 | dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, |
| 181 | <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; |
| 182 | dma-names = "tx", "rx"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 183 | pinctrl-names = "default"; |
| 184 | pinctrl-0 = <&pinctrl_usart0>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 185 | clocks = <&usart0_clk>; |
| 186 | clock-names = "usart"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 187 | status = "disabled"; |
| 188 | }; |
| 189 | |
| 190 | usart1: serial@f0020000 { |
| 191 | compatible = "atmel,at91sam9260-usart"; |
| 192 | reg = <0xf0020000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 193 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; |
Ludovic Desroches | d24cd78 | 2014-08-12 16:37:57 +0200 | [diff] [blame] | 194 | dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>, |
| 195 | <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; |
| 196 | dma-names = "tx", "rx"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 197 | pinctrl-names = "default"; |
| 198 | pinctrl-0 = <&pinctrl_usart1>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 199 | clocks = <&usart1_clk>; |
| 200 | clock-names = "usart"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 201 | status = "disabled"; |
| 202 | }; |
| 203 | |
Bo Shen | f3ab052 | 2013-12-19 11:59:17 +0800 | [diff] [blame] | 204 | pwm0: pwm@f002c000 { |
| 205 | compatible = "atmel,sama5d3-pwm"; |
| 206 | reg = <0xf002c000 0x300>; |
| 207 | interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>; |
| 208 | #pwm-cells = <3>; |
| 209 | clocks = <&pwm_clk>; |
| 210 | status = "disabled"; |
| 211 | }; |
| 212 | |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 213 | isi: isi@f0034000 { |
| 214 | compatible = "atmel,at91sam9g45-isi"; |
| 215 | reg = <0xf0034000 0x4000>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 216 | interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 217 | status = "disabled"; |
| 218 | }; |
| 219 | |
| 220 | mmc1: mmc@f8000000 { |
| 221 | compatible = "atmel,hsmci"; |
| 222 | reg = <0xf8000000 0x600>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 223 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>; |
Ludovic Desroches | d4ae89c | 2013-05-30 18:08:22 +0200 | [diff] [blame] | 224 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>; |
Ludovic Desroches | 05c1bc9 | 2013-04-16 15:03:10 +0200 | [diff] [blame] | 225 | dma-names = "rxtx"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 226 | pinctrl-names = "default"; |
| 227 | pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; |
| 228 | status = "disabled"; |
| 229 | #address-cells = <1>; |
| 230 | #size-cells = <0>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 231 | clocks = <&mci1_clk>; |
| 232 | clock-names = "mci_clk"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 233 | }; |
| 234 | |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 235 | spi1: spi@f8008000 { |
| 236 | #address-cells = <1>; |
| 237 | #size-cells = <0>; |
Nicolas Ferre | b7ef678 | 2013-06-24 12:04:55 +0200 | [diff] [blame] | 238 | compatible = "atmel,at91rm9200-spi"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 239 | reg = <0xf8008000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 240 | interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; |
Nicolas Ferre | e543a73 | 2013-06-24 12:16:05 +0200 | [diff] [blame] | 241 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>, |
| 242 | <&dma1 2 AT91_DMA_CFG_PER_ID(16)>; |
| 243 | dma-names = "tx", "rx"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 244 | pinctrl-names = "default"; |
| 245 | pinctrl-0 = <&pinctrl_spi1>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 246 | clocks = <&spi1_clk>; |
| 247 | clock-names = "spi_clk"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 248 | status = "disabled"; |
| 249 | }; |
| 250 | |
| 251 | ssc1: ssc@f800c000 { |
| 252 | compatible = "atmel,at91sam9g45-ssc"; |
| 253 | reg = <0xf800c000 0x4000>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 254 | interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; |
Bo Shen | 58962b7 | 2014-03-17 17:45:34 +0800 | [diff] [blame] | 255 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>, |
| 256 | <&dma1 2 AT91_DMA_CFG_PER_ID(4)>; |
| 257 | dma-names = "tx", "rx"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 258 | pinctrl-names = "default"; |
| 259 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 260 | clocks = <&ssc1_clk>; |
| 261 | clock-names = "pclk"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 262 | status = "disabled"; |
| 263 | }; |
| 264 | |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 265 | adc0: adc@f8018000 { |
Alexandre Belloni | b3b84de | 2014-03-10 20:17:24 +0100 | [diff] [blame] | 266 | #address-cells = <1>; |
| 267 | #size-cells = <0>; |
Ludovic Desroches | 9879b96 | 2014-02-26 17:29:50 +0100 | [diff] [blame] | 268 | compatible = "atmel,at91sam9x5-adc"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 269 | reg = <0xf8018000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 270 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 271 | pinctrl-names = "default"; |
| 272 | pinctrl-0 = < |
| 273 | &pinctrl_adc0_adtrg |
| 274 | &pinctrl_adc0_ad0 |
| 275 | &pinctrl_adc0_ad1 |
| 276 | &pinctrl_adc0_ad2 |
| 277 | &pinctrl_adc0_ad3 |
| 278 | &pinctrl_adc0_ad4 |
| 279 | &pinctrl_adc0_ad5 |
| 280 | &pinctrl_adc0_ad6 |
| 281 | &pinctrl_adc0_ad7 |
| 282 | &pinctrl_adc0_ad8 |
| 283 | &pinctrl_adc0_ad9 |
| 284 | &pinctrl_adc0_ad10 |
| 285 | &pinctrl_adc0_ad11 |
| 286 | >; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 287 | clocks = <&adc_clk>, |
| 288 | <&adc_op_clk>; |
| 289 | clock-names = "adc_clk", "adc_op_clk"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 290 | atmel,adc-channels-used = <0xfff>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 291 | atmel,adc-startup-time = <40>; |
Alexandre Belloni | b3b84de | 2014-03-10 20:17:24 +0100 | [diff] [blame] | 292 | atmel,adc-use-external-triggers; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 293 | atmel,adc-vref = <3000>; |
| 294 | atmel,adc-res = <10 12>; |
| 295 | atmel,adc-res-names = "lowres", "highres"; |
| 296 | status = "disabled"; |
| 297 | |
| 298 | trigger@0 { |
Alexandre Belloni | b3b84de | 2014-03-10 20:17:24 +0100 | [diff] [blame] | 299 | reg = <0>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 300 | trigger-name = "external-rising"; |
| 301 | trigger-value = <0x1>; |
| 302 | trigger-external; |
| 303 | }; |
| 304 | trigger@1 { |
Alexandre Belloni | b3b84de | 2014-03-10 20:17:24 +0100 | [diff] [blame] | 305 | reg = <1>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 306 | trigger-name = "external-falling"; |
| 307 | trigger-value = <0x2>; |
| 308 | trigger-external; |
| 309 | }; |
| 310 | trigger@2 { |
Alexandre Belloni | b3b84de | 2014-03-10 20:17:24 +0100 | [diff] [blame] | 311 | reg = <2>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 312 | trigger-name = "external-any"; |
| 313 | trigger-value = <0x3>; |
| 314 | trigger-external; |
| 315 | }; |
| 316 | trigger@3 { |
Alexandre Belloni | b3b84de | 2014-03-10 20:17:24 +0100 | [diff] [blame] | 317 | reg = <3>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 318 | trigger-name = "continuous"; |
| 319 | trigger-value = <0x6>; |
| 320 | }; |
| 321 | }; |
| 322 | |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 323 | i2c2: i2c@f801c000 { |
| 324 | compatible = "atmel,at91sam9x5-i2c"; |
| 325 | reg = <0xf801c000 0x4000>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 326 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>; |
Ludovic Desroches | d4ae89c | 2013-05-30 18:08:22 +0200 | [diff] [blame] | 327 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>, |
| 328 | <&dma1 2 AT91_DMA_CFG_PER_ID(12)>; |
Ludovic Desroches | d9a63a4 | 2013-04-16 15:03:08 +0200 | [diff] [blame] | 329 | dma-names = "tx", "rx"; |
Nicolas Ferre | 557844e | 2013-12-02 17:18:48 +0100 | [diff] [blame] | 330 | pinctrl-names = "default"; |
| 331 | pinctrl-0 = <&pinctrl_i2c2>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 332 | #address-cells = <1>; |
| 333 | #size-cells = <0>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 334 | clocks = <&twi2_clk>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 335 | status = "disabled"; |
| 336 | }; |
| 337 | |
| 338 | usart2: serial@f8020000 { |
| 339 | compatible = "atmel,at91sam9260-usart"; |
| 340 | reg = <0xf8020000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 341 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; |
Ludovic Desroches | d24cd78 | 2014-08-12 16:37:57 +0200 | [diff] [blame] | 342 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>, |
| 343 | <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>; |
| 344 | dma-names = "tx", "rx"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 345 | pinctrl-names = "default"; |
| 346 | pinctrl-0 = <&pinctrl_usart2>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 347 | clocks = <&usart2_clk>; |
| 348 | clock-names = "usart"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 349 | status = "disabled"; |
| 350 | }; |
| 351 | |
| 352 | usart3: serial@f8024000 { |
| 353 | compatible = "atmel,at91sam9260-usart"; |
| 354 | reg = <0xf8024000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 355 | interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; |
Ludovic Desroches | d24cd78 | 2014-08-12 16:37:57 +0200 | [diff] [blame] | 356 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>, |
| 357 | <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>; |
| 358 | dma-names = "tx", "rx"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 359 | pinctrl-names = "default"; |
| 360 | pinctrl-0 = <&pinctrl_usart3>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 361 | clocks = <&usart3_clk>; |
| 362 | clock-names = "usart"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 363 | status = "disabled"; |
| 364 | }; |
| 365 | |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 366 | sha@f8034000 { |
Nicolas Ferre | c76f266 | 2013-10-11 16:57:57 +0200 | [diff] [blame] | 367 | compatible = "atmel,at91sam9g46-sha"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 368 | reg = <0xf8034000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 369 | interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; |
Nicolas Ferre | 9860c51 | 2013-10-11 16:59:46 +0200 | [diff] [blame] | 370 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>; |
| 371 | dma-names = "tx"; |
Boris BREZILLON | 4df4f44 | 2013-12-19 16:11:13 +0100 | [diff] [blame] | 372 | clocks = <&sha_clk>; |
| 373 | clock-names = "sha_clk"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 374 | }; |
| 375 | |
| 376 | aes@f8038000 { |
Nicolas Ferre | c76f266 | 2013-10-11 16:57:57 +0200 | [diff] [blame] | 377 | compatible = "atmel,at91sam9g46-aes"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 378 | reg = <0xf8038000 0x100>; |
Nicolas Ferre | 07f7d50 | 2013-10-11 14:45:44 +0200 | [diff] [blame] | 379 | interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>; |
Nicolas Ferre | 9860c51 | 2013-10-11 16:59:46 +0200 | [diff] [blame] | 380 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>, |
| 381 | <&dma1 2 AT91_DMA_CFG_PER_ID(19)>; |
| 382 | dma-names = "tx", "rx"; |
Boris BREZILLON | f68cd35 | 2013-12-19 16:11:14 +0100 | [diff] [blame] | 383 | clocks = <&aes_clk>; |
| 384 | clock-names = "aes_clk"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 385 | }; |
| 386 | |
| 387 | tdes@f803c000 { |
Nicolas Ferre | c76f266 | 2013-10-11 16:57:57 +0200 | [diff] [blame] | 388 | compatible = "atmel,at91sam9g46-tdes"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 389 | reg = <0xf803c000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 390 | interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; |
Nicolas Ferre | 9860c51 | 2013-10-11 16:59:46 +0200 | [diff] [blame] | 391 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>, |
| 392 | <&dma1 2 AT91_DMA_CFG_PER_ID(21)>; |
| 393 | dma-names = "tx", "rx"; |
Boris BREZILLON | 45e5c2c | 2013-12-19 16:11:15 +0100 | [diff] [blame] | 394 | clocks = <&tdes_clk>; |
| 395 | clock-names = "tdes_clk"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 396 | }; |
| 397 | |
| 398 | dma0: dma-controller@ffffe600 { |
| 399 | compatible = "atmel,at91sam9g45-dma"; |
| 400 | reg = <0xffffe600 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 401 | interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; |
Ludovic Desroches | 980ce7d | 2013-04-16 15:03:06 +0200 | [diff] [blame] | 402 | #dma-cells = <2>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 403 | clocks = <&dma0_clk>; |
| 404 | clock-names = "dma_clk"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 405 | }; |
| 406 | |
| 407 | dma1: dma-controller@ffffe800 { |
| 408 | compatible = "atmel,at91sam9g45-dma"; |
| 409 | reg = <0xffffe800 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 410 | interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; |
Ludovic Desroches | 980ce7d | 2013-04-16 15:03:06 +0200 | [diff] [blame] | 411 | #dma-cells = <2>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 412 | clocks = <&dma1_clk>; |
| 413 | clock-names = "dma_clk"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 414 | }; |
| 415 | |
| 416 | ramc0: ramc@ffffea00 { |
Alexandre Belloni | 063de89 | 2014-07-08 18:21:14 +0200 | [diff] [blame] | 417 | compatible = "atmel,sama5d3-ddramc"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 418 | reg = <0xffffea00 0x200>; |
Alexandre Belloni | 063de89 | 2014-07-08 18:21:14 +0200 | [diff] [blame] | 419 | clocks = <&ddrck>, <&mpddr_clk>; |
| 420 | clock-names = "ddrck", "mpddr"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 421 | }; |
| 422 | |
| 423 | dbgu: serial@ffffee00 { |
| 424 | compatible = "atmel,at91sam9260-usart"; |
| 425 | reg = <0xffffee00 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 426 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; |
Ludovic Desroches | d24cd78 | 2014-08-12 16:37:57 +0200 | [diff] [blame] | 427 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>, |
| 428 | <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>; |
| 429 | dma-names = "tx", "rx"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 430 | pinctrl-names = "default"; |
| 431 | pinctrl-0 = <&pinctrl_dbgu>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 432 | clocks = <&dbgu_clk>; |
| 433 | clock-names = "usart"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 434 | status = "disabled"; |
| 435 | }; |
| 436 | |
| 437 | aic: interrupt-controller@fffff000 { |
| 438 | #interrupt-cells = <3>; |
| 439 | compatible = "atmel,sama5d3-aic"; |
| 440 | interrupt-controller; |
| 441 | reg = <0xfffff000 0x200>; |
| 442 | atmel,external-irqs = <47>; |
| 443 | }; |
| 444 | |
| 445 | pinctrl@fffff200 { |
| 446 | #address-cells = <1>; |
| 447 | #size-cells = <1>; |
Marek Roszko | e0065cf | 2014-08-23 23:12:05 -0400 | [diff] [blame] | 448 | compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 449 | ranges = <0xfffff200 0xfffff200 0xa00>; |
| 450 | atmel,mux-mask = < |
| 451 | /* A B C */ |
| 452 | 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */ |
| 453 | 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */ |
| 454 | 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */ |
| 455 | 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */ |
| 456 | 0xffffffff 0xbf9f8000 0x18000000 /* pioE */ |
| 457 | >; |
| 458 | |
| 459 | /* shared pinctrl settings */ |
| 460 | adc0 { |
| 461 | pinctrl_adc0_adtrg: adc0_adtrg { |
| 462 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 463 | <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */ |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 464 | }; |
| 465 | pinctrl_adc0_ad0: adc0_ad0 { |
| 466 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 467 | <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */ |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 468 | }; |
| 469 | pinctrl_adc0_ad1: adc0_ad1 { |
| 470 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 471 | <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */ |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 472 | }; |
| 473 | pinctrl_adc0_ad2: adc0_ad2 { |
| 474 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 475 | <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */ |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 476 | }; |
| 477 | pinctrl_adc0_ad3: adc0_ad3 { |
| 478 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 479 | <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */ |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 480 | }; |
| 481 | pinctrl_adc0_ad4: adc0_ad4 { |
| 482 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 483 | <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */ |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 484 | }; |
| 485 | pinctrl_adc0_ad5: adc0_ad5 { |
| 486 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 487 | <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */ |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 488 | }; |
| 489 | pinctrl_adc0_ad6: adc0_ad6 { |
| 490 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 491 | <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */ |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 492 | }; |
| 493 | pinctrl_adc0_ad7: adc0_ad7 { |
| 494 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 495 | <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */ |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 496 | }; |
| 497 | pinctrl_adc0_ad8: adc0_ad8 { |
| 498 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 499 | <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */ |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 500 | }; |
| 501 | pinctrl_adc0_ad9: adc0_ad9 { |
| 502 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 503 | <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */ |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 504 | }; |
| 505 | pinctrl_adc0_ad10: adc0_ad10 { |
| 506 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 507 | <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */ |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 508 | }; |
| 509 | pinctrl_adc0_ad11: adc0_ad11 { |
| 510 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 511 | <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */ |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 512 | }; |
| 513 | }; |
| 514 | |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 515 | dbgu { |
| 516 | pinctrl_dbgu: dbgu-0 { |
| 517 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 518 | <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */ |
| 519 | AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */ |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 520 | }; |
| 521 | }; |
| 522 | |
| 523 | i2c0 { |
| 524 | pinctrl_i2c0: i2c0-0 { |
| 525 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 526 | <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */ |
| 527 | AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 528 | }; |
| 529 | }; |
| 530 | |
| 531 | i2c1 { |
| 532 | pinctrl_i2c1: i2c1-0 { |
| 533 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 534 | <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */ |
| 535 | AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 536 | }; |
| 537 | }; |
| 538 | |
Nicolas Ferre | 557844e | 2013-12-02 17:18:48 +0100 | [diff] [blame] | 539 | i2c2 { |
| 540 | pinctrl_i2c2: i2c2-0 { |
| 541 | atmel,pins = |
| 542 | <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */ |
| 543 | AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */ |
| 544 | }; |
| 545 | }; |
| 546 | |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 547 | isi { |
| 548 | pinctrl_isi: isi-0 { |
| 549 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 550 | <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */ |
| 551 | AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */ |
| 552 | AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */ |
| 553 | AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */ |
| 554 | AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */ |
| 555 | AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */ |
| 556 | AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */ |
| 557 | AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */ |
| 558 | AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */ |
| 559 | AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */ |
| 560 | AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ |
| 561 | AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */ |
| 562 | AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 563 | }; |
| 564 | pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 { |
| 565 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 566 | <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */ |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 567 | }; |
| 568 | }; |
| 569 | |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 570 | mmc0 { |
| 571 | pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { |
| 572 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 573 | <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */ |
| 574 | AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */ |
| 575 | AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */ |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 576 | }; |
| 577 | pinctrl_mmc0_dat1_3: mmc0_dat1_3 { |
| 578 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 579 | <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */ |
| 580 | AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */ |
| 581 | AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */ |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 582 | }; |
| 583 | pinctrl_mmc0_dat4_7: mmc0_dat4_7 { |
| 584 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 585 | <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */ |
| 586 | AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */ |
| 587 | AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */ |
| 588 | AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 589 | }; |
| 590 | }; |
| 591 | |
| 592 | mmc1 { |
| 593 | pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { |
| 594 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 595 | <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */ |
| 596 | AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */ |
| 597 | AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 598 | }; |
| 599 | pinctrl_mmc1_dat1_3: mmc1_dat1_3 { |
| 600 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 601 | <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */ |
| 602 | AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */ |
| 603 | AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 604 | }; |
| 605 | }; |
| 606 | |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 607 | nand0 { |
| 608 | pinctrl_nand0_ale_cle: nand0_ale_cle-0 { |
| 609 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 610 | <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */ |
| 611 | AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */ |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 612 | }; |
| 613 | }; |
| 614 | |
Nicolas Ferre | 5eefd5f | 2014-04-24 17:33:51 +0200 | [diff] [blame] | 615 | pwm0 { |
| 616 | pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 { |
| 617 | atmel,pins = |
| 618 | <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D4 and LCDDAT20 */ |
| 619 | }; |
| 620 | pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 { |
| 621 | atmel,pins = |
| 622 | <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX0 */ |
| 623 | }; |
| 624 | pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 { |
| 625 | atmel,pins = |
| 626 | <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D5 and LCDDAT21 */ |
| 627 | }; |
| 628 | pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 { |
| 629 | atmel,pins = |
| 630 | <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX1 */ |
| 631 | }; |
| 632 | |
| 633 | pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 { |
| 634 | atmel,pins = |
| 635 | <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D6 and LCDDAT22 */ |
| 636 | }; |
| 637 | pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 { |
| 638 | atmel,pins = |
| 639 | <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX0 */ |
| 640 | }; |
| 641 | pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 { |
| 642 | atmel,pins = |
| 643 | <AT91_PIOB 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with G125CKO and RTS1 */ |
| 644 | }; |
| 645 | pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 { |
| 646 | atmel,pins = |
| 647 | <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D7 and LCDDAT23 */ |
| 648 | }; |
| 649 | pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 { |
| 650 | atmel,pins = |
| 651 | <AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX1 */ |
| 652 | }; |
| 653 | pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 { |
| 654 | atmel,pins = |
| 655 | <AT91_PIOE 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with IRQ */ |
| 656 | }; |
| 657 | |
| 658 | pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 { |
| 659 | atmel,pins = |
| 660 | <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXCK */ |
| 661 | }; |
| 662 | pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 { |
| 663 | atmel,pins = |
| 664 | <AT91_PIOD 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA4 and TIOA0 */ |
| 665 | }; |
| 666 | pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 { |
| 667 | atmel,pins = |
| 668 | <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXEN */ |
| 669 | }; |
| 670 | pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 { |
| 671 | atmel,pins = |
| 672 | <AT91_PIOD 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA5 and TIOB0 */ |
| 673 | }; |
| 674 | |
| 675 | pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 { |
| 676 | atmel,pins = |
| 677 | <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXDV */ |
| 678 | }; |
| 679 | pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 { |
| 680 | atmel,pins = |
| 681 | <AT91_PIOD 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA6 and TCLK0 */ |
| 682 | }; |
| 683 | pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 { |
| 684 | atmel,pins = |
| 685 | <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXER */ |
| 686 | }; |
| 687 | pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 { |
| 688 | atmel,pins = |
| 689 | <AT91_PIOD 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA7 */ |
| 690 | }; |
| 691 | }; |
| 692 | |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 693 | spi0 { |
| 694 | pinctrl_spi0: spi0-0 { |
| 695 | atmel,pins = |
| 696 | <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */ |
| 697 | AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */ |
| 698 | AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */ |
| 699 | }; |
| 700 | }; |
| 701 | |
| 702 | spi1 { |
| 703 | pinctrl_spi1: spi1-0 { |
| 704 | atmel,pins = |
| 705 | <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */ |
| 706 | AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */ |
| 707 | AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */ |
| 708 | }; |
| 709 | }; |
| 710 | |
| 711 | ssc0 { |
| 712 | pinctrl_ssc0_tx: ssc0_tx { |
| 713 | atmel,pins = |
| 714 | <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */ |
| 715 | AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */ |
| 716 | AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */ |
| 717 | }; |
| 718 | |
| 719 | pinctrl_ssc0_rx: ssc0_rx { |
| 720 | atmel,pins = |
| 721 | <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */ |
| 722 | AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */ |
| 723 | AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */ |
| 724 | }; |
| 725 | }; |
| 726 | |
| 727 | ssc1 { |
| 728 | pinctrl_ssc1_tx: ssc1_tx { |
| 729 | atmel,pins = |
| 730 | <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */ |
| 731 | AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */ |
| 732 | AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */ |
| 733 | }; |
| 734 | |
| 735 | pinctrl_ssc1_rx: ssc1_rx { |
| 736 | atmel,pins = |
| 737 | <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */ |
| 738 | AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */ |
| 739 | AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */ |
| 740 | }; |
| 741 | }; |
| 742 | |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 743 | usart0 { |
| 744 | pinctrl_usart0: usart0-0 { |
| 745 | atmel,pins = |
| 746 | <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */ |
| 747 | AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */ |
| 748 | }; |
| 749 | |
| 750 | pinctrl_usart0_rts_cts: usart0_rts_cts-0 { |
| 751 | atmel,pins = |
| 752 | <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */ |
| 753 | AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ |
| 754 | }; |
| 755 | }; |
| 756 | |
| 757 | usart1 { |
| 758 | pinctrl_usart1: usart1-0 { |
| 759 | atmel,pins = |
| 760 | <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */ |
| 761 | AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */ |
| 762 | }; |
| 763 | |
| 764 | pinctrl_usart1_rts_cts: usart1_rts_cts-0 { |
| 765 | atmel,pins = |
| 766 | <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */ |
| 767 | AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */ |
| 768 | }; |
| 769 | }; |
| 770 | |
| 771 | usart2 { |
| 772 | pinctrl_usart2: usart2-0 { |
| 773 | atmel,pins = |
| 774 | <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */ |
| 775 | AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */ |
| 776 | }; |
| 777 | |
| 778 | pinctrl_usart2_rts_cts: usart2_rts_cts-0 { |
| 779 | atmel,pins = |
| 780 | <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */ |
| 781 | AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */ |
| 782 | }; |
| 783 | }; |
| 784 | |
| 785 | usart3 { |
| 786 | pinctrl_usart3: usart3-0 { |
| 787 | atmel,pins = |
| 788 | <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */ |
| 789 | AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */ |
| 790 | }; |
| 791 | |
| 792 | pinctrl_usart3_rts_cts: usart3_rts_cts-0 { |
| 793 | atmel,pins = |
| 794 | <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */ |
| 795 | AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */ |
| 796 | }; |
| 797 | }; |
| 798 | |
| 799 | |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 800 | pioA: gpio@fffff200 { |
| 801 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 802 | reg = <0xfffff200 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 803 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 804 | #gpio-cells = <2>; |
| 805 | gpio-controller; |
| 806 | interrupt-controller; |
| 807 | #interrupt-cells = <2>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 808 | clocks = <&pioA_clk>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 809 | }; |
| 810 | |
| 811 | pioB: gpio@fffff400 { |
| 812 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 813 | reg = <0xfffff400 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 814 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 815 | #gpio-cells = <2>; |
| 816 | gpio-controller; |
| 817 | interrupt-controller; |
| 818 | #interrupt-cells = <2>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 819 | clocks = <&pioB_clk>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 820 | }; |
| 821 | |
| 822 | pioC: gpio@fffff600 { |
| 823 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 824 | reg = <0xfffff600 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 825 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 826 | #gpio-cells = <2>; |
| 827 | gpio-controller; |
| 828 | interrupt-controller; |
| 829 | #interrupt-cells = <2>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 830 | clocks = <&pioC_clk>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 831 | }; |
| 832 | |
| 833 | pioD: gpio@fffff800 { |
| 834 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 835 | reg = <0xfffff800 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 836 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 837 | #gpio-cells = <2>; |
| 838 | gpio-controller; |
| 839 | interrupt-controller; |
| 840 | #interrupt-cells = <2>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 841 | clocks = <&pioD_clk>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 842 | }; |
| 843 | |
| 844 | pioE: gpio@fffffa00 { |
| 845 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 846 | reg = <0xfffffa00 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 847 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 848 | #gpio-cells = <2>; |
| 849 | gpio-controller; |
| 850 | interrupt-controller; |
| 851 | #interrupt-cells = <2>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 852 | clocks = <&pioE_clk>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 853 | }; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 854 | }; |
| 855 | |
| 856 | pmc: pmc@fffffc00 { |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 857 | compatible = "atmel,sama5d3-pmc"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 858 | reg = <0xfffffc00 0x120>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 859 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 860 | interrupt-controller; |
| 861 | #address-cells = <1>; |
| 862 | #size-cells = <0>; |
| 863 | #interrupt-cells = <1>; |
| 864 | |
Boris BREZILLON | 4753219 | 2014-04-22 15:12:34 +0200 | [diff] [blame] | 865 | main_rc_osc: main_rc_osc { |
| 866 | compatible = "atmel,at91sam9x5-clk-main-rc-osc"; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 867 | #clock-cells = <0>; |
Boris BREZILLON | 4753219 | 2014-04-22 15:12:34 +0200 | [diff] [blame] | 868 | interrupt-parent = <&pmc>; |
| 869 | interrupts = <AT91_PMC_MOSCRCS>; |
| 870 | clock-frequency = <12000000>; |
| 871 | clock-accuracy = <50000000>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 872 | }; |
| 873 | |
Boris BREZILLON | 4753219 | 2014-04-22 15:12:34 +0200 | [diff] [blame] | 874 | main_osc: main_osc { |
| 875 | compatible = "atmel,at91rm9200-clk-main-osc"; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 876 | #clock-cells = <0>; |
| 877 | interrupt-parent = <&pmc>; |
| 878 | interrupts = <AT91_PMC_MOSCS>; |
Boris BREZILLON | 4753219 | 2014-04-22 15:12:34 +0200 | [diff] [blame] | 879 | clocks = <&main_xtal>; |
| 880 | }; |
| 881 | |
| 882 | main: mainck { |
| 883 | compatible = "atmel,at91sam9x5-clk-main"; |
| 884 | #clock-cells = <0>; |
| 885 | interrupt-parent = <&pmc>; |
| 886 | interrupts = <AT91_PMC_MOSCSELS>; |
| 887 | clocks = <&main_rc_osc &main_osc>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 888 | }; |
| 889 | |
| 890 | plla: pllack { |
| 891 | compatible = "atmel,sama5d3-clk-pll"; |
| 892 | #clock-cells = <0>; |
| 893 | interrupt-parent = <&pmc>; |
| 894 | interrupts = <AT91_PMC_LOCKA>; |
| 895 | clocks = <&main>; |
| 896 | reg = <0>; |
| 897 | atmel,clk-input-range = <8000000 50000000>; |
| 898 | #atmel,pll-clk-output-range-cells = <4>; |
| 899 | atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>; |
| 900 | }; |
| 901 | |
| 902 | plladiv: plladivck { |
| 903 | compatible = "atmel,at91sam9x5-clk-plldiv"; |
| 904 | #clock-cells = <0>; |
| 905 | clocks = <&plla>; |
| 906 | }; |
| 907 | |
| 908 | utmi: utmick { |
| 909 | compatible = "atmel,at91sam9x5-clk-utmi"; |
| 910 | #clock-cells = <0>; |
| 911 | interrupt-parent = <&pmc>; |
| 912 | interrupts = <AT91_PMC_LOCKU>; |
| 913 | clocks = <&main>; |
| 914 | }; |
| 915 | |
| 916 | mck: masterck { |
| 917 | compatible = "atmel,at91sam9x5-clk-master"; |
| 918 | #clock-cells = <0>; |
| 919 | interrupt-parent = <&pmc>; |
| 920 | interrupts = <AT91_PMC_MCKRDY>; |
| 921 | clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; |
| 922 | atmel,clk-output-range = <0 166000000>; |
| 923 | atmel,clk-divisors = <1 2 4 3>; |
| 924 | }; |
| 925 | |
| 926 | usb: usbck { |
| 927 | compatible = "atmel,at91sam9x5-clk-usb"; |
| 928 | #clock-cells = <0>; |
| 929 | clocks = <&plladiv>, <&utmi>; |
| 930 | }; |
| 931 | |
| 932 | prog: progck { |
| 933 | compatible = "atmel,at91sam9x5-clk-programmable"; |
| 934 | #address-cells = <1>; |
| 935 | #size-cells = <0>; |
| 936 | interrupt-parent = <&pmc>; |
| 937 | clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; |
| 938 | |
| 939 | prog0: prog0 { |
| 940 | #clock-cells = <0>; |
| 941 | reg = <0>; |
| 942 | interrupts = <AT91_PMC_PCKRDY(0)>; |
| 943 | }; |
| 944 | |
| 945 | prog1: prog1 { |
| 946 | #clock-cells = <0>; |
| 947 | reg = <1>; |
| 948 | interrupts = <AT91_PMC_PCKRDY(1)>; |
| 949 | }; |
| 950 | |
| 951 | prog2: prog2 { |
| 952 | #clock-cells = <0>; |
| 953 | reg = <2>; |
| 954 | interrupts = <AT91_PMC_PCKRDY(2)>; |
| 955 | }; |
| 956 | }; |
| 957 | |
| 958 | smd: smdclk { |
| 959 | compatible = "atmel,at91sam9x5-clk-smd"; |
| 960 | #clock-cells = <0>; |
| 961 | clocks = <&plladiv>, <&utmi>; |
| 962 | }; |
| 963 | |
| 964 | systemck { |
| 965 | compatible = "atmel,at91rm9200-clk-system"; |
| 966 | #address-cells = <1>; |
| 967 | #size-cells = <0>; |
| 968 | |
| 969 | ddrck: ddrck { |
| 970 | #clock-cells = <0>; |
| 971 | reg = <2>; |
| 972 | clocks = <&mck>; |
| 973 | }; |
| 974 | |
| 975 | smdck: smdck { |
| 976 | #clock-cells = <0>; |
| 977 | reg = <4>; |
| 978 | clocks = <&smd>; |
| 979 | }; |
| 980 | |
| 981 | uhpck: uhpck { |
| 982 | #clock-cells = <0>; |
| 983 | reg = <6>; |
| 984 | clocks = <&usb>; |
| 985 | }; |
| 986 | |
| 987 | udpck: udpck { |
| 988 | #clock-cells = <0>; |
| 989 | reg = <7>; |
| 990 | clocks = <&usb>; |
| 991 | }; |
| 992 | |
| 993 | pck0: pck0 { |
| 994 | #clock-cells = <0>; |
| 995 | reg = <8>; |
| 996 | clocks = <&prog0>; |
| 997 | }; |
| 998 | |
| 999 | pck1: pck1 { |
| 1000 | #clock-cells = <0>; |
| 1001 | reg = <9>; |
| 1002 | clocks = <&prog1>; |
| 1003 | }; |
| 1004 | |
| 1005 | pck2: pck2 { |
| 1006 | #clock-cells = <0>; |
| 1007 | reg = <10>; |
| 1008 | clocks = <&prog2>; |
| 1009 | }; |
| 1010 | }; |
| 1011 | |
| 1012 | periphck { |
| 1013 | compatible = "atmel,at91sam9x5-clk-peripheral"; |
| 1014 | #address-cells = <1>; |
| 1015 | #size-cells = <0>; |
| 1016 | clocks = <&mck>; |
| 1017 | |
| 1018 | dbgu_clk: dbgu_clk { |
| 1019 | #clock-cells = <0>; |
| 1020 | reg = <2>; |
| 1021 | }; |
| 1022 | |
Alexandre Belloni | 8a85ba2 | 2014-09-16 10:43:57 +0200 | [diff] [blame] | 1023 | hsmc_clk: hsmc_clk { |
| 1024 | #clock-cells = <0>; |
| 1025 | reg = <5>; |
| 1026 | }; |
| 1027 | |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 1028 | pioA_clk: pioA_clk { |
| 1029 | #clock-cells = <0>; |
| 1030 | reg = <6>; |
| 1031 | }; |
| 1032 | |
| 1033 | pioB_clk: pioB_clk { |
| 1034 | #clock-cells = <0>; |
| 1035 | reg = <7>; |
| 1036 | }; |
| 1037 | |
| 1038 | pioC_clk: pioC_clk { |
| 1039 | #clock-cells = <0>; |
| 1040 | reg = <8>; |
| 1041 | }; |
| 1042 | |
| 1043 | pioD_clk: pioD_clk { |
| 1044 | #clock-cells = <0>; |
| 1045 | reg = <9>; |
| 1046 | }; |
| 1047 | |
| 1048 | pioE_clk: pioE_clk { |
| 1049 | #clock-cells = <0>; |
| 1050 | reg = <10>; |
| 1051 | }; |
| 1052 | |
| 1053 | usart0_clk: usart0_clk { |
| 1054 | #clock-cells = <0>; |
| 1055 | reg = <12>; |
| 1056 | atmel,clk-output-range = <0 66000000>; |
| 1057 | }; |
| 1058 | |
| 1059 | usart1_clk: usart1_clk { |
| 1060 | #clock-cells = <0>; |
| 1061 | reg = <13>; |
| 1062 | atmel,clk-output-range = <0 66000000>; |
| 1063 | }; |
| 1064 | |
| 1065 | usart2_clk: usart2_clk { |
| 1066 | #clock-cells = <0>; |
| 1067 | reg = <14>; |
| 1068 | atmel,clk-output-range = <0 66000000>; |
| 1069 | }; |
| 1070 | |
| 1071 | usart3_clk: usart3_clk { |
| 1072 | #clock-cells = <0>; |
| 1073 | reg = <15>; |
| 1074 | atmel,clk-output-range = <0 66000000>; |
| 1075 | }; |
| 1076 | |
| 1077 | twi0_clk: twi0_clk { |
| 1078 | reg = <18>; |
| 1079 | #clock-cells = <0>; |
| 1080 | atmel,clk-output-range = <0 16625000>; |
| 1081 | }; |
| 1082 | |
| 1083 | twi1_clk: twi1_clk { |
| 1084 | #clock-cells = <0>; |
| 1085 | reg = <19>; |
| 1086 | atmel,clk-output-range = <0 16625000>; |
| 1087 | }; |
| 1088 | |
| 1089 | twi2_clk: twi2_clk { |
| 1090 | #clock-cells = <0>; |
| 1091 | reg = <20>; |
| 1092 | atmel,clk-output-range = <0 16625000>; |
| 1093 | }; |
| 1094 | |
| 1095 | mci0_clk: mci0_clk { |
| 1096 | #clock-cells = <0>; |
| 1097 | reg = <21>; |
| 1098 | }; |
| 1099 | |
| 1100 | mci1_clk: mci1_clk { |
| 1101 | #clock-cells = <0>; |
| 1102 | reg = <22>; |
| 1103 | }; |
| 1104 | |
| 1105 | spi0_clk: spi0_clk { |
| 1106 | #clock-cells = <0>; |
| 1107 | reg = <24>; |
| 1108 | atmel,clk-output-range = <0 133000000>; |
| 1109 | }; |
| 1110 | |
| 1111 | spi1_clk: spi1_clk { |
| 1112 | #clock-cells = <0>; |
| 1113 | reg = <25>; |
| 1114 | atmel,clk-output-range = <0 133000000>; |
| 1115 | }; |
| 1116 | |
| 1117 | tcb0_clk: tcb0_clk { |
| 1118 | #clock-cells = <0>; |
| 1119 | reg = <26>; |
| 1120 | atmel,clk-output-range = <0 133000000>; |
| 1121 | }; |
| 1122 | |
| 1123 | pwm_clk: pwm_clk { |
| 1124 | #clock-cells = <0>; |
| 1125 | reg = <28>; |
| 1126 | }; |
| 1127 | |
| 1128 | adc_clk: adc_clk { |
| 1129 | #clock-cells = <0>; |
| 1130 | reg = <29>; |
| 1131 | atmel,clk-output-range = <0 66000000>; |
| 1132 | }; |
| 1133 | |
| 1134 | dma0_clk: dma0_clk { |
| 1135 | #clock-cells = <0>; |
| 1136 | reg = <30>; |
| 1137 | }; |
| 1138 | |
| 1139 | dma1_clk: dma1_clk { |
| 1140 | #clock-cells = <0>; |
| 1141 | reg = <31>; |
| 1142 | }; |
| 1143 | |
| 1144 | uhphs_clk: uhphs_clk { |
| 1145 | #clock-cells = <0>; |
| 1146 | reg = <32>; |
| 1147 | }; |
| 1148 | |
| 1149 | udphs_clk: udphs_clk { |
| 1150 | #clock-cells = <0>; |
| 1151 | reg = <33>; |
| 1152 | }; |
| 1153 | |
| 1154 | isi_clk: isi_clk { |
| 1155 | #clock-cells = <0>; |
| 1156 | reg = <37>; |
| 1157 | }; |
| 1158 | |
| 1159 | ssc0_clk: ssc0_clk { |
| 1160 | #clock-cells = <0>; |
| 1161 | reg = <38>; |
| 1162 | atmel,clk-output-range = <0 66000000>; |
| 1163 | }; |
| 1164 | |
| 1165 | ssc1_clk: ssc1_clk { |
| 1166 | #clock-cells = <0>; |
| 1167 | reg = <39>; |
| 1168 | atmel,clk-output-range = <0 66000000>; |
| 1169 | }; |
| 1170 | |
| 1171 | sha_clk: sha_clk { |
| 1172 | #clock-cells = <0>; |
| 1173 | reg = <42>; |
| 1174 | }; |
| 1175 | |
| 1176 | aes_clk: aes_clk { |
| 1177 | #clock-cells = <0>; |
| 1178 | reg = <43>; |
| 1179 | }; |
| 1180 | |
| 1181 | tdes_clk: tdes_clk { |
| 1182 | #clock-cells = <0>; |
| 1183 | reg = <44>; |
| 1184 | }; |
| 1185 | |
| 1186 | trng_clk: trng_clk { |
| 1187 | #clock-cells = <0>; |
| 1188 | reg = <45>; |
| 1189 | }; |
| 1190 | |
| 1191 | fuse_clk: fuse_clk { |
| 1192 | #clock-cells = <0>; |
| 1193 | reg = <48>; |
| 1194 | }; |
Alexandre Belloni | 063de89 | 2014-07-08 18:21:14 +0200 | [diff] [blame] | 1195 | |
| 1196 | mpddr_clk: mpddr_clk { |
| 1197 | #clock-cells = <0>; |
| 1198 | reg = <49>; |
| 1199 | }; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 1200 | }; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 1201 | }; |
| 1202 | |
| 1203 | rstc@fffffe00 { |
| 1204 | compatible = "atmel,at91sam9g45-rstc"; |
| 1205 | reg = <0xfffffe00 0x10>; |
| 1206 | }; |
| 1207 | |
Maxime Ripard | 16aa7f1f1 | 2014-07-03 14:08:47 +0200 | [diff] [blame] | 1208 | shutdown-controller@fffffe10 { |
| 1209 | compatible = "atmel,at91sam9x5-shdwc"; |
| 1210 | reg = <0xfffffe10 0x10>; |
| 1211 | }; |
| 1212 | |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 1213 | pit: timer@fffffe30 { |
| 1214 | compatible = "atmel,at91sam9260-pit"; |
| 1215 | reg = <0xfffffe30 0xf>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 1216 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 1217 | clocks = <&mck>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 1218 | }; |
| 1219 | |
| 1220 | watchdog@fffffe40 { |
| 1221 | compatible = "atmel,at91sam9260-wdt"; |
| 1222 | reg = <0xfffffe40 0x10>; |
Boris BREZILLON | fe46aa6 | 2013-10-04 09:24:14 +0200 | [diff] [blame] | 1223 | interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; |
| 1224 | atmel,watchdog-type = "hardware"; |
| 1225 | atmel,reset-type = "all"; |
| 1226 | atmel,dbg-halt; |
| 1227 | atmel,idle-halt; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 1228 | status = "disabled"; |
| 1229 | }; |
| 1230 | |
Boris BREZILLON | 4753219 | 2014-04-22 15:12:34 +0200 | [diff] [blame] | 1231 | sckc@fffffe50 { |
| 1232 | compatible = "atmel,at91sam9x5-sckc"; |
| 1233 | reg = <0xfffffe50 0x4>; |
| 1234 | |
| 1235 | slow_rc_osc: slow_rc_osc { |
| 1236 | compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; |
| 1237 | #clock-cells = <0>; |
| 1238 | clock-frequency = <32768>; |
| 1239 | clock-accuracy = <50000000>; |
| 1240 | atmel,startup-time-usec = <75>; |
| 1241 | }; |
| 1242 | |
| 1243 | slow_osc: slow_osc { |
| 1244 | compatible = "atmel,at91sam9x5-clk-slow-osc"; |
| 1245 | #clock-cells = <0>; |
| 1246 | clocks = <&slow_xtal>; |
| 1247 | atmel,startup-time-usec = <1200000>; |
| 1248 | }; |
| 1249 | |
| 1250 | clk32k: slowck { |
| 1251 | compatible = "atmel,at91sam9x5-clk-slow"; |
| 1252 | #clock-cells = <0>; |
| 1253 | clocks = <&slow_rc_osc &slow_osc>; |
| 1254 | }; |
| 1255 | }; |
| 1256 | |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 1257 | rtc@fffffeb0 { |
| 1258 | compatible = "atmel,at91rm9200-rtc"; |
| 1259 | reg = <0xfffffeb0 0x30>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 1260 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 1261 | }; |
| 1262 | }; |
| 1263 | |
| 1264 | usb0: gadget@00500000 { |
| 1265 | #address-cells = <1>; |
| 1266 | #size-cells = <0>; |
| 1267 | compatible = "atmel,at91sam9rl-udc"; |
| 1268 | reg = <0x00500000 0x100000 |
| 1269 | 0xf8030000 0x4000>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 1270 | interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 1271 | clocks = <&udphs_clk>, <&utmi>; |
| 1272 | clock-names = "pclk", "hclk"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 1273 | status = "disabled"; |
| 1274 | |
| 1275 | ep0 { |
| 1276 | reg = <0>; |
| 1277 | atmel,fifo-size = <64>; |
| 1278 | atmel,nb-banks = <1>; |
| 1279 | }; |
| 1280 | |
| 1281 | ep1 { |
| 1282 | reg = <1>; |
| 1283 | atmel,fifo-size = <1024>; |
| 1284 | atmel,nb-banks = <3>; |
| 1285 | atmel,can-dma; |
| 1286 | atmel,can-isoc; |
| 1287 | }; |
| 1288 | |
| 1289 | ep2 { |
| 1290 | reg = <2>; |
| 1291 | atmel,fifo-size = <1024>; |
| 1292 | atmel,nb-banks = <3>; |
| 1293 | atmel,can-dma; |
| 1294 | atmel,can-isoc; |
| 1295 | }; |
| 1296 | |
| 1297 | ep3 { |
| 1298 | reg = <3>; |
| 1299 | atmel,fifo-size = <1024>; |
| 1300 | atmel,nb-banks = <2>; |
| 1301 | atmel,can-dma; |
| 1302 | }; |
| 1303 | |
| 1304 | ep4 { |
| 1305 | reg = <4>; |
| 1306 | atmel,fifo-size = <1024>; |
| 1307 | atmel,nb-banks = <2>; |
| 1308 | atmel,can-dma; |
| 1309 | }; |
| 1310 | |
| 1311 | ep5 { |
| 1312 | reg = <5>; |
| 1313 | atmel,fifo-size = <1024>; |
| 1314 | atmel,nb-banks = <2>; |
| 1315 | atmel,can-dma; |
| 1316 | }; |
| 1317 | |
| 1318 | ep6 { |
| 1319 | reg = <6>; |
| 1320 | atmel,fifo-size = <1024>; |
| 1321 | atmel,nb-banks = <2>; |
| 1322 | atmel,can-dma; |
| 1323 | }; |
| 1324 | |
| 1325 | ep7 { |
| 1326 | reg = <7>; |
| 1327 | atmel,fifo-size = <1024>; |
| 1328 | atmel,nb-banks = <2>; |
| 1329 | atmel,can-dma; |
| 1330 | }; |
| 1331 | |
| 1332 | ep8 { |
| 1333 | reg = <8>; |
| 1334 | atmel,fifo-size = <1024>; |
| 1335 | atmel,nb-banks = <2>; |
| 1336 | }; |
| 1337 | |
| 1338 | ep9 { |
| 1339 | reg = <9>; |
| 1340 | atmel,fifo-size = <1024>; |
| 1341 | atmel,nb-banks = <2>; |
| 1342 | }; |
| 1343 | |
| 1344 | ep10 { |
| 1345 | reg = <10>; |
| 1346 | atmel,fifo-size = <1024>; |
| 1347 | atmel,nb-banks = <2>; |
| 1348 | }; |
| 1349 | |
| 1350 | ep11 { |
| 1351 | reg = <11>; |
| 1352 | atmel,fifo-size = <1024>; |
| 1353 | atmel,nb-banks = <2>; |
| 1354 | }; |
| 1355 | |
| 1356 | ep12 { |
| 1357 | reg = <12>; |
| 1358 | atmel,fifo-size = <1024>; |
| 1359 | atmel,nb-banks = <2>; |
| 1360 | }; |
| 1361 | |
| 1362 | ep13 { |
| 1363 | reg = <13>; |
| 1364 | atmel,fifo-size = <1024>; |
| 1365 | atmel,nb-banks = <2>; |
| 1366 | }; |
| 1367 | |
| 1368 | ep14 { |
| 1369 | reg = <14>; |
| 1370 | atmel,fifo-size = <1024>; |
| 1371 | atmel,nb-banks = <2>; |
| 1372 | }; |
| 1373 | |
| 1374 | ep15 { |
| 1375 | reg = <15>; |
| 1376 | atmel,fifo-size = <1024>; |
| 1377 | atmel,nb-banks = <2>; |
| 1378 | }; |
| 1379 | }; |
| 1380 | |
| 1381 | usb1: ohci@00600000 { |
| 1382 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 1383 | reg = <0x00600000 0x100000>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 1384 | interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; |
Boris BREZILLON | 5f87751 | 2014-01-16 16:25:34 +0100 | [diff] [blame] | 1385 | clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 1386 | <&uhpck>; |
| 1387 | clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 1388 | status = "disabled"; |
| 1389 | }; |
| 1390 | |
| 1391 | usb2: ehci@00700000 { |
| 1392 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; |
| 1393 | reg = <0x00700000 0x100000>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 1394 | interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 1395 | clocks = <&usb>, <&uhphs_clk>, <&uhpck>; |
| 1396 | clock-names = "usb_clk", "ehci_clk", "uhpck"; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 1397 | status = "disabled"; |
| 1398 | }; |
| 1399 | |
| 1400 | nand0: nand@60000000 { |
| 1401 | compatible = "atmel,at91rm9200-nand"; |
| 1402 | #address-cells = <1>; |
| 1403 | #size-cells = <1>; |
Josh Wu | 8ae599e | 2013-06-05 19:17:31 +0800 | [diff] [blame] | 1404 | ranges; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 1405 | reg = < 0x60000000 0x01000000 /* EBI CS3 */ |
| 1406 | 0xffffc070 0x00000490 /* SMC PMECC regs */ |
| 1407 | 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */ |
Josh Wu | afa6a2a | 2013-08-23 14:27:41 +0800 | [diff] [blame] | 1408 | 0x00110000 0x00018000 /* ROM code */ |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 1409 | >; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 1410 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 1411 | atmel,nand-addr-offset = <21>; |
| 1412 | atmel,nand-cmd-offset = <22>; |
Nicolas Ferre | e8b2da6 | 2013-07-01 17:05:18 +0200 | [diff] [blame] | 1413 | atmel,nand-has-dma; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 1414 | pinctrl-names = "default"; |
| 1415 | pinctrl-0 = <&pinctrl_nand0_ale_cle>; |
Josh Wu | afa6a2a | 2013-08-23 14:27:41 +0800 | [diff] [blame] | 1416 | atmel,pmecc-lookup-table-offset = <0x0 0x8000>; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 1417 | status = "disabled"; |
Josh Wu | 8ae599e | 2013-06-05 19:17:31 +0800 | [diff] [blame] | 1418 | |
| 1419 | nfc@70000000 { |
| 1420 | compatible = "atmel,sama5d3-nfc"; |
| 1421 | #address-cells = <1>; |
| 1422 | #size-cells = <1>; |
| 1423 | reg = < |
| 1424 | 0x70000000 0x10000000 /* NFC Command Registers */ |
| 1425 | 0xffffc000 0x00000070 /* NFC HSMC regs */ |
| 1426 | 0x00200000 0x00100000 /* NFC SRAM banks */ |
| 1427 | >; |
Alexandre Belloni | 8a85ba2 | 2014-09-16 10:43:57 +0200 | [diff] [blame] | 1428 | clocks = <&hsmc_clk>; |
Josh Wu | 8ae599e | 2013-06-05 19:17:31 +0800 | [diff] [blame] | 1429 | }; |
Ludovic Desroches | 655ff266 | 2013-03-22 13:24:13 +0000 | [diff] [blame] | 1430 | }; |
| 1431 | }; |
| 1432 | }; |