blob: e66d6cf03adc7baeffdd6130a2ed99e32297fe6c [file] [log] [blame]
Ben Hutchings8ceee662008-04-27 12:55:59 +01001/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/bitops.h>
12#include <linux/delay.h>
13#include <linux/pci.h>
14#include <linux/module.h>
15#include <linux/seq_file.h>
Ben Hutchings37b5a602008-05-30 22:27:04 +010016#include <linux/i2c.h>
17#include <linux/i2c-algo-bit.h>
Ben Hutchings8ceee662008-04-27 12:55:59 +010018#include "net_driver.h"
19#include "bitfield.h"
20#include "efx.h"
21#include "mac.h"
22#include "gmii.h"
23#include "spi.h"
24#include "falcon.h"
25#include "falcon_hwdefs.h"
26#include "falcon_io.h"
27#include "mdio_10g.h"
28#include "phy.h"
29#include "boards.h"
30#include "workarounds.h"
31
32/* Falcon hardware control.
33 * Falcon is the internal codename for the SFC4000 controller that is
34 * present in SFE400X evaluation boards
35 */
36
37/**
38 * struct falcon_nic_data - Falcon NIC state
39 * @next_buffer_table: First available buffer table id
40 * @pci_dev2: The secondary PCI device if present
Ben Hutchings37b5a602008-05-30 22:27:04 +010041 * @i2c_data: Operations and state for I2C bit-bashing algorithm
Ben Hutchings8ceee662008-04-27 12:55:59 +010042 */
43struct falcon_nic_data {
44 unsigned next_buffer_table;
45 struct pci_dev *pci_dev2;
Ben Hutchings37b5a602008-05-30 22:27:04 +010046 struct i2c_algo_bit_data i2c_data;
Ben Hutchings8ceee662008-04-27 12:55:59 +010047};
48
49/**************************************************************************
50 *
51 * Configurable values
52 *
53 **************************************************************************
54 */
55
56static int disable_dma_stats;
57
58/* This is set to 16 for a good reason. In summary, if larger than
59 * 16, the descriptor cache holds more than a default socket
60 * buffer's worth of packets (for UDP we can only have at most one
61 * socket buffer's worth outstanding). This combined with the fact
62 * that we only get 1 TX event per descriptor cache means the NIC
63 * goes idle.
64 */
65#define TX_DC_ENTRIES 16
66#define TX_DC_ENTRIES_ORDER 0
67#define TX_DC_BASE 0x130000
68
69#define RX_DC_ENTRIES 64
70#define RX_DC_ENTRIES_ORDER 2
71#define RX_DC_BASE 0x100000
72
73/* RX FIFO XOFF watermark
74 *
75 * When the amount of the RX FIFO increases used increases past this
76 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
77 * This also has an effect on RX/TX arbitration
78 */
79static int rx_xoff_thresh_bytes = -1;
80module_param(rx_xoff_thresh_bytes, int, 0644);
81MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
82
83/* RX FIFO XON watermark
84 *
85 * When the amount of the RX FIFO used decreases below this
86 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
87 * This also has an effect on RX/TX arbitration
88 */
89static int rx_xon_thresh_bytes = -1;
90module_param(rx_xon_thresh_bytes, int, 0644);
91MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
92
93/* TX descriptor ring size - min 512 max 4k */
94#define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K
95#define FALCON_TXD_RING_SIZE 1024
96#define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
97
98/* RX descriptor ring size - min 512 max 4k */
99#define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K
100#define FALCON_RXD_RING_SIZE 1024
101#define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
102
103/* Event queue size - max 32k */
104#define FALCON_EVQ_ORDER EVQ_SIZE_4K
105#define FALCON_EVQ_SIZE 4096
106#define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
107
108/* Max number of internal errors. After this resets will not be performed */
109#define FALCON_MAX_INT_ERRORS 4
110
111/* Maximum period that we wait for flush events. If the flush event
112 * doesn't arrive in this period of time then we check if the queue
113 * was disabled anyway. */
114#define FALCON_FLUSH_TIMEOUT 10 /* 10ms */
115
116/**************************************************************************
117 *
118 * Falcon constants
119 *
120 **************************************************************************
121 */
122
Ben Hutchings9bbd7d92008-05-16 21:18:48 +0100123/* DMA address mask */
124#define FALCON_DMA_MASK DMA_BIT_MASK(46)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100125
126/* TX DMA length mask (13-bit) */
127#define FALCON_TX_DMA_MASK (4096 - 1)
128
129/* Size and alignment of special buffers (4KB) */
130#define FALCON_BUF_SIZE 4096
131
132/* Dummy SRAM size code */
133#define SRM_NB_BSZ_ONCHIP_ONLY (-1)
134
135/* Be nice if these (or equiv.) were in linux/pci_regs.h, but they're not. */
136#define PCI_EXP_DEVCAP_PWR_VAL_LBN 18
137#define PCI_EXP_DEVCAP_PWR_SCL_LBN 26
138#define PCI_EXP_DEVCTL_PAYLOAD_LBN 5
139#define PCI_EXP_LNKSTA_LNK_WID 0x3f0
140#define PCI_EXP_LNKSTA_LNK_WID_LBN 4
141
142#define FALCON_IS_DUAL_FUNC(efx) \
Ben Hutchings55668612008-05-16 21:16:10 +0100143 (falcon_rev(efx) < FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100144
145/**************************************************************************
146 *
147 * Falcon hardware access
148 *
149 **************************************************************************/
150
151/* Read the current event from the event queue */
152static inline efx_qword_t *falcon_event(struct efx_channel *channel,
153 unsigned int index)
154{
155 return (((efx_qword_t *) (channel->eventq.addr)) + index);
156}
157
158/* See if an event is present
159 *
160 * We check both the high and low dword of the event for all ones. We
161 * wrote all ones when we cleared the event, and no valid event can
162 * have all ones in either its high or low dwords. This approach is
163 * robust against reordering.
164 *
165 * Note that using a single 64-bit comparison is incorrect; even
166 * though the CPU read will be atomic, the DMA write may not be.
167 */
168static inline int falcon_event_present(efx_qword_t *event)
169{
170 return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
171 EFX_DWORD_IS_ALL_ONES(event->dword[1])));
172}
173
174/**************************************************************************
175 *
176 * I2C bus - this is a bit-bashing interface using GPIO pins
177 * Note that it uses the output enables to tristate the outputs
178 * SDA is the data pin and SCL is the clock
179 *
180 **************************************************************************
181 */
Ben Hutchings37b5a602008-05-30 22:27:04 +0100182static void falcon_setsda(void *data, int state)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100183{
Ben Hutchings37b5a602008-05-30 22:27:04 +0100184 struct efx_nic *efx = (struct efx_nic *)data;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100185 efx_oword_t reg;
186
Ben Hutchings37b5a602008-05-30 22:27:04 +0100187 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
188 EFX_SET_OWORD_FIELD(reg, GPIO3_OEN, !state);
189 falcon_write(efx, &reg, GPIO_CTL_REG_KER);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100190}
191
Ben Hutchings37b5a602008-05-30 22:27:04 +0100192static void falcon_setscl(void *data, int state)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100193{
Ben Hutchings37b5a602008-05-30 22:27:04 +0100194 struct efx_nic *efx = (struct efx_nic *)data;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100195 efx_oword_t reg;
196
Ben Hutchings37b5a602008-05-30 22:27:04 +0100197 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
198 EFX_SET_OWORD_FIELD(reg, GPIO0_OEN, !state);
199 falcon_write(efx, &reg, GPIO_CTL_REG_KER);
200}
201
202static int falcon_getsda(void *data)
203{
204 struct efx_nic *efx = (struct efx_nic *)data;
205 efx_oword_t reg;
206
207 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100208 return EFX_OWORD_FIELD(reg, GPIO3_IN);
209}
210
Ben Hutchings37b5a602008-05-30 22:27:04 +0100211static int falcon_getscl(void *data)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100212{
Ben Hutchings37b5a602008-05-30 22:27:04 +0100213 struct efx_nic *efx = (struct efx_nic *)data;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100214 efx_oword_t reg;
215
Ben Hutchings37b5a602008-05-30 22:27:04 +0100216 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
217 return EFX_OWORD_FIELD(reg, GPIO0_IN);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100218}
219
Ben Hutchings37b5a602008-05-30 22:27:04 +0100220static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
221 .setsda = falcon_setsda,
222 .setscl = falcon_setscl,
Ben Hutchings8ceee662008-04-27 12:55:59 +0100223 .getsda = falcon_getsda,
224 .getscl = falcon_getscl,
Ben Hutchings62c78322008-05-30 22:27:46 +0100225 .udelay = 5,
Ben Hutchings9dadae62008-07-18 18:59:12 +0100226 /* Wait up to 50 ms for slave to let us pull SCL high */
227 .timeout = DIV_ROUND_UP(HZ, 20),
Ben Hutchings8ceee662008-04-27 12:55:59 +0100228};
229
230/**************************************************************************
231 *
232 * Falcon special buffer handling
233 * Special buffers are used for event queues and the TX and RX
234 * descriptor rings.
235 *
236 *************************************************************************/
237
238/*
239 * Initialise a Falcon special buffer
240 *
241 * This will define a buffer (previously allocated via
242 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
243 * it to be used for event queues, descriptor rings etc.
244 */
Ben Hutchingsbc3c90a2008-09-01 12:48:46 +0100245static void
Ben Hutchings8ceee662008-04-27 12:55:59 +0100246falcon_init_special_buffer(struct efx_nic *efx,
247 struct efx_special_buffer *buffer)
248{
249 efx_qword_t buf_desc;
250 int index;
251 dma_addr_t dma_addr;
252 int i;
253
254 EFX_BUG_ON_PARANOID(!buffer->addr);
255
256 /* Write buffer descriptors to NIC */
257 for (i = 0; i < buffer->entries; i++) {
258 index = buffer->index + i;
259 dma_addr = buffer->dma_addr + (i * 4096);
260 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
261 index, (unsigned long long)dma_addr);
262 EFX_POPULATE_QWORD_4(buf_desc,
263 IP_DAT_BUF_SIZE, IP_DAT_BUF_SIZE_4K,
264 BUF_ADR_REGION, 0,
265 BUF_ADR_FBUF, (dma_addr >> 12),
266 BUF_OWNER_ID_FBUF, 0);
267 falcon_write_sram(efx, &buf_desc, index);
268 }
Ben Hutchings8ceee662008-04-27 12:55:59 +0100269}
270
271/* Unmaps a buffer from Falcon and clears the buffer table entries */
272static void
273falcon_fini_special_buffer(struct efx_nic *efx,
274 struct efx_special_buffer *buffer)
275{
276 efx_oword_t buf_tbl_upd;
277 unsigned int start = buffer->index;
278 unsigned int end = (buffer->index + buffer->entries - 1);
279
280 if (!buffer->entries)
281 return;
282
283 EFX_LOG(efx, "unmapping special buffers %d-%d\n",
284 buffer->index, buffer->index + buffer->entries - 1);
285
286 EFX_POPULATE_OWORD_4(buf_tbl_upd,
287 BUF_UPD_CMD, 0,
288 BUF_CLR_CMD, 1,
289 BUF_CLR_END_ID, end,
290 BUF_CLR_START_ID, start);
291 falcon_write(efx, &buf_tbl_upd, BUF_TBL_UPD_REG_KER);
292}
293
294/*
295 * Allocate a new Falcon special buffer
296 *
297 * This allocates memory for a new buffer, clears it and allocates a
298 * new buffer ID range. It does not write into Falcon's buffer table.
299 *
300 * This call will allocate 4KB buffers, since Falcon can't use 8KB
301 * buffers for event queues and descriptor rings.
302 */
303static int falcon_alloc_special_buffer(struct efx_nic *efx,
304 struct efx_special_buffer *buffer,
305 unsigned int len)
306{
307 struct falcon_nic_data *nic_data = efx->nic_data;
308
309 len = ALIGN(len, FALCON_BUF_SIZE);
310
311 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
312 &buffer->dma_addr);
313 if (!buffer->addr)
314 return -ENOMEM;
315 buffer->len = len;
316 buffer->entries = len / FALCON_BUF_SIZE;
317 BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
318
319 /* All zeros is a potentially valid event so memset to 0xff */
320 memset(buffer->addr, 0xff, len);
321
322 /* Select new buffer ID */
323 buffer->index = nic_data->next_buffer_table;
324 nic_data->next_buffer_table += buffer->entries;
325
326 EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
327 "(virt %p phys %lx)\n", buffer->index,
328 buffer->index + buffer->entries - 1,
329 (unsigned long long)buffer->dma_addr, len,
330 buffer->addr, virt_to_phys(buffer->addr));
331
332 return 0;
333}
334
335static void falcon_free_special_buffer(struct efx_nic *efx,
336 struct efx_special_buffer *buffer)
337{
338 if (!buffer->addr)
339 return;
340
341 EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
342 "(virt %p phys %lx)\n", buffer->index,
343 buffer->index + buffer->entries - 1,
344 (unsigned long long)buffer->dma_addr, buffer->len,
345 buffer->addr, virt_to_phys(buffer->addr));
346
347 pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
348 buffer->dma_addr);
349 buffer->addr = NULL;
350 buffer->entries = 0;
351}
352
353/**************************************************************************
354 *
355 * Falcon generic buffer handling
356 * These buffers are used for interrupt status and MAC stats
357 *
358 **************************************************************************/
359
360static int falcon_alloc_buffer(struct efx_nic *efx,
361 struct efx_buffer *buffer, unsigned int len)
362{
363 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
364 &buffer->dma_addr);
365 if (!buffer->addr)
366 return -ENOMEM;
367 buffer->len = len;
368 memset(buffer->addr, 0, len);
369 return 0;
370}
371
372static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
373{
374 if (buffer->addr) {
375 pci_free_consistent(efx->pci_dev, buffer->len,
376 buffer->addr, buffer->dma_addr);
377 buffer->addr = NULL;
378 }
379}
380
381/**************************************************************************
382 *
383 * Falcon TX path
384 *
385 **************************************************************************/
386
387/* Returns a pointer to the specified transmit descriptor in the TX
388 * descriptor queue belonging to the specified channel.
389 */
390static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
391 unsigned int index)
392{
393 return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
394}
395
396/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
397static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
398{
399 unsigned write_ptr;
400 efx_dword_t reg;
401
402 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
403 EFX_POPULATE_DWORD_1(reg, TX_DESC_WPTR_DWORD, write_ptr);
404 falcon_writel_page(tx_queue->efx, &reg,
405 TX_DESC_UPD_REG_KER_DWORD, tx_queue->queue);
406}
407
408
409/* For each entry inserted into the software descriptor ring, create a
410 * descriptor in the hardware TX descriptor ring (in host memory), and
411 * write a doorbell.
412 */
413void falcon_push_buffers(struct efx_tx_queue *tx_queue)
414{
415
416 struct efx_tx_buffer *buffer;
417 efx_qword_t *txd;
418 unsigned write_ptr;
419
420 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
421
422 do {
423 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
424 buffer = &tx_queue->buffer[write_ptr];
425 txd = falcon_tx_desc(tx_queue, write_ptr);
426 ++tx_queue->write_count;
427
428 /* Create TX descriptor ring entry */
429 EFX_POPULATE_QWORD_5(*txd,
430 TX_KER_PORT, 0,
431 TX_KER_CONT, buffer->continuation,
432 TX_KER_BYTE_CNT, buffer->len,
433 TX_KER_BUF_REGION, 0,
434 TX_KER_BUF_ADR, buffer->dma_addr);
435 } while (tx_queue->write_count != tx_queue->insert_count);
436
437 wmb(); /* Ensure descriptors are written before they are fetched */
438 falcon_notify_tx_desc(tx_queue);
439}
440
441/* Allocate hardware resources for a TX queue */
442int falcon_probe_tx(struct efx_tx_queue *tx_queue)
443{
444 struct efx_nic *efx = tx_queue->efx;
445 return falcon_alloc_special_buffer(efx, &tx_queue->txd,
446 FALCON_TXD_RING_SIZE *
447 sizeof(efx_qword_t));
448}
449
Ben Hutchingsbc3c90a2008-09-01 12:48:46 +0100450void falcon_init_tx(struct efx_tx_queue *tx_queue)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100451{
452 efx_oword_t tx_desc_ptr;
453 struct efx_nic *efx = tx_queue->efx;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100454
455 /* Pin TX descriptor ring */
Ben Hutchingsbc3c90a2008-09-01 12:48:46 +0100456 falcon_init_special_buffer(efx, &tx_queue->txd);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100457
458 /* Push TX descriptor ring to card */
459 EFX_POPULATE_OWORD_10(tx_desc_ptr,
460 TX_DESCQ_EN, 1,
461 TX_ISCSI_DDIG_EN, 0,
462 TX_ISCSI_HDIG_EN, 0,
463 TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
Ben Hutchingsd3074022008-09-01 12:48:03 +0100464 TX_DESCQ_EVQ_ID, tx_queue->channel->channel,
Ben Hutchings8ceee662008-04-27 12:55:59 +0100465 TX_DESCQ_OWNER_ID, 0,
466 TX_DESCQ_LABEL, tx_queue->queue,
467 TX_DESCQ_SIZE, FALCON_TXD_RING_ORDER,
468 TX_DESCQ_TYPE, 0,
469 TX_NON_IP_DROP_DIS_B0, 1);
470
Ben Hutchings55668612008-05-16 21:16:10 +0100471 if (falcon_rev(efx) >= FALCON_REV_B0) {
Ben Hutchings60ac1062008-09-01 12:44:59 +0100472 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
473 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_IP_CHKSM_DIS_B0, !csum);
474 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_TCP_CHKSM_DIS_B0, !csum);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100475 }
476
477 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
478 tx_queue->queue);
479
Ben Hutchings55668612008-05-16 21:16:10 +0100480 if (falcon_rev(efx) < FALCON_REV_B0) {
Ben Hutchings8ceee662008-04-27 12:55:59 +0100481 efx_oword_t reg;
482
Ben Hutchings60ac1062008-09-01 12:44:59 +0100483 /* Only 128 bits in this register */
484 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100485
486 falcon_read(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
Ben Hutchings60ac1062008-09-01 12:44:59 +0100487 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100488 clear_bit_le(tx_queue->queue, (void *)&reg);
489 else
490 set_bit_le(tx_queue->queue, (void *)&reg);
491 falcon_write(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
492 }
Ben Hutchings8ceee662008-04-27 12:55:59 +0100493}
494
495static int falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
496{
497 struct efx_nic *efx = tx_queue->efx;
498 struct efx_channel *channel = &efx->channel[0];
499 efx_oword_t tx_flush_descq;
500 unsigned int read_ptr, i;
501
502 /* Post a flush command */
503 EFX_POPULATE_OWORD_2(tx_flush_descq,
504 TX_FLUSH_DESCQ_CMD, 1,
505 TX_FLUSH_DESCQ, tx_queue->queue);
506 falcon_write(efx, &tx_flush_descq, TX_FLUSH_DESCQ_REG_KER);
507 msleep(FALCON_FLUSH_TIMEOUT);
508
509 if (EFX_WORKAROUND_7803(efx))
510 return 0;
511
512 /* Look for a flush completed event */
513 read_ptr = channel->eventq_read_ptr;
514 for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
515 efx_qword_t *event = falcon_event(channel, read_ptr);
516 int ev_code, ev_sub_code, ev_queue;
517 if (!falcon_event_present(event))
518 break;
519
520 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
521 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
522 ev_queue = EFX_QWORD_FIELD(*event, DRIVER_EV_TX_DESCQ_ID);
523 if ((ev_sub_code == TX_DESCQ_FLS_DONE_EV_DECODE) &&
524 (ev_queue == tx_queue->queue)) {
525 EFX_LOG(efx, "tx queue %d flush command succesful\n",
526 tx_queue->queue);
527 return 0;
528 }
529
530 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
531 }
532
533 if (EFX_WORKAROUND_11557(efx)) {
534 efx_oword_t reg;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100535 bool enabled;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100536
537 falcon_read_table(efx, &reg, efx->type->txd_ptr_tbl_base,
538 tx_queue->queue);
539 enabled = EFX_OWORD_FIELD(reg, TX_DESCQ_EN);
540 if (!enabled) {
541 EFX_LOG(efx, "tx queue %d disabled without a "
542 "flush event seen\n", tx_queue->queue);
543 return 0;
544 }
545 }
546
547 EFX_ERR(efx, "tx queue %d flush command timed out\n", tx_queue->queue);
548 return -ETIMEDOUT;
549}
550
551void falcon_fini_tx(struct efx_tx_queue *tx_queue)
552{
553 struct efx_nic *efx = tx_queue->efx;
554 efx_oword_t tx_desc_ptr;
555
556 /* Stop the hardware using the queue */
557 if (falcon_flush_tx_queue(tx_queue))
558 EFX_ERR(efx, "failed to flush tx queue %d\n", tx_queue->queue);
559
560 /* Remove TX descriptor ring from card */
561 EFX_ZERO_OWORD(tx_desc_ptr);
562 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
563 tx_queue->queue);
564
565 /* Unpin TX descriptor ring */
566 falcon_fini_special_buffer(efx, &tx_queue->txd);
567}
568
569/* Free buffers backing TX queue */
570void falcon_remove_tx(struct efx_tx_queue *tx_queue)
571{
572 falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
573}
574
575/**************************************************************************
576 *
577 * Falcon RX path
578 *
579 **************************************************************************/
580
581/* Returns a pointer to the specified descriptor in the RX descriptor queue */
582static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
583 unsigned int index)
584{
585 return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
586}
587
588/* This creates an entry in the RX descriptor queue */
589static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
590 unsigned index)
591{
592 struct efx_rx_buffer *rx_buf;
593 efx_qword_t *rxd;
594
595 rxd = falcon_rx_desc(rx_queue, index);
596 rx_buf = efx_rx_buffer(rx_queue, index);
597 EFX_POPULATE_QWORD_3(*rxd,
598 RX_KER_BUF_SIZE,
599 rx_buf->len -
600 rx_queue->efx->type->rx_buffer_padding,
601 RX_KER_BUF_REGION, 0,
602 RX_KER_BUF_ADR, rx_buf->dma_addr);
603}
604
605/* This writes to the RX_DESC_WPTR register for the specified receive
606 * descriptor ring.
607 */
608void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
609{
610 efx_dword_t reg;
611 unsigned write_ptr;
612
613 while (rx_queue->notified_count != rx_queue->added_count) {
614 falcon_build_rx_desc(rx_queue,
615 rx_queue->notified_count &
616 FALCON_RXD_RING_MASK);
617 ++rx_queue->notified_count;
618 }
619
620 wmb();
621 write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK;
622 EFX_POPULATE_DWORD_1(reg, RX_DESC_WPTR_DWORD, write_ptr);
623 falcon_writel_page(rx_queue->efx, &reg,
624 RX_DESC_UPD_REG_KER_DWORD, rx_queue->queue);
625}
626
627int falcon_probe_rx(struct efx_rx_queue *rx_queue)
628{
629 struct efx_nic *efx = rx_queue->efx;
630 return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
631 FALCON_RXD_RING_SIZE *
632 sizeof(efx_qword_t));
633}
634
Ben Hutchingsbc3c90a2008-09-01 12:48:46 +0100635void falcon_init_rx(struct efx_rx_queue *rx_queue)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100636{
637 efx_oword_t rx_desc_ptr;
638 struct efx_nic *efx = rx_queue->efx;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100639 bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
640 bool iscsi_digest_en = is_b0;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100641
642 EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
643 rx_queue->queue, rx_queue->rxd.index,
644 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
645
646 /* Pin RX descriptor ring */
Ben Hutchingsbc3c90a2008-09-01 12:48:46 +0100647 falcon_init_special_buffer(efx, &rx_queue->rxd);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100648
649 /* Push RX descriptor ring to card */
650 EFX_POPULATE_OWORD_10(rx_desc_ptr,
651 RX_ISCSI_DDIG_EN, iscsi_digest_en,
652 RX_ISCSI_HDIG_EN, iscsi_digest_en,
653 RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
Ben Hutchingsd3074022008-09-01 12:48:03 +0100654 RX_DESCQ_EVQ_ID, rx_queue->channel->channel,
Ben Hutchings8ceee662008-04-27 12:55:59 +0100655 RX_DESCQ_OWNER_ID, 0,
656 RX_DESCQ_LABEL, rx_queue->queue,
657 RX_DESCQ_SIZE, FALCON_RXD_RING_ORDER,
658 RX_DESCQ_TYPE, 0 /* kernel queue */ ,
659 /* For >=B0 this is scatter so disable */
660 RX_DESCQ_JUMBO, !is_b0,
661 RX_DESCQ_EN, 1);
662 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
663 rx_queue->queue);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100664}
665
666static int falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
667{
668 struct efx_nic *efx = rx_queue->efx;
669 struct efx_channel *channel = &efx->channel[0];
670 unsigned int read_ptr, i;
671 efx_oword_t rx_flush_descq;
672
673 /* Post a flush command */
674 EFX_POPULATE_OWORD_2(rx_flush_descq,
675 RX_FLUSH_DESCQ_CMD, 1,
676 RX_FLUSH_DESCQ, rx_queue->queue);
677 falcon_write(efx, &rx_flush_descq, RX_FLUSH_DESCQ_REG_KER);
678 msleep(FALCON_FLUSH_TIMEOUT);
679
680 if (EFX_WORKAROUND_7803(efx))
681 return 0;
682
683 /* Look for a flush completed event */
684 read_ptr = channel->eventq_read_ptr;
685 for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
686 efx_qword_t *event = falcon_event(channel, read_ptr);
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100687 int ev_code, ev_sub_code, ev_queue;
688 bool ev_failed;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100689 if (!falcon_event_present(event))
690 break;
691
692 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
693 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
694 ev_queue = EFX_QWORD_FIELD(*event, DRIVER_EV_RX_DESCQ_ID);
695 ev_failed = EFX_QWORD_FIELD(*event, DRIVER_EV_RX_FLUSH_FAIL);
696
697 if ((ev_sub_code == RX_DESCQ_FLS_DONE_EV_DECODE) &&
698 (ev_queue == rx_queue->queue)) {
699 if (ev_failed) {
700 EFX_INFO(efx, "rx queue %d flush command "
701 "failed\n", rx_queue->queue);
702 return -EAGAIN;
703 } else {
704 EFX_LOG(efx, "rx queue %d flush command "
705 "succesful\n", rx_queue->queue);
706 return 0;
707 }
708 }
709
710 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
711 }
712
713 if (EFX_WORKAROUND_11557(efx)) {
714 efx_oword_t reg;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100715 bool enabled;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100716
717 falcon_read_table(efx, &reg, efx->type->rxd_ptr_tbl_base,
718 rx_queue->queue);
719 enabled = EFX_OWORD_FIELD(reg, RX_DESCQ_EN);
720 if (!enabled) {
721 EFX_LOG(efx, "rx queue %d disabled without a "
722 "flush event seen\n", rx_queue->queue);
723 return 0;
724 }
725 }
726
727 EFX_ERR(efx, "rx queue %d flush command timed out\n", rx_queue->queue);
728 return -ETIMEDOUT;
729}
730
731void falcon_fini_rx(struct efx_rx_queue *rx_queue)
732{
733 efx_oword_t rx_desc_ptr;
734 struct efx_nic *efx = rx_queue->efx;
735 int i, rc;
736
737 /* Try and flush the rx queue. This may need to be repeated */
738 for (i = 0; i < 5; i++) {
739 rc = falcon_flush_rx_queue(rx_queue);
740 if (rc == -EAGAIN)
741 continue;
742 break;
743 }
Steve Hodgson23bdfdd2008-06-09 19:34:32 +0100744 if (rc) {
Ben Hutchings8ceee662008-04-27 12:55:59 +0100745 EFX_ERR(efx, "failed to flush rx queue %d\n", rx_queue->queue);
Steve Hodgson23bdfdd2008-06-09 19:34:32 +0100746 efx_schedule_reset(efx, RESET_TYPE_INVISIBLE);
747 }
Ben Hutchings8ceee662008-04-27 12:55:59 +0100748
749 /* Remove RX descriptor ring from card */
750 EFX_ZERO_OWORD(rx_desc_ptr);
751 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
752 rx_queue->queue);
753
754 /* Unpin RX descriptor ring */
755 falcon_fini_special_buffer(efx, &rx_queue->rxd);
756}
757
758/* Free buffers backing RX queue */
759void falcon_remove_rx(struct efx_rx_queue *rx_queue)
760{
761 falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
762}
763
764/**************************************************************************
765 *
766 * Falcon event queue processing
767 * Event queues are processed by per-channel tasklets.
768 *
769 **************************************************************************/
770
771/* Update a channel's event queue's read pointer (RPTR) register
772 *
773 * This writes the EVQ_RPTR_REG register for the specified channel's
774 * event queue.
775 *
776 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
777 * whereas channel->eventq_read_ptr contains the index of the "next to
778 * read" event.
779 */
780void falcon_eventq_read_ack(struct efx_channel *channel)
781{
782 efx_dword_t reg;
783 struct efx_nic *efx = channel->efx;
784
785 EFX_POPULATE_DWORD_1(reg, EVQ_RPTR_DWORD, channel->eventq_read_ptr);
786 falcon_writel_table(efx, &reg, efx->type->evq_rptr_tbl_base,
Ben Hutchingsd3074022008-09-01 12:48:03 +0100787 channel->channel);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100788}
789
790/* Use HW to insert a SW defined event */
791void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
792{
793 efx_oword_t drv_ev_reg;
794
795 EFX_POPULATE_OWORD_2(drv_ev_reg,
Ben Hutchingsd3074022008-09-01 12:48:03 +0100796 DRV_EV_QID, channel->channel,
Ben Hutchings8ceee662008-04-27 12:55:59 +0100797 DRV_EV_DATA,
798 EFX_QWORD_FIELD64(*event, WHOLE_EVENT));
799 falcon_write(channel->efx, &drv_ev_reg, DRV_EV_REG_KER);
800}
801
802/* Handle a transmit completion event
803 *
804 * Falcon batches TX completion events; the message we receive is of
805 * the form "complete all TX events up to this index".
806 */
Ben Hutchings4d566062008-09-01 12:47:12 +0100807static void falcon_handle_tx_event(struct efx_channel *channel,
808 efx_qword_t *event)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100809{
810 unsigned int tx_ev_desc_ptr;
811 unsigned int tx_ev_q_label;
812 struct efx_tx_queue *tx_queue;
813 struct efx_nic *efx = channel->efx;
814
815 if (likely(EFX_QWORD_FIELD(*event, TX_EV_COMP))) {
816 /* Transmit completion */
817 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, TX_EV_DESC_PTR);
818 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
819 tx_queue = &efx->tx_queue[tx_ev_q_label];
820 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
821 } else if (EFX_QWORD_FIELD(*event, TX_EV_WQ_FF_FULL)) {
822 /* Rewrite the FIFO write pointer */
823 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
824 tx_queue = &efx->tx_queue[tx_ev_q_label];
825
Ben Hutchings55668612008-05-16 21:16:10 +0100826 if (efx_dev_registered(efx))
Ben Hutchings8ceee662008-04-27 12:55:59 +0100827 netif_tx_lock(efx->net_dev);
828 falcon_notify_tx_desc(tx_queue);
Ben Hutchings55668612008-05-16 21:16:10 +0100829 if (efx_dev_registered(efx))
Ben Hutchings8ceee662008-04-27 12:55:59 +0100830 netif_tx_unlock(efx->net_dev);
831 } else if (EFX_QWORD_FIELD(*event, TX_EV_PKT_ERR) &&
832 EFX_WORKAROUND_10727(efx)) {
833 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
834 } else {
835 EFX_ERR(efx, "channel %d unexpected TX event "
836 EFX_QWORD_FMT"\n", channel->channel,
837 EFX_QWORD_VAL(*event));
838 }
839}
840
Ben Hutchings8ceee662008-04-27 12:55:59 +0100841/* Detect errors included in the rx_evt_pkt_ok bit. */
842static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
843 const efx_qword_t *event,
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100844 bool *rx_ev_pkt_ok,
845 bool *discard)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100846{
847 struct efx_nic *efx = rx_queue->efx;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100848 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
849 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
850 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
851 bool rx_ev_other_err, rx_ev_pause_frm;
852 bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
853 unsigned rx_ev_pkt_type;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100854
855 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
856 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
857 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, RX_EV_TOBE_DISC);
858 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, RX_EV_PKT_TYPE);
859 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
860 RX_EV_BUF_OWNER_ID_ERR);
861 rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, RX_EV_IF_FRAG_ERR);
862 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
863 RX_EV_IP_HDR_CHKSUM_ERR);
864 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
865 RX_EV_TCP_UDP_CHKSUM_ERR);
866 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, RX_EV_ETH_CRC_ERR);
867 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, RX_EV_FRM_TRUNC);
Ben Hutchings55668612008-05-16 21:16:10 +0100868 rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
Ben Hutchings8ceee662008-04-27 12:55:59 +0100869 0 : EFX_QWORD_FIELD(*event, RX_EV_DRIB_NIB));
870 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, RX_EV_PAUSE_FRM_ERR);
871
872 /* Every error apart from tobe_disc and pause_frm */
873 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
874 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
875 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
876
Ben Hutchings8ceee662008-04-27 12:55:59 +0100877 /* Count errors that are not in MAC stats. */
878 if (rx_ev_frm_trunc)
879 ++rx_queue->channel->n_rx_frm_trunc;
880 else if (rx_ev_tobe_disc)
881 ++rx_queue->channel->n_rx_tobe_disc;
882 else if (rx_ev_ip_hdr_chksum_err)
883 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
884 else if (rx_ev_tcp_udp_chksum_err)
885 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
886 if (rx_ev_ip_frag_err)
887 ++rx_queue->channel->n_rx_ip_frag_err;
888
889 /* The frame must be discarded if any of these are true. */
890 *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
891 rx_ev_tobe_disc | rx_ev_pause_frm);
892
893 /* TOBE_DISC is expected on unicast mismatches; don't print out an
894 * error message. FRM_TRUNC indicates RXDP dropped the packet due
895 * to a FIFO overflow.
896 */
897#ifdef EFX_ENABLE_DEBUG
898 if (rx_ev_other_err) {
899 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
Ben Hutchings5b39fe32008-09-01 12:46:03 +0100900 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
Ben Hutchings8ceee662008-04-27 12:55:59 +0100901 rx_queue->queue, EFX_QWORD_VAL(*event),
902 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
903 rx_ev_ip_hdr_chksum_err ?
904 " [IP_HDR_CHKSUM_ERR]" : "",
905 rx_ev_tcp_udp_chksum_err ?
906 " [TCP_UDP_CHKSUM_ERR]" : "",
907 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
908 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
909 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
910 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
Ben Hutchings5b39fe32008-09-01 12:46:03 +0100911 rx_ev_pause_frm ? " [PAUSE]" : "");
Ben Hutchings8ceee662008-04-27 12:55:59 +0100912 }
913#endif
914
915 if (unlikely(rx_ev_eth_crc_err && EFX_WORKAROUND_10750(efx) &&
916 efx->phy_type == PHY_TYPE_10XPRESS))
917 tenxpress_crc_err(efx);
918}
919
920/* Handle receive events that are not in-order. */
921static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
922 unsigned index)
923{
924 struct efx_nic *efx = rx_queue->efx;
925 unsigned expected, dropped;
926
927 expected = rx_queue->removed_count & FALCON_RXD_RING_MASK;
928 dropped = ((index + FALCON_RXD_RING_SIZE - expected) &
929 FALCON_RXD_RING_MASK);
930 EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
931 dropped, index, expected);
932
933 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
934 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
935}
936
937/* Handle a packet received event
938 *
939 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
940 * wrong destination address
941 * Also "is multicast" and "matches multicast filter" flags can be used to
942 * discard non-matching multicast packets.
943 */
Ben Hutchings42cbe2d2008-09-01 12:48:08 +0100944static void falcon_handle_rx_event(struct efx_channel *channel,
945 const efx_qword_t *event)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100946{
Ben Hutchings42cbe2d2008-09-01 12:48:08 +0100947 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100948 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100949 unsigned expected_ptr;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100950 bool rx_ev_pkt_ok, discard = false, checksummed;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100951 struct efx_rx_queue *rx_queue;
952 struct efx_nic *efx = channel->efx;
953
954 /* Basic packet information */
955 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, RX_EV_BYTE_CNT);
956 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, RX_EV_PKT_OK);
957 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
958 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_JUMBO_CONT));
959 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_SOP) != 1);
Ben Hutchings42cbe2d2008-09-01 12:48:08 +0100960 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_Q_LABEL) != channel->channel);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100961
Ben Hutchings42cbe2d2008-09-01 12:48:08 +0100962 rx_queue = &efx->rx_queue[channel->channel];
Ben Hutchings8ceee662008-04-27 12:55:59 +0100963
964 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
965 expected_ptr = rx_queue->removed_count & FALCON_RXD_RING_MASK;
Ben Hutchings42cbe2d2008-09-01 12:48:08 +0100966 if (unlikely(rx_ev_desc_ptr != expected_ptr))
Ben Hutchings8ceee662008-04-27 12:55:59 +0100967 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100968
969 if (likely(rx_ev_pkt_ok)) {
970 /* If packet is marked as OK and packet type is TCP/IPv4 or
971 * UDP/IPv4, then we can rely on the hardware checksum.
972 */
973 checksummed = RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type);
974 } else {
975 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
Ben Hutchings5b39fe32008-09-01 12:46:03 +0100976 &discard);
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100977 checksummed = false;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100978 }
979
980 /* Detect multicast packets that didn't match the filter */
981 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
982 if (rx_ev_mcast_pkt) {
983 unsigned int rx_ev_mcast_hash_match =
984 EFX_QWORD_FIELD(*event, RX_EV_MCAST_HASH_MATCH);
985
986 if (unlikely(!rx_ev_mcast_hash_match))
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100987 discard = true;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100988 }
989
990 /* Handle received packet */
991 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
992 checksummed, discard);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100993}
994
995/* Global events are basically PHY events */
996static void falcon_handle_global_event(struct efx_channel *channel,
997 efx_qword_t *event)
998{
999 struct efx_nic *efx = channel->efx;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +01001000 bool is_phy_event = false, handled = false;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001001
1002 /* Check for interrupt on either port. Some boards have a
1003 * single PHY wired to the interrupt line for port 1. */
1004 if (EFX_QWORD_FIELD(*event, G_PHY0_INTR) ||
1005 EFX_QWORD_FIELD(*event, G_PHY1_INTR) ||
1006 EFX_QWORD_FIELD(*event, XG_PHY_INTR))
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +01001007 is_phy_event = true;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001008
Ben Hutchings55668612008-05-16 21:16:10 +01001009 if ((falcon_rev(efx) >= FALCON_REV_B0) &&
Ben Hutchings8ceee662008-04-27 12:55:59 +01001010 EFX_OWORD_FIELD(*event, XG_MNT_INTR_B0))
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +01001011 is_phy_event = true;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001012
1013 if (is_phy_event) {
1014 efx->phy_op->clear_interrupt(efx);
1015 queue_work(efx->workqueue, &efx->reconfigure_work);
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +01001016 handled = true;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001017 }
1018
1019 if (EFX_QWORD_FIELD_VER(efx, *event, RX_RECOVERY)) {
1020 EFX_ERR(efx, "channel %d seen global RX_RESET "
1021 "event. Resetting.\n", channel->channel);
1022
1023 atomic_inc(&efx->rx_reset);
1024 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
1025 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +01001026 handled = true;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001027 }
1028
1029 if (!handled)
1030 EFX_ERR(efx, "channel %d unknown global event "
1031 EFX_QWORD_FMT "\n", channel->channel,
1032 EFX_QWORD_VAL(*event));
1033}
1034
1035static void falcon_handle_driver_event(struct efx_channel *channel,
1036 efx_qword_t *event)
1037{
1038 struct efx_nic *efx = channel->efx;
1039 unsigned int ev_sub_code;
1040 unsigned int ev_sub_data;
1041
1042 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
1043 ev_sub_data = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_DATA);
1044
1045 switch (ev_sub_code) {
1046 case TX_DESCQ_FLS_DONE_EV_DECODE:
1047 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
1048 channel->channel, ev_sub_data);
1049 break;
1050 case RX_DESCQ_FLS_DONE_EV_DECODE:
1051 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
1052 channel->channel, ev_sub_data);
1053 break;
1054 case EVQ_INIT_DONE_EV_DECODE:
1055 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
1056 channel->channel, ev_sub_data);
1057 break;
1058 case SRM_UPD_DONE_EV_DECODE:
1059 EFX_TRACE(efx, "channel %d SRAM update done\n",
1060 channel->channel);
1061 break;
1062 case WAKE_UP_EV_DECODE:
1063 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
1064 channel->channel, ev_sub_data);
1065 break;
1066 case TIMER_EV_DECODE:
1067 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
1068 channel->channel, ev_sub_data);
1069 break;
1070 case RX_RECOVERY_EV_DECODE:
1071 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
1072 "Resetting.\n", channel->channel);
Ben Hutchings05e3ec02008-05-07 13:00:39 +01001073 atomic_inc(&efx->rx_reset);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001074 efx_schedule_reset(efx,
1075 EFX_WORKAROUND_6555(efx) ?
1076 RESET_TYPE_RX_RECOVERY :
1077 RESET_TYPE_DISABLE);
1078 break;
1079 case RX_DSC_ERROR_EV_DECODE:
1080 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
1081 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1082 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
1083 break;
1084 case TX_DSC_ERROR_EV_DECODE:
1085 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
1086 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1087 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
1088 break;
1089 default:
1090 EFX_TRACE(efx, "channel %d unknown driver event code %d "
1091 "data %04x\n", channel->channel, ev_sub_code,
1092 ev_sub_data);
1093 break;
1094 }
1095}
1096
Ben Hutchings42cbe2d2008-09-01 12:48:08 +01001097int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001098{
1099 unsigned int read_ptr;
1100 efx_qword_t event, *p_event;
1101 int ev_code;
Ben Hutchings42cbe2d2008-09-01 12:48:08 +01001102 int rx_packets = 0;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001103
1104 read_ptr = channel->eventq_read_ptr;
1105
1106 do {
1107 p_event = falcon_event(channel, read_ptr);
1108 event = *p_event;
1109
1110 if (!falcon_event_present(&event))
1111 /* End of events */
1112 break;
1113
1114 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1115 channel->channel, EFX_QWORD_VAL(event));
1116
1117 /* Clear this event by marking it all ones */
1118 EFX_SET_QWORD(*p_event);
1119
1120 ev_code = EFX_QWORD_FIELD(event, EV_CODE);
1121
1122 switch (ev_code) {
1123 case RX_IP_EV_DECODE:
Ben Hutchings42cbe2d2008-09-01 12:48:08 +01001124 falcon_handle_rx_event(channel, &event);
1125 ++rx_packets;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001126 break;
1127 case TX_IP_EV_DECODE:
1128 falcon_handle_tx_event(channel, &event);
1129 break;
1130 case DRV_GEN_EV_DECODE:
1131 channel->eventq_magic
1132 = EFX_QWORD_FIELD(event, EVQ_MAGIC);
1133 EFX_LOG(channel->efx, "channel %d received generated "
1134 "event "EFX_QWORD_FMT"\n", channel->channel,
1135 EFX_QWORD_VAL(event));
1136 break;
1137 case GLOBAL_EV_DECODE:
1138 falcon_handle_global_event(channel, &event);
1139 break;
1140 case DRIVER_EV_DECODE:
1141 falcon_handle_driver_event(channel, &event);
1142 break;
1143 default:
1144 EFX_ERR(channel->efx, "channel %d unknown event type %d"
1145 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1146 ev_code, EFX_QWORD_VAL(event));
1147 }
1148
1149 /* Increment read pointer */
1150 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1151
Ben Hutchings42cbe2d2008-09-01 12:48:08 +01001152 } while (rx_packets < rx_quota);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001153
1154 channel->eventq_read_ptr = read_ptr;
Ben Hutchings42cbe2d2008-09-01 12:48:08 +01001155 return rx_packets;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001156}
1157
1158void falcon_set_int_moderation(struct efx_channel *channel)
1159{
1160 efx_dword_t timer_cmd;
1161 struct efx_nic *efx = channel->efx;
1162
1163 /* Set timer register */
1164 if (channel->irq_moderation) {
1165 /* Round to resolution supported by hardware. The value we
1166 * program is based at 0. So actual interrupt moderation
1167 * achieved is ((x + 1) * res).
1168 */
1169 unsigned int res = 5;
1170 channel->irq_moderation -= (channel->irq_moderation % res);
1171 if (channel->irq_moderation < res)
1172 channel->irq_moderation = res;
1173 EFX_POPULATE_DWORD_2(timer_cmd,
1174 TIMER_MODE, TIMER_MODE_INT_HLDOFF,
1175 TIMER_VAL,
1176 (channel->irq_moderation / res) - 1);
1177 } else {
1178 EFX_POPULATE_DWORD_2(timer_cmd,
1179 TIMER_MODE, TIMER_MODE_DIS,
1180 TIMER_VAL, 0);
1181 }
1182 falcon_writel_page_locked(efx, &timer_cmd, TIMER_CMD_REG_KER,
Ben Hutchingsd3074022008-09-01 12:48:03 +01001183 channel->channel);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001184
1185}
1186
1187/* Allocate buffer table entries for event queue */
1188int falcon_probe_eventq(struct efx_channel *channel)
1189{
1190 struct efx_nic *efx = channel->efx;
1191 unsigned int evq_size;
1192
1193 evq_size = FALCON_EVQ_SIZE * sizeof(efx_qword_t);
1194 return falcon_alloc_special_buffer(efx, &channel->eventq, evq_size);
1195}
1196
Ben Hutchingsbc3c90a2008-09-01 12:48:46 +01001197void falcon_init_eventq(struct efx_channel *channel)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001198{
1199 efx_oword_t evq_ptr;
1200 struct efx_nic *efx = channel->efx;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001201
1202 EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1203 channel->channel, channel->eventq.index,
1204 channel->eventq.index + channel->eventq.entries - 1);
1205
1206 /* Pin event queue buffer */
Ben Hutchingsbc3c90a2008-09-01 12:48:46 +01001207 falcon_init_special_buffer(efx, &channel->eventq);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001208
1209 /* Fill event queue with all ones (i.e. empty events) */
1210 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1211
1212 /* Push event queue to card */
1213 EFX_POPULATE_OWORD_3(evq_ptr,
1214 EVQ_EN, 1,
1215 EVQ_SIZE, FALCON_EVQ_ORDER,
1216 EVQ_BUF_BASE_ID, channel->eventq.index);
1217 falcon_write_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
Ben Hutchingsd3074022008-09-01 12:48:03 +01001218 channel->channel);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001219
1220 falcon_set_int_moderation(channel);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001221}
1222
1223void falcon_fini_eventq(struct efx_channel *channel)
1224{
1225 efx_oword_t eventq_ptr;
1226 struct efx_nic *efx = channel->efx;
1227
1228 /* Remove event queue from card */
1229 EFX_ZERO_OWORD(eventq_ptr);
1230 falcon_write_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
Ben Hutchingsd3074022008-09-01 12:48:03 +01001231 channel->channel);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001232
1233 /* Unpin event queue */
1234 falcon_fini_special_buffer(efx, &channel->eventq);
1235}
1236
1237/* Free buffers backing event queue */
1238void falcon_remove_eventq(struct efx_channel *channel)
1239{
1240 falcon_free_special_buffer(channel->efx, &channel->eventq);
1241}
1242
1243
1244/* Generates a test event on the event queue. A subsequent call to
1245 * process_eventq() should pick up the event and place the value of
1246 * "magic" into channel->eventq_magic;
1247 */
1248void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1249{
1250 efx_qword_t test_event;
1251
1252 EFX_POPULATE_QWORD_2(test_event,
1253 EV_CODE, DRV_GEN_EV_DECODE,
1254 EVQ_MAGIC, magic);
1255 falcon_generate_event(channel, &test_event);
1256}
1257
1258
1259/**************************************************************************
1260 *
1261 * Falcon hardware interrupts
1262 * The hardware interrupt handler does very little work; all the event
1263 * queue processing is carried out by per-channel tasklets.
1264 *
1265 **************************************************************************/
1266
1267/* Enable/disable/generate Falcon interrupts */
1268static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1269 int force)
1270{
1271 efx_oword_t int_en_reg_ker;
1272
1273 EFX_POPULATE_OWORD_2(int_en_reg_ker,
1274 KER_INT_KER, force,
1275 DRV_INT_EN_KER, enabled);
1276 falcon_write(efx, &int_en_reg_ker, INT_EN_REG_KER);
1277}
1278
1279void falcon_enable_interrupts(struct efx_nic *efx)
1280{
1281 efx_oword_t int_adr_reg_ker;
1282 struct efx_channel *channel;
1283
1284 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1285 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1286
1287 /* Program address */
1288 EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1289 NORM_INT_VEC_DIS_KER, EFX_INT_MODE_USE_MSI(efx),
1290 INT_ADR_KER, efx->irq_status.dma_addr);
1291 falcon_write(efx, &int_adr_reg_ker, INT_ADR_REG_KER);
1292
1293 /* Enable interrupts */
1294 falcon_interrupts(efx, 1, 0);
1295
1296 /* Force processing of all the channels to get the EVQ RPTRs up to
1297 date */
Ben Hutchings64ee3122008-09-01 12:47:38 +01001298 efx_for_each_channel(channel, efx)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001299 efx_schedule_channel(channel);
1300}
1301
1302void falcon_disable_interrupts(struct efx_nic *efx)
1303{
1304 /* Disable interrupts */
1305 falcon_interrupts(efx, 0, 0);
1306}
1307
1308/* Generate a Falcon test interrupt
1309 * Interrupt must already have been enabled, otherwise nasty things
1310 * may happen.
1311 */
1312void falcon_generate_interrupt(struct efx_nic *efx)
1313{
1314 falcon_interrupts(efx, 1, 1);
1315}
1316
1317/* Acknowledge a legacy interrupt from Falcon
1318 *
1319 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1320 *
1321 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1322 * BIU. Interrupt acknowledge is read sensitive so must write instead
1323 * (then read to ensure the BIU collector is flushed)
1324 *
1325 * NB most hardware supports MSI interrupts
1326 */
1327static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1328{
1329 efx_dword_t reg;
1330
1331 EFX_POPULATE_DWORD_1(reg, INT_ACK_DUMMY_DATA, 0xb7eb7e);
1332 falcon_writel(efx, &reg, INT_ACK_REG_KER_A1);
1333 falcon_readl(efx, &reg, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1);
1334}
1335
1336/* Process a fatal interrupt
1337 * Disable bus mastering ASAP and schedule a reset
1338 */
1339static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1340{
1341 struct falcon_nic_data *nic_data = efx->nic_data;
Ben Hutchingsd3208b52008-05-16 21:20:00 +01001342 efx_oword_t *int_ker = efx->irq_status.addr;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001343 efx_oword_t fatal_intr;
1344 int error, mem_perr;
1345 static int n_int_errors;
1346
1347 falcon_read(efx, &fatal_intr, FATAL_INTR_REG_KER);
1348 error = EFX_OWORD_FIELD(fatal_intr, INT_KER_ERROR);
1349
1350 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1351 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1352 EFX_OWORD_VAL(fatal_intr),
1353 error ? "disabling bus mastering" : "no recognised error");
1354 if (error == 0)
1355 goto out;
1356
1357 /* If this is a memory parity error dump which blocks are offending */
1358 mem_perr = EFX_OWORD_FIELD(fatal_intr, MEM_PERR_INT_KER);
1359 if (mem_perr) {
1360 efx_oword_t reg;
1361 falcon_read(efx, &reg, MEM_STAT_REG_KER);
1362 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1363 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1364 }
1365
1366 /* Disable DMA bus mastering on both devices */
1367 pci_disable_device(efx->pci_dev);
1368 if (FALCON_IS_DUAL_FUNC(efx))
1369 pci_disable_device(nic_data->pci_dev2);
1370
1371 if (++n_int_errors < FALCON_MAX_INT_ERRORS) {
1372 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1373 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1374 } else {
1375 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1376 "NIC will be disabled\n");
1377 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1378 }
1379out:
1380 return IRQ_HANDLED;
1381}
1382
1383/* Handle a legacy interrupt from Falcon
1384 * Acknowledges the interrupt and schedule event queue processing.
1385 */
1386static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1387{
Ben Hutchingsd3208b52008-05-16 21:20:00 +01001388 struct efx_nic *efx = dev_id;
1389 efx_oword_t *int_ker = efx->irq_status.addr;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001390 struct efx_channel *channel;
1391 efx_dword_t reg;
1392 u32 queues;
1393 int syserr;
1394
1395 /* Read the ISR which also ACKs the interrupts */
1396 falcon_readl(efx, &reg, INT_ISR0_B0);
1397 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1398
1399 /* Check to see if we have a serious error condition */
1400 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1401 if (unlikely(syserr))
1402 return falcon_fatal_interrupt(efx);
1403
1404 if (queues == 0)
1405 return IRQ_NONE;
1406
1407 efx->last_irq_cpu = raw_smp_processor_id();
1408 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1409 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1410
1411 /* Schedule processing of any interrupting queues */
1412 channel = &efx->channel[0];
1413 while (queues) {
1414 if (queues & 0x01)
1415 efx_schedule_channel(channel);
1416 channel++;
1417 queues >>= 1;
1418 }
1419
1420 return IRQ_HANDLED;
1421}
1422
1423
1424static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1425{
Ben Hutchingsd3208b52008-05-16 21:20:00 +01001426 struct efx_nic *efx = dev_id;
1427 efx_oword_t *int_ker = efx->irq_status.addr;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001428 struct efx_channel *channel;
1429 int syserr;
1430 int queues;
1431
1432 /* Check to see if this is our interrupt. If it isn't, we
1433 * exit without having touched the hardware.
1434 */
1435 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1436 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1437 raw_smp_processor_id());
1438 return IRQ_NONE;
1439 }
1440 efx->last_irq_cpu = raw_smp_processor_id();
1441 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1442 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1443
1444 /* Check to see if we have a serious error condition */
1445 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1446 if (unlikely(syserr))
1447 return falcon_fatal_interrupt(efx);
1448
1449 /* Determine interrupting queues, clear interrupt status
1450 * register and acknowledge the device interrupt.
1451 */
1452 BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1453 queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1454 EFX_ZERO_OWORD(*int_ker);
1455 wmb(); /* Ensure the vector is cleared before interrupt ack */
1456 falcon_irq_ack_a1(efx);
1457
1458 /* Schedule processing of any interrupting queues */
1459 channel = &efx->channel[0];
1460 while (queues) {
1461 if (queues & 0x01)
1462 efx_schedule_channel(channel);
1463 channel++;
1464 queues >>= 1;
1465 }
1466
1467 return IRQ_HANDLED;
1468}
1469
1470/* Handle an MSI interrupt from Falcon
1471 *
1472 * Handle an MSI hardware interrupt. This routine schedules event
1473 * queue processing. No interrupt acknowledgement cycle is necessary.
1474 * Also, we never need to check that the interrupt is for us, since
1475 * MSI interrupts cannot be shared.
1476 */
1477static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1478{
Ben Hutchingsd3208b52008-05-16 21:20:00 +01001479 struct efx_channel *channel = dev_id;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001480 struct efx_nic *efx = channel->efx;
Ben Hutchingsd3208b52008-05-16 21:20:00 +01001481 efx_oword_t *int_ker = efx->irq_status.addr;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001482 int syserr;
1483
1484 efx->last_irq_cpu = raw_smp_processor_id();
1485 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1486 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1487
1488 /* Check to see if we have a serious error condition */
1489 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1490 if (unlikely(syserr))
1491 return falcon_fatal_interrupt(efx);
1492
1493 /* Schedule processing of the channel */
1494 efx_schedule_channel(channel);
1495
1496 return IRQ_HANDLED;
1497}
1498
1499
1500/* Setup RSS indirection table.
1501 * This maps from the hash value of the packet to RXQ
1502 */
1503static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1504{
1505 int i = 0;
1506 unsigned long offset;
1507 efx_dword_t dword;
1508
Ben Hutchings55668612008-05-16 21:16:10 +01001509 if (falcon_rev(efx) < FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001510 return;
1511
1512 for (offset = RX_RSS_INDIR_TBL_B0;
1513 offset < RX_RSS_INDIR_TBL_B0 + 0x800;
1514 offset += 0x10) {
1515 EFX_POPULATE_DWORD_1(dword, RX_RSS_INDIR_ENT_B0,
Ben Hutchings8831da72008-09-01 12:47:48 +01001516 i % efx->n_rx_queues);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001517 falcon_writel(efx, &dword, offset);
1518 i++;
1519 }
1520}
1521
1522/* Hook interrupt handler(s)
1523 * Try MSI and then legacy interrupts.
1524 */
1525int falcon_init_interrupt(struct efx_nic *efx)
1526{
1527 struct efx_channel *channel;
1528 int rc;
1529
1530 if (!EFX_INT_MODE_USE_MSI(efx)) {
1531 irq_handler_t handler;
Ben Hutchings55668612008-05-16 21:16:10 +01001532 if (falcon_rev(efx) >= FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001533 handler = falcon_legacy_interrupt_b0;
1534 else
1535 handler = falcon_legacy_interrupt_a1;
1536
1537 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1538 efx->name, efx);
1539 if (rc) {
1540 EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1541 efx->pci_dev->irq);
1542 goto fail1;
1543 }
1544 return 0;
1545 }
1546
1547 /* Hook MSI or MSI-X interrupt */
Ben Hutchings64ee3122008-09-01 12:47:38 +01001548 efx_for_each_channel(channel, efx) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01001549 rc = request_irq(channel->irq, falcon_msi_interrupt,
1550 IRQF_PROBE_SHARED, /* Not shared */
1551 efx->name, channel);
1552 if (rc) {
1553 EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1554 goto fail2;
1555 }
1556 }
1557
1558 return 0;
1559
1560 fail2:
Ben Hutchings64ee3122008-09-01 12:47:38 +01001561 efx_for_each_channel(channel, efx)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001562 free_irq(channel->irq, channel);
1563 fail1:
1564 return rc;
1565}
1566
1567void falcon_fini_interrupt(struct efx_nic *efx)
1568{
1569 struct efx_channel *channel;
1570 efx_oword_t reg;
1571
1572 /* Disable MSI/MSI-X interrupts */
Ben Hutchings64ee3122008-09-01 12:47:38 +01001573 efx_for_each_channel(channel, efx) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01001574 if (channel->irq)
1575 free_irq(channel->irq, channel);
Ben Hutchingsb3475642008-05-16 21:15:49 +01001576 }
Ben Hutchings8ceee662008-04-27 12:55:59 +01001577
1578 /* ACK legacy interrupt */
Ben Hutchings55668612008-05-16 21:16:10 +01001579 if (falcon_rev(efx) >= FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001580 falcon_read(efx, &reg, INT_ISR0_B0);
1581 else
1582 falcon_irq_ack_a1(efx);
1583
1584 /* Disable legacy interrupt */
1585 if (efx->legacy_irq)
1586 free_irq(efx->legacy_irq, efx);
1587}
1588
1589/**************************************************************************
1590 *
1591 * EEPROM/flash
1592 *
1593 **************************************************************************
1594 */
1595
1596#define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1597
1598/* Wait for SPI command completion */
1599static int falcon_spi_wait(struct efx_nic *efx)
1600{
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001601 unsigned long timeout = jiffies + DIV_ROUND_UP(HZ, 10);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001602 efx_oword_t reg;
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001603 bool cmd_en, timer_active;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001604
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001605 for (;;) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01001606 falcon_read(efx, &reg, EE_SPI_HCMD_REG_KER);
1607 cmd_en = EFX_OWORD_FIELD(reg, EE_SPI_HCMD_CMD_EN);
1608 timer_active = EFX_OWORD_FIELD(reg, EE_WR_TIMER_ACTIVE);
1609 if (!cmd_en && !timer_active)
1610 return 0;
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001611 if (time_after_eq(jiffies, timeout)) {
1612 EFX_ERR(efx, "timed out waiting for SPI\n");
1613 return -ETIMEDOUT;
1614 }
1615 cpu_relax();
1616 }
Ben Hutchings8ceee662008-04-27 12:55:59 +01001617}
1618
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001619static int falcon_spi_cmd(const struct efx_spi_device *spi,
1620 unsigned int command, int address,
1621 const void *in, void *out, unsigned int len)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001622{
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001623 struct efx_nic *efx = spi->efx;
1624 bool addressed = (address >= 0);
1625 bool reading = (out != NULL);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001626 efx_oword_t reg;
1627 int rc;
1628
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001629 /* Input validation */
1630 if (len > FALCON_SPI_MAX_LEN)
1631 return -EINVAL;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001632
1633 /* Check SPI not currently being accessed */
1634 rc = falcon_spi_wait(efx);
1635 if (rc)
1636 return rc;
1637
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001638 /* Program address register, if we have an address */
1639 if (addressed) {
1640 EFX_POPULATE_OWORD_1(reg, EE_SPI_HADR_ADR, address);
1641 falcon_write(efx, &reg, EE_SPI_HADR_REG_KER);
1642 }
Ben Hutchings8ceee662008-04-27 12:55:59 +01001643
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001644 /* Program data register, if we have data */
1645 if (in != NULL) {
1646 memcpy(&reg, in, len);
1647 falcon_write(efx, &reg, EE_SPI_HDATA_REG_KER);
1648 }
1649
1650 /* Issue read/write command */
Ben Hutchings8ceee662008-04-27 12:55:59 +01001651 EFX_POPULATE_OWORD_7(reg,
1652 EE_SPI_HCMD_CMD_EN, 1,
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001653 EE_SPI_HCMD_SF_SEL, spi->device_id,
Ben Hutchings8ceee662008-04-27 12:55:59 +01001654 EE_SPI_HCMD_DABCNT, len,
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001655 EE_SPI_HCMD_READ, reading,
Ben Hutchings8ceee662008-04-27 12:55:59 +01001656 EE_SPI_HCMD_DUBCNT, 0,
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001657 EE_SPI_HCMD_ADBCNT,
1658 (addressed ? spi->addr_len : 0),
Ben Hutchings8ceee662008-04-27 12:55:59 +01001659 EE_SPI_HCMD_ENC, command);
1660 falcon_write(efx, &reg, EE_SPI_HCMD_REG_KER);
1661
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001662 /* Wait for read/write to complete */
Ben Hutchings8ceee662008-04-27 12:55:59 +01001663 rc = falcon_spi_wait(efx);
1664 if (rc)
1665 return rc;
1666
1667 /* Read data */
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001668 if (out != NULL) {
1669 falcon_read(efx, &reg, EE_SPI_HDATA_REG_KER);
1670 memcpy(out, &reg, len);
1671 }
1672
Ben Hutchings8ceee662008-04-27 12:55:59 +01001673 return 0;
1674}
1675
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001676static unsigned int
1677falcon_spi_write_limit(const struct efx_spi_device *spi, unsigned int start)
1678{
1679 return min(FALCON_SPI_MAX_LEN,
1680 (spi->block_size - (start & (spi->block_size - 1))));
1681}
1682
1683static inline u8
1684efx_spi_munge_command(const struct efx_spi_device *spi,
1685 const u8 command, const unsigned int address)
1686{
1687 return command | (((address >> 8) & spi->munge_address) << 3);
1688}
1689
1690
1691static int falcon_spi_fast_wait(const struct efx_spi_device *spi)
1692{
1693 u8 status;
1694 int i, rc;
1695
1696 /* Wait up to 1000us for flash/EEPROM to finish a fast operation. */
1697 for (i = 0; i < 50; i++) {
1698 udelay(20);
1699
1700 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
1701 &status, sizeof(status));
1702 if (rc)
1703 return rc;
1704 if (!(status & SPI_STATUS_NRDY))
1705 return 0;
1706 }
1707 EFX_ERR(spi->efx,
1708 "timed out waiting for device %d last status=0x%02x\n",
1709 spi->device_id, status);
1710 return -ETIMEDOUT;
1711}
1712
1713int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1714 size_t len, size_t *retlen, u8 *buffer)
1715{
1716 unsigned int command, block_len, pos = 0;
1717 int rc = 0;
1718
1719 while (pos < len) {
1720 block_len = min((unsigned int)len - pos,
1721 FALCON_SPI_MAX_LEN);
1722
1723 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1724 rc = falcon_spi_cmd(spi, command, start + pos, NULL,
1725 buffer + pos, block_len);
1726 if (rc)
1727 break;
1728 pos += block_len;
1729
1730 /* Avoid locking up the system */
1731 cond_resched();
1732 if (signal_pending(current)) {
1733 rc = -EINTR;
1734 break;
1735 }
1736 }
1737
1738 if (retlen)
1739 *retlen = pos;
1740 return rc;
1741}
1742
1743int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1744 size_t len, size_t *retlen, const u8 *buffer)
1745{
1746 u8 verify_buffer[FALCON_SPI_MAX_LEN];
1747 unsigned int command, block_len, pos = 0;
1748 int rc = 0;
1749
1750 while (pos < len) {
1751 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
1752 if (rc)
1753 break;
1754
1755 block_len = min((unsigned int)len - pos,
1756 falcon_spi_write_limit(spi, start + pos));
1757 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1758 rc = falcon_spi_cmd(spi, command, start + pos,
1759 buffer + pos, NULL, block_len);
1760 if (rc)
1761 break;
1762
1763 rc = falcon_spi_fast_wait(spi);
1764 if (rc)
1765 break;
1766
1767 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1768 rc = falcon_spi_cmd(spi, command, start + pos,
1769 NULL, verify_buffer, block_len);
1770 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1771 rc = -EIO;
1772 break;
1773 }
1774
1775 pos += block_len;
1776
1777 /* Avoid locking up the system */
1778 cond_resched();
1779 if (signal_pending(current)) {
1780 rc = -EINTR;
1781 break;
1782 }
1783 }
1784
1785 if (retlen)
1786 *retlen = pos;
1787 return rc;
1788}
1789
Ben Hutchings8ceee662008-04-27 12:55:59 +01001790/**************************************************************************
1791 *
1792 * MAC wrapper
1793 *
1794 **************************************************************************
1795 */
1796void falcon_drain_tx_fifo(struct efx_nic *efx)
1797{
1798 efx_oword_t temp;
1799 int count;
1800
Ben Hutchings55668612008-05-16 21:16:10 +01001801 if ((falcon_rev(efx) < FALCON_REV_B0) ||
Ben Hutchings3273c2e2008-05-07 13:36:19 +01001802 (efx->loopback_mode != LOOPBACK_NONE))
Ben Hutchings8ceee662008-04-27 12:55:59 +01001803 return;
1804
1805 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1806 /* There is no point in draining more than once */
1807 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1808 return;
1809
1810 /* MAC stats will fail whilst the TX fifo is draining. Serialise
1811 * the drain sequence with the statistics fetch */
1812 spin_lock(&efx->stats_lock);
1813
1814 EFX_SET_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0, 1);
1815 falcon_write(efx, &temp, MAC0_CTRL_REG_KER);
1816
1817 /* Reset the MAC and EM block. */
1818 falcon_read(efx, &temp, GLB_CTL_REG_KER);
1819 EFX_SET_OWORD_FIELD(temp, RST_XGTX, 1);
1820 EFX_SET_OWORD_FIELD(temp, RST_XGRX, 1);
1821 EFX_SET_OWORD_FIELD(temp, RST_EM, 1);
1822 falcon_write(efx, &temp, GLB_CTL_REG_KER);
1823
1824 count = 0;
1825 while (1) {
1826 falcon_read(efx, &temp, GLB_CTL_REG_KER);
1827 if (!EFX_OWORD_FIELD(temp, RST_XGTX) &&
1828 !EFX_OWORD_FIELD(temp, RST_XGRX) &&
1829 !EFX_OWORD_FIELD(temp, RST_EM)) {
1830 EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1831 count);
1832 break;
1833 }
1834 if (count > 20) {
1835 EFX_ERR(efx, "MAC reset failed\n");
1836 break;
1837 }
1838 count++;
1839 udelay(10);
1840 }
1841
1842 spin_unlock(&efx->stats_lock);
1843
1844 /* If we've reset the EM block and the link is up, then
1845 * we'll have to kick the XAUI link so the PHY can recover */
1846 if (efx->link_up && EFX_WORKAROUND_5147(efx))
1847 falcon_reset_xaui(efx);
1848}
1849
1850void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1851{
1852 efx_oword_t temp;
1853
Ben Hutchings55668612008-05-16 21:16:10 +01001854 if (falcon_rev(efx) < FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001855 return;
1856
1857 /* Isolate the MAC -> RX */
1858 falcon_read(efx, &temp, RX_CFG_REG_KER);
1859 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 0);
1860 falcon_write(efx, &temp, RX_CFG_REG_KER);
1861
1862 if (!efx->link_up)
1863 falcon_drain_tx_fifo(efx);
1864}
1865
1866void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1867{
1868 efx_oword_t reg;
1869 int link_speed;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +01001870 bool tx_fc;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001871
1872 if (efx->link_options & GM_LPA_10000)
1873 link_speed = 0x3;
1874 else if (efx->link_options & GM_LPA_1000)
1875 link_speed = 0x2;
1876 else if (efx->link_options & GM_LPA_100)
1877 link_speed = 0x1;
1878 else
1879 link_speed = 0x0;
1880 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1881 * as advertised. Disable to ensure packets are not
1882 * indefinitely held and TX queue can be flushed at any point
1883 * while the link is down. */
1884 EFX_POPULATE_OWORD_5(reg,
1885 MAC_XOFF_VAL, 0xffff /* max pause time */,
1886 MAC_BCAD_ACPT, 1,
1887 MAC_UC_PROM, efx->promiscuous,
1888 MAC_LINK_STATUS, 1, /* always set */
1889 MAC_SPEED, link_speed);
1890 /* On B0, MAC backpressure can be disabled and packets get
1891 * discarded. */
Ben Hutchings55668612008-05-16 21:16:10 +01001892 if (falcon_rev(efx) >= FALCON_REV_B0) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01001893 EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0,
1894 !efx->link_up);
1895 }
1896
1897 falcon_write(efx, &reg, MAC0_CTRL_REG_KER);
1898
1899 /* Restore the multicast hash registers. */
1900 falcon_set_multicast_hash(efx);
1901
1902 /* Transmission of pause frames when RX crosses the threshold is
1903 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
1904 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +01001905 tx_fc = !!(efx->flow_control & EFX_FC_TX);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001906 falcon_read(efx, &reg, RX_CFG_REG_KER);
1907 EFX_SET_OWORD_FIELD_VER(efx, reg, RX_XOFF_MAC_EN, tx_fc);
1908
1909 /* Unisolate the MAC -> RX */
Ben Hutchings55668612008-05-16 21:16:10 +01001910 if (falcon_rev(efx) >= FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001911 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 1);
1912 falcon_write(efx, &reg, RX_CFG_REG_KER);
1913}
1914
1915int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
1916{
1917 efx_oword_t reg;
1918 u32 *dma_done;
1919 int i;
1920
1921 if (disable_dma_stats)
1922 return 0;
1923
1924 /* Statistics fetch will fail if the MAC is in TX drain */
Ben Hutchings55668612008-05-16 21:16:10 +01001925 if (falcon_rev(efx) >= FALCON_REV_B0) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01001926 efx_oword_t temp;
1927 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1928 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1929 return 0;
1930 }
1931
1932 dma_done = (efx->stats_buffer.addr + done_offset);
1933 *dma_done = FALCON_STATS_NOT_DONE;
1934 wmb(); /* ensure done flag is clear */
1935
1936 /* Initiate DMA transfer of stats */
1937 EFX_POPULATE_OWORD_2(reg,
1938 MAC_STAT_DMA_CMD, 1,
1939 MAC_STAT_DMA_ADR,
1940 efx->stats_buffer.dma_addr);
1941 falcon_write(efx, &reg, MAC0_STAT_DMA_REG_KER);
1942
1943 /* Wait for transfer to complete */
1944 for (i = 0; i < 400; i++) {
1945 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE)
1946 return 0;
1947 udelay(10);
1948 }
1949
1950 EFX_ERR(efx, "timed out waiting for statistics\n");
1951 return -ETIMEDOUT;
1952}
1953
1954/**************************************************************************
1955 *
1956 * PHY access via GMII
1957 *
1958 **************************************************************************
1959 */
1960
1961/* Use the top bit of the MII PHY id to indicate the PHY type
1962 * (1G/10G), with the remaining bits as the actual PHY id.
1963 *
1964 * This allows us to avoid leaking information from the mii_if_info
1965 * structure into other data structures.
1966 */
1967#define FALCON_PHY_ID_ID_WIDTH EFX_WIDTH(MD_PRT_DEV_ADR)
1968#define FALCON_PHY_ID_ID_MASK ((1 << FALCON_PHY_ID_ID_WIDTH) - 1)
1969#define FALCON_PHY_ID_WIDTH (FALCON_PHY_ID_ID_WIDTH + 1)
1970#define FALCON_PHY_ID_MASK ((1 << FALCON_PHY_ID_WIDTH) - 1)
1971#define FALCON_PHY_ID_10G (1 << (FALCON_PHY_ID_WIDTH - 1))
1972
1973
1974/* Packing the clause 45 port and device fields into a single value */
1975#define MD_PRT_ADR_COMP_LBN (MD_PRT_ADR_LBN - MD_DEV_ADR_LBN)
1976#define MD_PRT_ADR_COMP_WIDTH MD_PRT_ADR_WIDTH
1977#define MD_DEV_ADR_COMP_LBN 0
1978#define MD_DEV_ADR_COMP_WIDTH MD_DEV_ADR_WIDTH
1979
1980
1981/* Wait for GMII access to complete */
1982static int falcon_gmii_wait(struct efx_nic *efx)
1983{
1984 efx_dword_t md_stat;
1985 int count;
1986
1987 for (count = 0; count < 1000; count++) { /* wait upto 10ms */
1988 falcon_readl(efx, &md_stat, MD_STAT_REG_KER);
1989 if (EFX_DWORD_FIELD(md_stat, MD_BSY) == 0) {
1990 if (EFX_DWORD_FIELD(md_stat, MD_LNFL) != 0 ||
1991 EFX_DWORD_FIELD(md_stat, MD_BSERR) != 0) {
1992 EFX_ERR(efx, "error from GMII access "
1993 EFX_DWORD_FMT"\n",
1994 EFX_DWORD_VAL(md_stat));
1995 return -EIO;
1996 }
1997 return 0;
1998 }
1999 udelay(10);
2000 }
2001 EFX_ERR(efx, "timed out waiting for GMII\n");
2002 return -ETIMEDOUT;
2003}
2004
2005/* Writes a GMII register of a PHY connected to Falcon using MDIO. */
2006static void falcon_mdio_write(struct net_device *net_dev, int phy_id,
2007 int addr, int value)
2008{
Ben Hutchings767e4682008-09-01 12:43:14 +01002009 struct efx_nic *efx = netdev_priv(net_dev);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002010 unsigned int phy_id2 = phy_id & FALCON_PHY_ID_ID_MASK;
2011 efx_oword_t reg;
2012
2013 /* The 'generic' prt/dev packing in mdio_10g.h is conveniently
2014 * chosen so that the only current user, Falcon, can take the
2015 * packed value and use them directly.
2016 * Fail to build if this assumption is broken.
2017 */
2018 BUILD_BUG_ON(FALCON_PHY_ID_10G != MDIO45_XPRT_ID_IS10G);
2019 BUILD_BUG_ON(FALCON_PHY_ID_ID_WIDTH != MDIO45_PRT_DEV_WIDTH);
2020 BUILD_BUG_ON(MD_PRT_ADR_COMP_LBN != MDIO45_PRT_ID_COMP_LBN);
2021 BUILD_BUG_ON(MD_DEV_ADR_COMP_LBN != MDIO45_DEV_ID_COMP_LBN);
2022
2023 if (phy_id2 == PHY_ADDR_INVALID)
2024 return;
2025
2026 /* See falcon_mdio_read for an explanation. */
2027 if (!(phy_id & FALCON_PHY_ID_10G)) {
2028 int mmd = ffs(efx->phy_op->mmds) - 1;
2029 EFX_TRACE(efx, "Fixing erroneous clause22 write\n");
2030 phy_id2 = mdio_clause45_pack(phy_id2, mmd)
2031 & FALCON_PHY_ID_ID_MASK;
2032 }
2033
2034 EFX_REGDUMP(efx, "writing GMII %d register %02x with %04x\n", phy_id,
2035 addr, value);
2036
2037 spin_lock_bh(&efx->phy_lock);
2038
2039 /* Check MII not currently being accessed */
2040 if (falcon_gmii_wait(efx) != 0)
2041 goto out;
2042
2043 /* Write the address/ID register */
2044 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2045 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2046
2047 EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_id2);
2048 falcon_write(efx, &reg, MD_ID_REG_KER);
2049
2050 /* Write data */
2051 EFX_POPULATE_OWORD_1(reg, MD_TXD, value);
2052 falcon_write(efx, &reg, MD_TXD_REG_KER);
2053
2054 EFX_POPULATE_OWORD_2(reg,
2055 MD_WRC, 1,
2056 MD_GC, 0);
2057 falcon_write(efx, &reg, MD_CS_REG_KER);
2058
2059 /* Wait for data to be written */
2060 if (falcon_gmii_wait(efx) != 0) {
2061 /* Abort the write operation */
2062 EFX_POPULATE_OWORD_2(reg,
2063 MD_WRC, 0,
2064 MD_GC, 1);
2065 falcon_write(efx, &reg, MD_CS_REG_KER);
2066 udelay(10);
2067 }
2068
2069 out:
2070 spin_unlock_bh(&efx->phy_lock);
2071}
2072
2073/* Reads a GMII register from a PHY connected to Falcon. If no value
2074 * could be read, -1 will be returned. */
2075static int falcon_mdio_read(struct net_device *net_dev, int phy_id, int addr)
2076{
Ben Hutchings767e4682008-09-01 12:43:14 +01002077 struct efx_nic *efx = netdev_priv(net_dev);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002078 unsigned int phy_addr = phy_id & FALCON_PHY_ID_ID_MASK;
2079 efx_oword_t reg;
2080 int value = -1;
2081
2082 if (phy_addr == PHY_ADDR_INVALID)
2083 return -1;
2084
2085 /* Our PHY code knows whether it needs to talk clause 22(1G) or 45(10G)
2086 * but the generic Linux code does not make any distinction or have
2087 * any state for this.
2088 * We spot the case where someone tried to talk 22 to a 45 PHY and
2089 * redirect the request to the lowest numbered MMD as a clause45
2090 * request. This is enough to allow simple queries like id and link
2091 * state to succeed. TODO: We may need to do more in future.
2092 */
2093 if (!(phy_id & FALCON_PHY_ID_10G)) {
2094 int mmd = ffs(efx->phy_op->mmds) - 1;
2095 EFX_TRACE(efx, "Fixing erroneous clause22 read\n");
2096 phy_addr = mdio_clause45_pack(phy_addr, mmd)
2097 & FALCON_PHY_ID_ID_MASK;
2098 }
2099
2100 spin_lock_bh(&efx->phy_lock);
2101
2102 /* Check MII not currently being accessed */
2103 if (falcon_gmii_wait(efx) != 0)
2104 goto out;
2105
2106 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2107 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2108
2109 EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_addr);
2110 falcon_write(efx, &reg, MD_ID_REG_KER);
2111
2112 /* Request data to be read */
2113 EFX_POPULATE_OWORD_2(reg, MD_RDC, 1, MD_GC, 0);
2114 falcon_write(efx, &reg, MD_CS_REG_KER);
2115
2116 /* Wait for data to become available */
2117 value = falcon_gmii_wait(efx);
2118 if (value == 0) {
2119 falcon_read(efx, &reg, MD_RXD_REG_KER);
2120 value = EFX_OWORD_FIELD(reg, MD_RXD);
2121 EFX_REGDUMP(efx, "read from GMII %d register %02x, got %04x\n",
2122 phy_id, addr, value);
2123 } else {
2124 /* Abort the read operation */
2125 EFX_POPULATE_OWORD_2(reg,
2126 MD_RIC, 0,
2127 MD_GC, 1);
2128 falcon_write(efx, &reg, MD_CS_REG_KER);
2129
2130 EFX_LOG(efx, "read from GMII 0x%x register %02x, got "
2131 "error %d\n", phy_id, addr, value);
2132 }
2133
2134 out:
2135 spin_unlock_bh(&efx->phy_lock);
2136
2137 return value;
2138}
2139
2140static void falcon_init_mdio(struct mii_if_info *gmii)
2141{
2142 gmii->mdio_read = falcon_mdio_read;
2143 gmii->mdio_write = falcon_mdio_write;
2144 gmii->phy_id_mask = FALCON_PHY_ID_MASK;
2145 gmii->reg_num_mask = ((1 << EFX_WIDTH(MD_PHY_ADR)) - 1);
2146}
2147
2148static int falcon_probe_phy(struct efx_nic *efx)
2149{
2150 switch (efx->phy_type) {
2151 case PHY_TYPE_10XPRESS:
2152 efx->phy_op = &falcon_tenxpress_phy_ops;
2153 break;
2154 case PHY_TYPE_XFP:
2155 efx->phy_op = &falcon_xfp_phy_ops;
2156 break;
2157 default:
2158 EFX_ERR(efx, "Unknown PHY type %d\n",
2159 efx->phy_type);
2160 return -1;
2161 }
Ben Hutchings3273c2e2008-05-07 13:36:19 +01002162
2163 efx->loopback_modes = LOOPBACKS_10G_INTERNAL | efx->phy_op->loopbacks;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002164 return 0;
2165}
2166
2167/* This call is responsible for hooking in the MAC and PHY operations */
2168int falcon_probe_port(struct efx_nic *efx)
2169{
2170 int rc;
2171
2172 /* Hook in PHY operations table */
2173 rc = falcon_probe_phy(efx);
2174 if (rc)
2175 return rc;
2176
2177 /* Set up GMII structure for PHY */
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +01002178 efx->mii.supports_gmii = true;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002179 falcon_init_mdio(&efx->mii);
2180
2181 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
Ben Hutchings55668612008-05-16 21:16:10 +01002182 if (falcon_rev(efx) >= FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +01002183 efx->flow_control = EFX_FC_RX | EFX_FC_TX;
2184 else
2185 efx->flow_control = EFX_FC_RX;
2186
2187 /* Allocate buffer for stats */
2188 rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2189 FALCON_MAC_STATS_SIZE);
2190 if (rc)
2191 return rc;
2192 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %lx)\n",
2193 (unsigned long long)efx->stats_buffer.dma_addr,
2194 efx->stats_buffer.addr,
2195 virt_to_phys(efx->stats_buffer.addr));
2196
2197 return 0;
2198}
2199
2200void falcon_remove_port(struct efx_nic *efx)
2201{
2202 falcon_free_buffer(efx, &efx->stats_buffer);
2203}
2204
2205/**************************************************************************
2206 *
2207 * Multicast filtering
2208 *
2209 **************************************************************************
2210 */
2211
2212void falcon_set_multicast_hash(struct efx_nic *efx)
2213{
2214 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2215
2216 /* Broadcast packets go through the multicast hash filter.
2217 * ether_crc_le() of the broadcast address is 0xbe2612ff
2218 * so we always add bit 0xff to the mask.
2219 */
2220 set_bit_le(0xff, mc_hash->byte);
2221
2222 falcon_write(efx, &mc_hash->oword[0], MAC_MCAST_HASH_REG0_KER);
2223 falcon_write(efx, &mc_hash->oword[1], MAC_MCAST_HASH_REG1_KER);
2224}
2225
2226/**************************************************************************
2227 *
2228 * Device reset
2229 *
2230 **************************************************************************
2231 */
2232
2233/* Resets NIC to known state. This routine must be called in process
2234 * context and is allowed to sleep. */
2235int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2236{
2237 struct falcon_nic_data *nic_data = efx->nic_data;
2238 efx_oword_t glb_ctl_reg_ker;
2239 int rc;
2240
2241 EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2242
2243 /* Initiate device reset */
2244 if (method == RESET_TYPE_WORLD) {
2245 rc = pci_save_state(efx->pci_dev);
2246 if (rc) {
2247 EFX_ERR(efx, "failed to backup PCI state of primary "
2248 "function prior to hardware reset\n");
2249 goto fail1;
2250 }
2251 if (FALCON_IS_DUAL_FUNC(efx)) {
2252 rc = pci_save_state(nic_data->pci_dev2);
2253 if (rc) {
2254 EFX_ERR(efx, "failed to backup PCI state of "
2255 "secondary function prior to "
2256 "hardware reset\n");
2257 goto fail2;
2258 }
2259 }
2260
2261 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2262 EXT_PHY_RST_DUR, 0x7,
2263 SWRST, 1);
2264 } else {
2265 int reset_phy = (method == RESET_TYPE_INVISIBLE ?
2266 EXCLUDE_FROM_RESET : 0);
2267
2268 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2269 EXT_PHY_RST_CTL, reset_phy,
2270 PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET,
2271 PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET,
2272 PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET,
2273 EE_RST_CTL, EXCLUDE_FROM_RESET,
2274 EXT_PHY_RST_DUR, 0x7 /* 10ms */,
2275 SWRST, 1);
2276 }
2277 falcon_write(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2278
2279 EFX_LOG(efx, "waiting for hardware reset\n");
2280 schedule_timeout_uninterruptible(HZ / 20);
2281
2282 /* Restore PCI configuration if needed */
2283 if (method == RESET_TYPE_WORLD) {
2284 if (FALCON_IS_DUAL_FUNC(efx)) {
2285 rc = pci_restore_state(nic_data->pci_dev2);
2286 if (rc) {
2287 EFX_ERR(efx, "failed to restore PCI config for "
2288 "the secondary function\n");
2289 goto fail3;
2290 }
2291 }
2292 rc = pci_restore_state(efx->pci_dev);
2293 if (rc) {
2294 EFX_ERR(efx, "failed to restore PCI config for the "
2295 "primary function\n");
2296 goto fail4;
2297 }
2298 EFX_LOG(efx, "successfully restored PCI config\n");
2299 }
2300
2301 /* Assert that reset complete */
2302 falcon_read(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2303 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, SWRST) != 0) {
2304 rc = -ETIMEDOUT;
2305 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2306 goto fail5;
2307 }
2308 EFX_LOG(efx, "hardware reset complete\n");
2309
2310 return 0;
2311
2312 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2313fail2:
2314fail3:
2315 pci_restore_state(efx->pci_dev);
2316fail1:
2317fail4:
2318fail5:
2319 return rc;
2320}
2321
2322/* Zeroes out the SRAM contents. This routine must be called in
2323 * process context and is allowed to sleep.
2324 */
2325static int falcon_reset_sram(struct efx_nic *efx)
2326{
2327 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2328 int count;
2329
2330 /* Set the SRAM wake/sleep GPIO appropriately. */
2331 falcon_read(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2332 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OEN, 1);
2333 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OUT, 1);
2334 falcon_write(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2335
2336 /* Initiate SRAM reset */
2337 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2338 SRAM_OOB_BT_INIT_EN, 1,
2339 SRM_NUM_BANKS_AND_BANK_SIZE, 0);
2340 falcon_write(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2341
2342 /* Wait for SRAM reset to complete */
2343 count = 0;
2344 do {
2345 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2346
2347 /* SRAM reset is slow; expect around 16ms */
2348 schedule_timeout_uninterruptible(HZ / 50);
2349
2350 /* Check for reset complete */
2351 falcon_read(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2352 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, SRAM_OOB_BT_INIT_EN)) {
2353 EFX_LOG(efx, "SRAM reset complete\n");
2354
2355 return 0;
2356 }
2357 } while (++count < 20); /* wait upto 0.4 sec */
2358
2359 EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2360 return -ETIMEDOUT;
2361}
2362
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002363static int falcon_spi_device_init(struct efx_nic *efx,
2364 struct efx_spi_device **spi_device_ret,
2365 unsigned int device_id, u32 device_type)
2366{
2367 struct efx_spi_device *spi_device;
2368
2369 if (device_type != 0) {
2370 spi_device = kmalloc(sizeof(*spi_device), GFP_KERNEL);
2371 if (!spi_device)
2372 return -ENOMEM;
2373 spi_device->device_id = device_id;
2374 spi_device->size =
2375 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2376 spi_device->addr_len =
2377 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2378 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2379 spi_device->addr_len == 1);
2380 spi_device->block_size =
2381 1 << SPI_DEV_TYPE_FIELD(device_type,
2382 SPI_DEV_TYPE_BLOCK_SIZE);
2383
2384 spi_device->efx = efx;
2385 } else {
2386 spi_device = NULL;
2387 }
2388
2389 kfree(*spi_device_ret);
2390 *spi_device_ret = spi_device;
2391 return 0;
2392}
2393
2394
2395static void falcon_remove_spi_devices(struct efx_nic *efx)
2396{
2397 kfree(efx->spi_eeprom);
2398 efx->spi_eeprom = NULL;
2399 kfree(efx->spi_flash);
2400 efx->spi_flash = NULL;
2401}
2402
Ben Hutchings8ceee662008-04-27 12:55:59 +01002403/* Extract non-volatile configuration */
2404static int falcon_probe_nvconfig(struct efx_nic *efx)
2405{
2406 struct falcon_nvconfig *nvconfig;
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002407 struct efx_spi_device *spi;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002408 int magic_num, struct_ver, board_rev;
2409 int rc;
2410
Ben Hutchings8ceee662008-04-27 12:55:59 +01002411 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002412 if (!nvconfig)
2413 return -ENOMEM;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002414
2415 /* Read the whole configuration structure into memory. */
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002416 spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
2417 rc = falcon_spi_read(spi, NVCONFIG_BASE, sizeof(*nvconfig),
2418 NULL, (char *)nvconfig);
2419 if (rc) {
2420 EFX_ERR(efx, "Failed to read %s\n", efx->spi_flash ? "flash" :
2421 "EEPROM");
2422 goto fail1;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002423 }
2424
2425 /* Read the MAC addresses */
2426 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2427
2428 /* Read the board configuration. */
2429 magic_num = le16_to_cpu(nvconfig->board_magic_num);
2430 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2431
2432 if (magic_num != NVCONFIG_BOARD_MAGIC_NUM || struct_ver < 2) {
2433 EFX_ERR(efx, "Non volatile memory bad magic=%x ver=%x "
2434 "therefore using defaults\n", magic_num, struct_ver);
2435 efx->phy_type = PHY_TYPE_NONE;
2436 efx->mii.phy_id = PHY_ADDR_INVALID;
2437 board_rev = 0;
2438 } else {
2439 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002440 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002441
2442 efx->phy_type = v2->port0_phy_type;
2443 efx->mii.phy_id = v2->port0_phy_addr;
2444 board_rev = le16_to_cpu(v2->board_revision);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002445
2446 if (struct_ver >= 3) {
2447 __le32 fl = v3->spi_device_type[EE_SPI_FLASH];
2448 __le32 ee = v3->spi_device_type[EE_SPI_EEPROM];
2449 rc = falcon_spi_device_init(efx, &efx->spi_flash,
2450 EE_SPI_FLASH,
2451 le32_to_cpu(fl));
2452 if (rc)
2453 goto fail2;
2454 rc = falcon_spi_device_init(efx, &efx->spi_eeprom,
2455 EE_SPI_EEPROM,
2456 le32_to_cpu(ee));
2457 if (rc)
2458 goto fail2;
2459 }
Ben Hutchings8ceee662008-04-27 12:55:59 +01002460 }
2461
2462 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mii.phy_id);
2463
2464 efx_set_board_info(efx, board_rev);
2465
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002466 kfree(nvconfig);
2467 return 0;
2468
2469 fail2:
2470 falcon_remove_spi_devices(efx);
2471 fail1:
Ben Hutchings8ceee662008-04-27 12:55:59 +01002472 kfree(nvconfig);
2473 return rc;
2474}
2475
2476/* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2477 * count, port speed). Set workaround and feature flags accordingly.
2478 */
2479static int falcon_probe_nic_variant(struct efx_nic *efx)
2480{
2481 efx_oword_t altera_build;
2482
2483 falcon_read(efx, &altera_build, ALTERA_BUILD_REG_KER);
2484 if (EFX_OWORD_FIELD(altera_build, VER_ALL)) {
2485 EFX_ERR(efx, "Falcon FPGA not supported\n");
2486 return -ENODEV;
2487 }
2488
Ben Hutchings55668612008-05-16 21:16:10 +01002489 switch (falcon_rev(efx)) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01002490 case FALCON_REV_A0:
2491 case 0xff:
2492 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2493 return -ENODEV;
2494
2495 case FALCON_REV_A1:{
2496 efx_oword_t nic_stat;
2497
2498 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2499
2500 if (EFX_OWORD_FIELD(nic_stat, STRAP_PCIE) == 0) {
2501 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2502 return -ENODEV;
2503 }
2504 if (!EFX_OWORD_FIELD(nic_stat, STRAP_10G)) {
2505 EFX_ERR(efx, "1G mode not supported\n");
2506 return -ENODEV;
2507 }
2508 break;
2509 }
2510
2511 case FALCON_REV_B0:
2512 break;
2513
2514 default:
Ben Hutchings55668612008-05-16 21:16:10 +01002515 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
Ben Hutchings8ceee662008-04-27 12:55:59 +01002516 return -ENODEV;
2517 }
2518
2519 return 0;
2520}
2521
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002522/* Probe all SPI devices on the NIC */
2523static void falcon_probe_spi_devices(struct efx_nic *efx)
2524{
2525 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2526 bool has_flash, has_eeprom, boot_is_external;
2527
2528 falcon_read(efx, &gpio_ctl, GPIO_CTL_REG_KER);
2529 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2530 falcon_read(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
2531
2532 has_flash = EFX_OWORD_FIELD(nic_stat, SF_PRST);
2533 has_eeprom = EFX_OWORD_FIELD(nic_stat, EE_PRST);
2534 boot_is_external = EFX_OWORD_FIELD(gpio_ctl, BOOTED_USING_NVDEVICE);
2535
2536 if (has_flash) {
2537 /* Default flash SPI device: Atmel AT25F1024
2538 * 128 KB, 24-bit address, 32 KB erase block,
2539 * 256 B write block
2540 */
2541 u32 flash_device_type =
2542 (17 << SPI_DEV_TYPE_SIZE_LBN)
2543 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
2544 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
2545 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
2546 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN);
2547
2548 falcon_spi_device_init(efx, &efx->spi_flash,
2549 EE_SPI_FLASH, flash_device_type);
2550
2551 if (!boot_is_external) {
2552 /* Disable VPD and set clock dividers to safe
2553 * values for initial programming.
2554 */
2555 EFX_LOG(efx, "Booted from internal ASIC settings;"
2556 " setting SPI config\n");
2557 EFX_POPULATE_OWORD_3(ee_vpd_cfg, EE_VPD_EN, 0,
2558 /* 125 MHz / 7 ~= 20 MHz */
2559 EE_SF_CLOCK_DIV, 7,
2560 /* 125 MHz / 63 ~= 2 MHz */
2561 EE_EE_CLOCK_DIV, 63);
2562 falcon_write(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
2563 }
2564 }
2565
2566 if (has_eeprom) {
2567 u32 eeprom_device_type;
2568
2569 /* If it has no flash, it must have a large EEPROM
2570 * for chip config; otherwise check whether 9-bit
2571 * addressing is used for VPD configuration
2572 */
2573 if (has_flash &&
2574 (!boot_is_external ||
2575 EFX_OWORD_FIELD(ee_vpd_cfg, EE_VPD_EN_AD9_MODE))) {
2576 /* Default SPI device: Atmel AT25040 or similar
2577 * 512 B, 9-bit address, 8 B write block
2578 */
2579 eeprom_device_type =
2580 (9 << SPI_DEV_TYPE_SIZE_LBN)
2581 | (1 << SPI_DEV_TYPE_ADDR_LEN_LBN)
2582 | (3 << SPI_DEV_TYPE_BLOCK_SIZE_LBN);
2583 } else {
2584 /* "Large" SPI device: Atmel AT25640 or similar
2585 * 8 KB, 16-bit address, 32 B write block
2586 */
2587 eeprom_device_type =
2588 (13 << SPI_DEV_TYPE_SIZE_LBN)
2589 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
2590 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN);
2591 }
2592
2593 falcon_spi_device_init(efx, &efx->spi_eeprom,
2594 EE_SPI_EEPROM, eeprom_device_type);
2595 }
2596
2597 EFX_LOG(efx, "flash is %s, EEPROM is %s\n",
2598 (has_flash ? "present" : "absent"),
2599 (has_eeprom ? "present" : "absent"));
2600}
2601
Ben Hutchings8ceee662008-04-27 12:55:59 +01002602int falcon_probe_nic(struct efx_nic *efx)
2603{
2604 struct falcon_nic_data *nic_data;
2605 int rc;
2606
Ben Hutchings8ceee662008-04-27 12:55:59 +01002607 /* Allocate storage for hardware specific data */
2608 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
Ben Hutchings5daab962008-05-16 21:19:43 +01002609 efx->nic_data = nic_data;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002610
2611 /* Determine number of ports etc. */
2612 rc = falcon_probe_nic_variant(efx);
2613 if (rc)
2614 goto fail1;
2615
2616 /* Probe secondary function if expected */
2617 if (FALCON_IS_DUAL_FUNC(efx)) {
2618 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2619
2620 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2621 dev))) {
2622 if (dev->bus == efx->pci_dev->bus &&
2623 dev->devfn == efx->pci_dev->devfn + 1) {
2624 nic_data->pci_dev2 = dev;
2625 break;
2626 }
2627 }
2628 if (!nic_data->pci_dev2) {
2629 EFX_ERR(efx, "failed to find secondary function\n");
2630 rc = -ENODEV;
2631 goto fail2;
2632 }
2633 }
2634
2635 /* Now we can reset the NIC */
2636 rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2637 if (rc) {
2638 EFX_ERR(efx, "failed to reset NIC\n");
2639 goto fail3;
2640 }
2641
2642 /* Allocate memory for INT_KER */
2643 rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2644 if (rc)
2645 goto fail4;
2646 BUG_ON(efx->irq_status.dma_addr & 0x0f);
2647
2648 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %lx)\n",
2649 (unsigned long long)efx->irq_status.dma_addr,
2650 efx->irq_status.addr, virt_to_phys(efx->irq_status.addr));
2651
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002652 falcon_probe_spi_devices(efx);
2653
Ben Hutchings8ceee662008-04-27 12:55:59 +01002654 /* Read in the non-volatile configuration */
2655 rc = falcon_probe_nvconfig(efx);
2656 if (rc)
2657 goto fail5;
2658
Ben Hutchings37b5a602008-05-30 22:27:04 +01002659 /* Initialise I2C adapter */
2660 efx->i2c_adap.owner = THIS_MODULE;
Ben Hutchings37b5a602008-05-30 22:27:04 +01002661 nic_data->i2c_data = falcon_i2c_bit_operations;
2662 nic_data->i2c_data.data = efx;
2663 efx->i2c_adap.algo_data = &nic_data->i2c_data;
2664 efx->i2c_adap.dev.parent = &efx->pci_dev->dev;
Ben Hutchings9dadae62008-07-18 18:59:12 +01002665 strlcpy(efx->i2c_adap.name, "SFC4000 GPIO", sizeof(efx->i2c_adap.name));
Ben Hutchings37b5a602008-05-30 22:27:04 +01002666 rc = i2c_bit_add_bus(&efx->i2c_adap);
2667 if (rc)
2668 goto fail5;
2669
Ben Hutchings8ceee662008-04-27 12:55:59 +01002670 return 0;
2671
2672 fail5:
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002673 falcon_remove_spi_devices(efx);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002674 falcon_free_buffer(efx, &efx->irq_status);
2675 fail4:
Ben Hutchings8ceee662008-04-27 12:55:59 +01002676 fail3:
2677 if (nic_data->pci_dev2) {
2678 pci_dev_put(nic_data->pci_dev2);
2679 nic_data->pci_dev2 = NULL;
2680 }
2681 fail2:
Ben Hutchings8ceee662008-04-27 12:55:59 +01002682 fail1:
2683 kfree(efx->nic_data);
2684 return rc;
2685}
2686
2687/* This call performs hardware-specific global initialisation, such as
2688 * defining the descriptor cache sizes and number of RSS channels.
2689 * It does not set up any buffers, descriptor rings or event queues.
2690 */
2691int falcon_init_nic(struct efx_nic *efx)
2692{
Ben Hutchings8ceee662008-04-27 12:55:59 +01002693 efx_oword_t temp;
2694 unsigned thresh;
2695 int rc;
2696
Ben Hutchings8ceee662008-04-27 12:55:59 +01002697 /* Set up the address region register. This is only needed
2698 * for the B0 FPGA, but since we are just pushing in the
2699 * reset defaults this may as well be unconditional. */
2700 EFX_POPULATE_OWORD_4(temp, ADR_REGION0, 0,
2701 ADR_REGION1, (1 << 16),
2702 ADR_REGION2, (2 << 16),
2703 ADR_REGION3, (3 << 16));
2704 falcon_write(efx, &temp, ADR_REGION_REG_KER);
2705
2706 /* Use on-chip SRAM */
2707 falcon_read(efx, &temp, NIC_STAT_REG);
2708 EFX_SET_OWORD_FIELD(temp, ONCHIP_SRAM, 1);
2709 falcon_write(efx, &temp, NIC_STAT_REG);
2710
2711 /* Set buffer table mode */
2712 EFX_POPULATE_OWORD_1(temp, BUF_TBL_MODE, BUF_TBL_MODE_FULL);
2713 falcon_write(efx, &temp, BUF_TBL_CFG_REG_KER);
2714
2715 rc = falcon_reset_sram(efx);
2716 if (rc)
2717 return rc;
2718
2719 /* Set positions of descriptor caches in SRAM. */
2720 EFX_POPULATE_OWORD_1(temp, SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
2721 falcon_write(efx, &temp, SRM_TX_DC_CFG_REG_KER);
2722 EFX_POPULATE_OWORD_1(temp, SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
2723 falcon_write(efx, &temp, SRM_RX_DC_CFG_REG_KER);
2724
2725 /* Set TX descriptor cache size. */
2726 BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
2727 EFX_POPULATE_OWORD_1(temp, TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
2728 falcon_write(efx, &temp, TX_DC_CFG_REG_KER);
2729
2730 /* Set RX descriptor cache size. Set low watermark to size-8, as
2731 * this allows most efficient prefetching.
2732 */
2733 BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
2734 EFX_POPULATE_OWORD_1(temp, RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
2735 falcon_write(efx, &temp, RX_DC_CFG_REG_KER);
2736 EFX_POPULATE_OWORD_1(temp, RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
2737 falcon_write(efx, &temp, RX_DC_PF_WM_REG_KER);
2738
2739 /* Clear the parity enables on the TX data fifos as
2740 * they produce false parity errors because of timing issues
2741 */
2742 if (EFX_WORKAROUND_5129(efx)) {
2743 falcon_read(efx, &temp, SPARE_REG_KER);
2744 EFX_SET_OWORD_FIELD(temp, MEM_PERR_EN_TX_DATA, 0);
2745 falcon_write(efx, &temp, SPARE_REG_KER);
2746 }
2747
2748 /* Enable all the genuinely fatal interrupts. (They are still
2749 * masked by the overall interrupt mask, controlled by
2750 * falcon_interrupts()).
2751 *
2752 * Note: All other fatal interrupts are enabled
2753 */
2754 EFX_POPULATE_OWORD_3(temp,
2755 ILL_ADR_INT_KER_EN, 1,
2756 RBUF_OWN_INT_KER_EN, 1,
2757 TBUF_OWN_INT_KER_EN, 1);
2758 EFX_INVERT_OWORD(temp);
2759 falcon_write(efx, &temp, FATAL_INTR_REG_KER);
2760
Ben Hutchings8ceee662008-04-27 12:55:59 +01002761 if (EFX_WORKAROUND_7244(efx)) {
Ben Hutchings955f0a72008-09-01 12:47:52 +01002762 falcon_read(efx, &temp, RX_FILTER_CTL_REG);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002763 EFX_SET_OWORD_FIELD(temp, UDP_FULL_SRCH_LIMIT, 8);
2764 EFX_SET_OWORD_FIELD(temp, UDP_WILD_SRCH_LIMIT, 8);
2765 EFX_SET_OWORD_FIELD(temp, TCP_FULL_SRCH_LIMIT, 8);
2766 EFX_SET_OWORD_FIELD(temp, TCP_WILD_SRCH_LIMIT, 8);
Ben Hutchings955f0a72008-09-01 12:47:52 +01002767 falcon_write(efx, &temp, RX_FILTER_CTL_REG);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002768 }
Ben Hutchings8ceee662008-04-27 12:55:59 +01002769
2770 falcon_setup_rss_indir_table(efx);
2771
2772 /* Setup RX. Wait for descriptor is broken and must
2773 * be disabled. RXDP recovery shouldn't be needed, but is.
2774 */
2775 falcon_read(efx, &temp, RX_SELF_RST_REG_KER);
2776 EFX_SET_OWORD_FIELD(temp, RX_NODESC_WAIT_DIS, 1);
2777 EFX_SET_OWORD_FIELD(temp, RX_RECOVERY_EN, 1);
2778 if (EFX_WORKAROUND_5583(efx))
2779 EFX_SET_OWORD_FIELD(temp, RX_ISCSI_DIS, 1);
2780 falcon_write(efx, &temp, RX_SELF_RST_REG_KER);
2781
2782 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
2783 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
2784 */
2785 falcon_read(efx, &temp, TX_CFG2_REG_KER);
2786 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER, 0xfe);
2787 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER_EN, 1);
2788 EFX_SET_OWORD_FIELD(temp, TX_ONE_PKT_PER_Q, 1);
2789 EFX_SET_OWORD_FIELD(temp, TX_CSR_PUSH_EN, 0);
2790 EFX_SET_OWORD_FIELD(temp, TX_DIS_NON_IP_EV, 1);
2791 /* Enable SW_EV to inherit in char driver - assume harmless here */
2792 EFX_SET_OWORD_FIELD(temp, TX_SW_EV_EN, 1);
2793 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
2794 EFX_SET_OWORD_FIELD(temp, TX_PREF_THRESHOLD, 2);
2795 /* Squash TX of packets of 16 bytes or less */
Ben Hutchings55668612008-05-16 21:16:10 +01002796 if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
Ben Hutchings8ceee662008-04-27 12:55:59 +01002797 EFX_SET_OWORD_FIELD(temp, TX_FLUSH_MIN_LEN_EN_B0, 1);
2798 falcon_write(efx, &temp, TX_CFG2_REG_KER);
2799
2800 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
2801 * descriptors (which is bad).
2802 */
2803 falcon_read(efx, &temp, TX_CFG_REG_KER);
2804 EFX_SET_OWORD_FIELD(temp, TX_NO_EOP_DISC_EN, 0);
2805 falcon_write(efx, &temp, TX_CFG_REG_KER);
2806
2807 /* RX config */
2808 falcon_read(efx, &temp, RX_CFG_REG_KER);
2809 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_DESC_PUSH_EN, 0);
2810 if (EFX_WORKAROUND_7575(efx))
2811 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_USR_BUF_SIZE,
2812 (3 * 4096) / 32);
Ben Hutchings55668612008-05-16 21:16:10 +01002813 if (falcon_rev(efx) >= FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +01002814 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 1);
2815
2816 /* RX FIFO flow control thresholds */
2817 thresh = ((rx_xon_thresh_bytes >= 0) ?
2818 rx_xon_thresh_bytes : efx->type->rx_xon_thresh);
2819 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_MAC_TH, thresh / 256);
2820 thresh = ((rx_xoff_thresh_bytes >= 0) ?
2821 rx_xoff_thresh_bytes : efx->type->rx_xoff_thresh);
2822 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_MAC_TH, thresh / 256);
2823 /* RX control FIFO thresholds [32 entries] */
Ben Hutchingsc84a6f12008-09-01 12:46:21 +01002824 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_TX_TH, 20);
2825 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_TX_TH, 25);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002826 falcon_write(efx, &temp, RX_CFG_REG_KER);
2827
2828 /* Set destination of both TX and RX Flush events */
Ben Hutchings55668612008-05-16 21:16:10 +01002829 if (falcon_rev(efx) >= FALCON_REV_B0) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01002830 EFX_POPULATE_OWORD_1(temp, FLS_EVQ_ID, 0);
2831 falcon_write(efx, &temp, DP_CTRL_REG);
2832 }
2833
2834 return 0;
2835}
2836
2837void falcon_remove_nic(struct efx_nic *efx)
2838{
2839 struct falcon_nic_data *nic_data = efx->nic_data;
Ben Hutchings37b5a602008-05-30 22:27:04 +01002840 int rc;
2841
2842 rc = i2c_del_adapter(&efx->i2c_adap);
2843 BUG_ON(rc);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002844
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002845 falcon_remove_spi_devices(efx);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002846 falcon_free_buffer(efx, &efx->irq_status);
2847
Ben Hutchings91ad7572008-05-16 21:14:27 +01002848 falcon_reset_hw(efx, RESET_TYPE_ALL);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002849
2850 /* Release the second function after the reset */
2851 if (nic_data->pci_dev2) {
2852 pci_dev_put(nic_data->pci_dev2);
2853 nic_data->pci_dev2 = NULL;
2854 }
2855
2856 /* Tear down the private nic state */
2857 kfree(efx->nic_data);
2858 efx->nic_data = NULL;
2859}
2860
2861void falcon_update_nic_stats(struct efx_nic *efx)
2862{
2863 efx_oword_t cnt;
2864
2865 falcon_read(efx, &cnt, RX_NODESC_DROP_REG_KER);
2866 efx->n_rx_nodesc_drop_cnt += EFX_OWORD_FIELD(cnt, RX_NODESC_DROP_CNT);
2867}
2868
2869/**************************************************************************
2870 *
2871 * Revision-dependent attributes used by efx.c
2872 *
2873 **************************************************************************
2874 */
2875
2876struct efx_nic_type falcon_a_nic_type = {
2877 .mem_bar = 2,
2878 .mem_map_size = 0x20000,
2879 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_A1,
2880 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_A1,
2881 .buf_tbl_base = BUF_TBL_KER_A1,
2882 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_A1,
2883 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_A1,
2884 .txd_ring_mask = FALCON_TXD_RING_MASK,
2885 .rxd_ring_mask = FALCON_RXD_RING_MASK,
2886 .evq_size = FALCON_EVQ_SIZE,
2887 .max_dma_mask = FALCON_DMA_MASK,
2888 .tx_dma_mask = FALCON_TX_DMA_MASK,
2889 .bug5391_mask = 0xf,
2890 .rx_xoff_thresh = 2048,
2891 .rx_xon_thresh = 512,
2892 .rx_buffer_padding = 0x24,
2893 .max_interrupt_mode = EFX_INT_MODE_MSI,
2894 .phys_addr_channels = 4,
2895};
2896
2897struct efx_nic_type falcon_b_nic_type = {
2898 .mem_bar = 2,
2899 /* Map everything up to and including the RSS indirection
2900 * table. Don't map MSI-X table, MSI-X PBA since Linux
2901 * requires that they not be mapped. */
2902 .mem_map_size = RX_RSS_INDIR_TBL_B0 + 0x800,
2903 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_B0,
2904 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_B0,
2905 .buf_tbl_base = BUF_TBL_KER_B0,
2906 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_B0,
2907 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_B0,
2908 .txd_ring_mask = FALCON_TXD_RING_MASK,
2909 .rxd_ring_mask = FALCON_RXD_RING_MASK,
2910 .evq_size = FALCON_EVQ_SIZE,
2911 .max_dma_mask = FALCON_DMA_MASK,
2912 .tx_dma_mask = FALCON_TX_DMA_MASK,
2913 .bug5391_mask = 0,
2914 .rx_xoff_thresh = 54272, /* ~80Kb - 3*max MTU */
2915 .rx_xon_thresh = 27648, /* ~3*max MTU */
2916 .rx_buffer_padding = 0,
2917 .max_interrupt_mode = EFX_INT_MODE_MSIX,
2918 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
2919 * interrupt handler only supports 32
2920 * channels */
2921};
2922