| Sandeep Patil | ddbf565 | 2008-10-21 14:06:23 +0100 | [diff] [blame] | 1 | /* linux/arch/arm/mach-s3c24a0/include/mach/regs-clock.h |
| 2 | * |
| Ben Dooks | e02f866 | 2009-11-13 22:54:13 +0000 | [diff] [blame] | 3 | * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk> |
| 4 | * http://armlinux.simtec.co.uk/ |
| Sandeep Patil | ddbf565 | 2008-10-21 14:06:23 +0100 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * S3C24A0 clock register definitions |
| 11 | */ |
| 12 | |
| 13 | #ifndef __ASM_ARCH_24A0_REGS_CLOCK_H |
| 14 | #define __ASM_ARCH_24A0_REGS_CLOCK_H __FILE__ |
| 15 | |
| 16 | #define S3C24A0_MPLLCON S3C2410_CLKREG(0x10) |
| 17 | #define S3C24A0_UPLLCON S3C2410_CLKREG(0x14) |
| 18 | #define S3C24A0_CLKCON S3C2410_CLKREG(0x20) |
| 19 | #define S3C24A0_CLKSRC S3C2410_CLKREG(0x24) |
| 20 | #define S3C24A0_CLKDIVN S3C2410_CLKREG(0x28) |
| 21 | |
| 22 | /* CLKCON register bits */ |
| 23 | |
| 24 | #define S3C24A0_CLKCON_VLX (1<<29) |
| 25 | #define S3C24A0_CLKCON_VPOST (1<<28) |
| 26 | #define S3C24A0_CLKCON_WDT (1<<27) /* reserved */ |
| 27 | #define S3C24A0_CLKCON_MPEGDCTQ (1<<26) |
| 28 | #define S3C24A0_CLKCON_VPOSTIF (1<<25) |
| 29 | #define S3C24A0_CLKCON_MPEG4IF (1<<24) |
| 30 | #define S3C24A0_CLKCON_CAM_UPLL (1<<23) |
| 31 | #define S3C24A0_CLKCON_LCDC (1<<22) |
| 32 | #define S3C24A0_CLKCON_CAM_HCLK (1<<21) |
| 33 | #define S3C24A0_CLKCON_MPEG4 (1<<20) |
| 34 | #define S3C24A0_CLKCON_KEYPAD (1<<19) |
| 35 | #define S3C24A0_CLKCON_ADC (1<<18) |
| 36 | #define S3C24A0_CLKCON_SDI (1<<17) |
| 37 | #define S3C24A0_CLKCON_MS (1<<16) /* memory stick */ |
| 38 | #define S3C24A0_CLKCON_USBD (1<<15) |
| 39 | #define S3C24A0_CLKCON_GPIO (1<<14) |
| 40 | #define S3C24A0_CLKCON_IIS (1<<13) |
| 41 | #define S3C24A0_CLKCON_IIC (1<<12) |
| 42 | #define S3C24A0_CLKCON_SPI (1<<11) |
| 43 | #define S3C24A0_CLKCON_UART1 (1<<10) |
| 44 | #define S3C24A0_CLKCON_UART0 (1<<9) |
| 45 | #define S3C24A0_CLKCON_PWMT (1<<8) |
| 46 | #define S3C24A0_CLKCON_USBH (1<<7) |
| 47 | #define S3C24A0_CLKCON_AC97 (1<<6) |
| 48 | #define S3C24A0_CLKCON_IrDA (1<<4) |
| 49 | #define S3C24A0_CLKCON_IDLE (1<<2) |
| 50 | #define S3C24A0_CLKCON_MON (1<<1) |
| 51 | #define S3C24A0_CLKCON_STOP (1<<0) |
| 52 | |
| 53 | /* CLKSRC register bits */ |
| 54 | |
| 55 | #define S3C24A0_CLKSRC_OSC (1<<8) /* CLKSRC */ |
| 56 | #define S3C24A0_CLKSRC_UPLL (1<<7) |
| 57 | #define S3C24A0_CLKSRC_MPLL (1<<5) |
| 58 | #define S3C24A0_CLKSRC_EXT (1<<4) |
| 59 | |
| 60 | /* Use a single interface with the common code, for s3c24xx */ |
| 61 | |
| 62 | #define S3C2410_MPLLCON S3C24A0_MPLLCON |
| 63 | #define S3C2410_UPLLCON S3C24A0_UPLLCON |
| 64 | #define S3C2410_CLKCON S3C24A0_CLKCON |
| 65 | #define S3C2410_CLKSLOW S3C24A0_CLKSRC |
| 66 | #define S3C2410_CLKDIVN S3C24A0_CLKDIVN |
| 67 | |
| 68 | #define S3C2410_CLKCON_IDLE S3C24A0_CLKCON_IDLE |
| 69 | #define S3C2410_CLKCON_POWER S3C24A0_CLKCON_STOP |
| 70 | #define S3C2410_CLKCON_LCDC S3C24A0_CLKCON_LCDC |
| 71 | #define S3C2410_CLKCON_USBH S3C24A0_CLKCON_USBH |
| 72 | #define S3C2410_CLKCON_USBD S3C24A0_CLKCON_USBD |
| 73 | #define S3C2410_CLKCON_PWMT S3C24A0_CLKCON_PWMT |
| 74 | #define S3C2410_CLKCON_SDI S3C24A0_CLKCON_SDI |
| 75 | #define S3C2410_CLKCON_UART0 S3C24A0_CLKCON_UART0 |
| 76 | #define S3C2410_CLKCON_UART1 S3C24A0_CLKCON_UART1 |
| 77 | #define S3C2410_CLKCON_GPIO S3C24A0_CLKCON_GPIO |
| 78 | #define S3C2410_CLKCON_ADC S3C24A0_CLKCON_ADC |
| 79 | #define S3C2410_CLKCON_IIC S3C24A0_CLKCON_IIC |
| 80 | #define S3C2410_CLKCON_IIS S3C24A0_CLKCON_IIS |
| 81 | #define S3C2410_CLKCON_SPI S3C24A0_CLKCON_SPI |
| 82 | |
| 83 | #define S3C2410_CLKSLOW_UCLK_OFF S3C24A0_CLKSRC_UPLL |
| 84 | #define S3C2410_CLKSLOW_MPLL_OFF S3C24A0_CLKSRC_MPLL |
| 85 | #define S3C2410_CLKSLOW_SLOW (0xFF) |
| 86 | #define S3C2410_CLKSLOW_GET_SLOWVAL(x) (0x1) |
| 87 | |
| 88 | #endif /* __ASM_ARCH_24A0_REGS_CLOCK_H */ |