Ian Minett | bcd109c | 2012-09-20 20:29:14 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * HD audio interface patch for Creative CA0132 chip. |
| 3 | * CA0132 registers defines. |
| 4 | * |
| 5 | * Copyright (c) 2011, Creative Technology Ltd. |
| 6 | * |
| 7 | * This driver is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This driver is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 20 | */ |
| 21 | |
| 22 | #ifndef __CA0132_REGS_H |
| 23 | #define __CA0312_REGS_H |
| 24 | |
| 25 | #define DSP_CHIP_OFFSET 0x100000 |
| 26 | #define DSP_DBGCNTL_MODULE_OFFSET 0xE30 |
| 27 | #define DSP_DBGCNTL_INST_OFFSET \ |
| 28 | (DSP_CHIP_OFFSET + DSP_DBGCNTL_MODULE_OFFSET) |
| 29 | |
| 30 | #define DSP_DBGCNTL_EXEC_LOBIT 0x0 |
| 31 | #define DSP_DBGCNTL_EXEC_HIBIT 0x3 |
| 32 | #define DSP_DBGCNTL_EXEC_MASK 0xF |
| 33 | |
| 34 | #define DSP_DBGCNTL_SS_LOBIT 0x4 |
| 35 | #define DSP_DBGCNTL_SS_HIBIT 0x7 |
| 36 | #define DSP_DBGCNTL_SS_MASK 0xF0 |
| 37 | |
| 38 | #define DSP_DBGCNTL_STATE_LOBIT 0xA |
| 39 | #define DSP_DBGCNTL_STATE_HIBIT 0xD |
| 40 | #define DSP_DBGCNTL_STATE_MASK 0x3C00 |
| 41 | |
| 42 | #define XRAM_CHIP_OFFSET 0x0 |
| 43 | #define XRAM_XRAM_CHANNEL_COUNT 0xE000 |
| 44 | #define XRAM_XRAM_MODULE_OFFSET 0x0 |
| 45 | #define XRAM_XRAM_CHAN_INCR 4 |
| 46 | #define XRAM_XRAM_INST_OFFSET(_chan) \ |
| 47 | (XRAM_CHIP_OFFSET + XRAM_XRAM_MODULE_OFFSET + \ |
| 48 | (_chan * XRAM_XRAM_CHAN_INCR)) |
| 49 | |
| 50 | #define YRAM_CHIP_OFFSET 0x40000 |
| 51 | #define YRAM_YRAM_CHANNEL_COUNT 0x8000 |
| 52 | #define YRAM_YRAM_MODULE_OFFSET 0x0 |
| 53 | #define YRAM_YRAM_CHAN_INCR 4 |
| 54 | #define YRAM_YRAM_INST_OFFSET(_chan) \ |
| 55 | (YRAM_CHIP_OFFSET + YRAM_YRAM_MODULE_OFFSET + \ |
| 56 | (_chan * YRAM_YRAM_CHAN_INCR)) |
| 57 | |
| 58 | #define UC_CHIP_OFFSET 0x80000 |
| 59 | #define UC_UC_CHANNEL_COUNT 0x10000 |
| 60 | #define UC_UC_MODULE_OFFSET 0x0 |
| 61 | #define UC_UC_CHAN_INCR 4 |
| 62 | #define UC_UC_INST_OFFSET(_chan) \ |
| 63 | (UC_CHIP_OFFSET + UC_UC_MODULE_OFFSET + \ |
| 64 | (_chan * UC_UC_CHAN_INCR)) |
| 65 | |
| 66 | #define AXRAM_CHIP_OFFSET 0x3C000 |
| 67 | #define AXRAM_AXRAM_CHANNEL_COUNT 0x1000 |
| 68 | #define AXRAM_AXRAM_MODULE_OFFSET 0x0 |
| 69 | #define AXRAM_AXRAM_CHAN_INCR 4 |
| 70 | #define AXRAM_AXRAM_INST_OFFSET(_chan) \ |
| 71 | (AXRAM_CHIP_OFFSET + AXRAM_AXRAM_MODULE_OFFSET + \ |
| 72 | (_chan * AXRAM_AXRAM_CHAN_INCR)) |
| 73 | |
| 74 | #define AYRAM_CHIP_OFFSET 0x78000 |
| 75 | #define AYRAM_AYRAM_CHANNEL_COUNT 0x1000 |
| 76 | #define AYRAM_AYRAM_MODULE_OFFSET 0x0 |
| 77 | #define AYRAM_AYRAM_CHAN_INCR 4 |
| 78 | #define AYRAM_AYRAM_INST_OFFSET(_chan) \ |
| 79 | (AYRAM_CHIP_OFFSET + AYRAM_AYRAM_MODULE_OFFSET + \ |
| 80 | (_chan * AYRAM_AYRAM_CHAN_INCR)) |
| 81 | |
| 82 | #define DSPDMAC_CHIP_OFFSET 0x110000 |
| 83 | #define DSPDMAC_DMA_CFG_CHANNEL_COUNT 12 |
| 84 | #define DSPDMAC_DMACFG_MODULE_OFFSET 0xF00 |
| 85 | #define DSPDMAC_DMACFG_CHAN_INCR 0x10 |
| 86 | #define DSPDMAC_DMACFG_INST_OFFSET(_chan) \ |
| 87 | (DSPDMAC_CHIP_OFFSET + DSPDMAC_DMACFG_MODULE_OFFSET + \ |
| 88 | (_chan * DSPDMAC_DMACFG_CHAN_INCR)) |
| 89 | |
| 90 | #define DSPDMAC_DMACFG_DBADR_LOBIT 0x0 |
| 91 | #define DSPDMAC_DMACFG_DBADR_HIBIT 0x10 |
| 92 | #define DSPDMAC_DMACFG_DBADR_MASK 0x1FFFF |
| 93 | #define DSPDMAC_DMACFG_LP_LOBIT 0x11 |
| 94 | #define DSPDMAC_DMACFG_LP_HIBIT 0x11 |
| 95 | #define DSPDMAC_DMACFG_LP_MASK 0x20000 |
| 96 | |
| 97 | #define DSPDMAC_DMACFG_AINCR_LOBIT 0x12 |
| 98 | #define DSPDMAC_DMACFG_AINCR_HIBIT 0x12 |
| 99 | #define DSPDMAC_DMACFG_AINCR_MASK 0x40000 |
| 100 | |
| 101 | #define DSPDMAC_DMACFG_DWR_LOBIT 0x13 |
| 102 | #define DSPDMAC_DMACFG_DWR_HIBIT 0x13 |
| 103 | #define DSPDMAC_DMACFG_DWR_MASK 0x80000 |
| 104 | |
| 105 | #define DSPDMAC_DMACFG_AJUMP_LOBIT 0x14 |
| 106 | #define DSPDMAC_DMACFG_AJUMP_HIBIT 0x17 |
| 107 | #define DSPDMAC_DMACFG_AJUMP_MASK 0xF00000 |
| 108 | |
| 109 | #define DSPDMAC_DMACFG_AMODE_LOBIT 0x18 |
| 110 | #define DSPDMAC_DMACFG_AMODE_HIBIT 0x19 |
| 111 | #define DSPDMAC_DMACFG_AMODE_MASK 0x3000000 |
| 112 | |
| 113 | #define DSPDMAC_DMACFG_LK_LOBIT 0x1A |
| 114 | #define DSPDMAC_DMACFG_LK_HIBIT 0x1A |
| 115 | #define DSPDMAC_DMACFG_LK_MASK 0x4000000 |
| 116 | |
| 117 | #define DSPDMAC_DMACFG_AICS_LOBIT 0x1B |
| 118 | #define DSPDMAC_DMACFG_AICS_HIBIT 0x1F |
| 119 | #define DSPDMAC_DMACFG_AICS_MASK 0xF8000000 |
| 120 | |
| 121 | #define DSPDMAC_DMACFG_LP_SINGLE 0 |
| 122 | #define DSPDMAC_DMACFG_LP_LOOPING 1 |
| 123 | |
| 124 | #define DSPDMAC_DMACFG_AINCR_XANDY 0 |
| 125 | #define DSPDMAC_DMACFG_AINCR_XORY 1 |
| 126 | |
| 127 | #define DSPDMAC_DMACFG_DWR_DMA_RD 0 |
| 128 | #define DSPDMAC_DMACFG_DWR_DMA_WR 1 |
| 129 | |
| 130 | #define DSPDMAC_DMACFG_AMODE_LINEAR 0 |
| 131 | #define DSPDMAC_DMACFG_AMODE_RSV1 1 |
| 132 | #define DSPDMAC_DMACFG_AMODE_WINTLV 2 |
| 133 | #define DSPDMAC_DMACFG_AMODE_GINTLV 3 |
| 134 | |
| 135 | #define DSPDMAC_DSP_ADR_OFS_CHANNEL_COUNT 12 |
| 136 | #define DSPDMAC_DSPADROFS_MODULE_OFFSET 0xF04 |
| 137 | #define DSPDMAC_DSPADROFS_CHAN_INCR 0x10 |
| 138 | #define DSPDMAC_DSPADROFS_INST_OFFSET(_chan) \ |
| 139 | (DSPDMAC_CHIP_OFFSET + DSPDMAC_DSPADROFS_MODULE_OFFSET + \ |
| 140 | (_chan * DSPDMAC_DSPADROFS_CHAN_INCR)) |
| 141 | |
| 142 | #define DSPDMAC_DSPADROFS_COFS_LOBIT 0x0 |
| 143 | #define DSPDMAC_DSPADROFS_COFS_HIBIT 0xF |
| 144 | #define DSPDMAC_DSPADROFS_COFS_MASK 0xFFFF |
| 145 | |
| 146 | #define DSPDMAC_DSPADROFS_BOFS_LOBIT 0x10 |
| 147 | #define DSPDMAC_DSPADROFS_BOFS_HIBIT 0x1F |
| 148 | #define DSPDMAC_DSPADROFS_BOFS_MASK 0xFFFF0000 |
| 149 | |
| 150 | #define DSPDMAC_DSP_ADR_WOFS_CHANNEL_COUNT 12 |
| 151 | #define DSPDMAC_DSPADRWOFS_MODULE_OFFSET 0xF04 |
| 152 | #define DSPDMAC_DSPADRWOFS_CHAN_INCR 0x10 |
| 153 | |
| 154 | #define DSPDMAC_DSPADRWOFS_INST_OFFSET(_chan) \ |
| 155 | (DSPDMAC_CHIP_OFFSET + DSPDMAC_DSPADRWOFS_MODULE_OFFSET + \ |
| 156 | (_chan * DSPDMAC_DSPADRWOFS_CHAN_INCR)) |
| 157 | |
| 158 | #define DSPDMAC_DSPADRWOFS_WCOFS_LOBIT 0x0 |
| 159 | #define DSPDMAC_DSPADRWOFS_WCOFS_HIBIT 0xA |
| 160 | #define DSPDMAC_DSPADRWOFS_WCOFS_MASK 0x7FF |
| 161 | |
| 162 | #define DSPDMAC_DSPADRWOFS_WCBFR_LOBIT 0xB |
| 163 | #define DSPDMAC_DSPADRWOFS_WCBFR_HIBIT 0xF |
| 164 | #define DSPDMAC_DSPADRWOFS_WCBFR_MASK 0xF800 |
| 165 | |
| 166 | #define DSPDMAC_DSPADRWOFS_WBOFS_LOBIT 0x10 |
| 167 | #define DSPDMAC_DSPADRWOFS_WBOFS_HIBIT 0x1A |
| 168 | #define DSPDMAC_DSPADRWOFS_WBOFS_MASK 0x7FF0000 |
| 169 | |
| 170 | #define DSPDMAC_DSPADRWOFS_WBBFR_LOBIT 0x1B |
| 171 | #define DSPDMAC_DSPADRWOFS_WBBFR_HIBIT 0x1F |
| 172 | #define DSPDMAC_DSPADRWOFS_WBBFR_MASK 0xF8000000 |
| 173 | |
| 174 | #define DSPDMAC_DSP_ADR_GOFS_CHANNEL_COUNT 12 |
| 175 | #define DSPDMAC_DSPADRGOFS_MODULE_OFFSET 0xF04 |
| 176 | #define DSPDMAC_DSPADRGOFS_CHAN_INCR 0x10 |
| 177 | #define DSPDMAC_DSPADRGOFS_INST_OFFSET(_chan) \ |
| 178 | (DSPDMAC_CHIP_OFFSET + DSPDMAC_DSPADRGOFS_MODULE_OFFSET + \ |
| 179 | (_chan * DSPDMAC_DSPADRGOFS_CHAN_INCR)) |
| 180 | |
| 181 | #define DSPDMAC_DSPADRGOFS_GCOFS_LOBIT 0x0 |
| 182 | #define DSPDMAC_DSPADRGOFS_GCOFS_HIBIT 0x9 |
| 183 | #define DSPDMAC_DSPADRGOFS_GCOFS_MASK 0x3FF |
| 184 | |
| 185 | #define DSPDMAC_DSPADRGOFS_GCS_LOBIT 0xA |
| 186 | #define DSPDMAC_DSPADRGOFS_GCS_HIBIT 0xC |
| 187 | #define DSPDMAC_DSPADRGOFS_GCS_MASK 0x1C00 |
| 188 | |
| 189 | #define DSPDMAC_DSPADRGOFS_GCBFR_LOBIT 0xD |
| 190 | #define DSPDMAC_DSPADRGOFS_GCBFR_HIBIT 0xF |
| 191 | #define DSPDMAC_DSPADRGOFS_GCBFR_MASK 0xE000 |
| 192 | |
| 193 | #define DSPDMAC_DSPADRGOFS_GBOFS_LOBIT 0x10 |
| 194 | #define DSPDMAC_DSPADRGOFS_GBOFS_HIBIT 0x19 |
| 195 | #define DSPDMAC_DSPADRGOFS_GBOFS_MASK 0x3FF0000 |
| 196 | |
| 197 | #define DSPDMAC_DSPADRGOFS_GBS_LOBIT 0x1A |
| 198 | #define DSPDMAC_DSPADRGOFS_GBS_HIBIT 0x1C |
| 199 | #define DSPDMAC_DSPADRGOFS_GBS_MASK 0x1C000000 |
| 200 | |
| 201 | #define DSPDMAC_DSPADRGOFS_GBBFR_LOBIT 0x1D |
| 202 | #define DSPDMAC_DSPADRGOFS_GBBFR_HIBIT 0x1F |
| 203 | #define DSPDMAC_DSPADRGOFS_GBBFR_MASK 0xE0000000 |
| 204 | |
| 205 | #define DSPDMAC_XFR_CNT_CHANNEL_COUNT 12 |
| 206 | #define DSPDMAC_XFRCNT_MODULE_OFFSET 0xF08 |
| 207 | #define DSPDMAC_XFRCNT_CHAN_INCR 0x10 |
| 208 | |
| 209 | #define DSPDMAC_XFRCNT_INST_OFFSET(_chan) \ |
| 210 | (DSPDMAC_CHIP_OFFSET + DSPDMAC_XFRCNT_MODULE_OFFSET + \ |
| 211 | (_chan * DSPDMAC_XFRCNT_CHAN_INCR)) |
| 212 | |
| 213 | #define DSPDMAC_XFRCNT_CCNT_LOBIT 0x0 |
| 214 | #define DSPDMAC_XFRCNT_CCNT_HIBIT 0xF |
| 215 | #define DSPDMAC_XFRCNT_CCNT_MASK 0xFFFF |
| 216 | |
| 217 | #define DSPDMAC_XFRCNT_BCNT_LOBIT 0x10 |
| 218 | #define DSPDMAC_XFRCNT_BCNT_HIBIT 0x1F |
| 219 | #define DSPDMAC_XFRCNT_BCNT_MASK 0xFFFF0000 |
| 220 | |
| 221 | #define DSPDMAC_IRQ_CNT_CHANNEL_COUNT 12 |
| 222 | #define DSPDMAC_IRQCNT_MODULE_OFFSET 0xF0C |
| 223 | #define DSPDMAC_IRQCNT_CHAN_INCR 0x10 |
| 224 | #define DSPDMAC_IRQCNT_INST_OFFSET(_chan) \ |
| 225 | (DSPDMAC_CHIP_OFFSET + DSPDMAC_IRQCNT_MODULE_OFFSET + \ |
| 226 | (_chan * DSPDMAC_IRQCNT_CHAN_INCR)) |
| 227 | |
| 228 | #define DSPDMAC_IRQCNT_CICNT_LOBIT 0x0 |
| 229 | #define DSPDMAC_IRQCNT_CICNT_HIBIT 0xF |
| 230 | #define DSPDMAC_IRQCNT_CICNT_MASK 0xFFFF |
| 231 | |
| 232 | #define DSPDMAC_IRQCNT_BICNT_LOBIT 0x10 |
| 233 | #define DSPDMAC_IRQCNT_BICNT_HIBIT 0x1F |
| 234 | #define DSPDMAC_IRQCNT_BICNT_MASK 0xFFFF0000 |
| 235 | |
| 236 | #define DSPDMAC_AUD_CHSEL_CHANNEL_COUNT 12 |
| 237 | #define DSPDMAC_AUDCHSEL_MODULE_OFFSET 0xFC0 |
| 238 | #define DSPDMAC_AUDCHSEL_CHAN_INCR 0x4 |
| 239 | #define DSPDMAC_AUDCHSEL_INST_OFFSET(_chan) \ |
| 240 | (DSPDMAC_CHIP_OFFSET + DSPDMAC_AUDCHSEL_MODULE_OFFSET + \ |
| 241 | (_chan * DSPDMAC_AUDCHSEL_CHAN_INCR)) |
| 242 | |
| 243 | #define DSPDMAC_AUDCHSEL_ACS_LOBIT 0x0 |
| 244 | #define DSPDMAC_AUDCHSEL_ACS_HIBIT 0x1F |
| 245 | #define DSPDMAC_AUDCHSEL_ACS_MASK 0xFFFFFFFF |
| 246 | |
| 247 | #define DSPDMAC_CHNLSTART_MODULE_OFFSET 0xFF0 |
| 248 | #define DSPDMAC_CHNLSTART_INST_OFFSET \ |
| 249 | (DSPDMAC_CHIP_OFFSET + DSPDMAC_CHNLSTART_MODULE_OFFSET) |
| 250 | |
| 251 | #define DSPDMAC_CHNLSTART_EN_LOBIT 0x0 |
| 252 | #define DSPDMAC_CHNLSTART_EN_HIBIT 0xB |
| 253 | #define DSPDMAC_CHNLSTART_EN_MASK 0xFFF |
| 254 | |
| 255 | #define DSPDMAC_CHNLSTART_VAI1_LOBIT 0xC |
| 256 | #define DSPDMAC_CHNLSTART_VAI1_HIBIT 0xF |
| 257 | #define DSPDMAC_CHNLSTART_VAI1_MASK 0xF000 |
| 258 | |
| 259 | #define DSPDMAC_CHNLSTART_DIS_LOBIT 0x10 |
| 260 | #define DSPDMAC_CHNLSTART_DIS_HIBIT 0x1B |
| 261 | #define DSPDMAC_CHNLSTART_DIS_MASK 0xFFF0000 |
| 262 | |
| 263 | #define DSPDMAC_CHNLSTART_VAI2_LOBIT 0x1C |
| 264 | #define DSPDMAC_CHNLSTART_VAI2_HIBIT 0x1F |
| 265 | #define DSPDMAC_CHNLSTART_VAI2_MASK 0xF0000000 |
| 266 | |
| 267 | #define DSPDMAC_CHNLSTATUS_MODULE_OFFSET 0xFF4 |
| 268 | #define DSPDMAC_CHNLSTATUS_INST_OFFSET \ |
| 269 | (DSPDMAC_CHIP_OFFSET + DSPDMAC_CHNLSTATUS_MODULE_OFFSET) |
| 270 | |
| 271 | #define DSPDMAC_CHNLSTATUS_ISC_LOBIT 0x0 |
| 272 | #define DSPDMAC_CHNLSTATUS_ISC_HIBIT 0xB |
| 273 | #define DSPDMAC_CHNLSTATUS_ISC_MASK 0xFFF |
| 274 | |
| 275 | #define DSPDMAC_CHNLSTATUS_AOO_LOBIT 0xC |
| 276 | #define DSPDMAC_CHNLSTATUS_AOO_HIBIT 0xC |
| 277 | #define DSPDMAC_CHNLSTATUS_AOO_MASK 0x1000 |
| 278 | |
| 279 | #define DSPDMAC_CHNLSTATUS_AOU_LOBIT 0xD |
| 280 | #define DSPDMAC_CHNLSTATUS_AOU_HIBIT 0xD |
| 281 | #define DSPDMAC_CHNLSTATUS_AOU_MASK 0x2000 |
| 282 | |
| 283 | #define DSPDMAC_CHNLSTATUS_AIO_LOBIT 0xE |
| 284 | #define DSPDMAC_CHNLSTATUS_AIO_HIBIT 0xE |
| 285 | #define DSPDMAC_CHNLSTATUS_AIO_MASK 0x4000 |
| 286 | |
| 287 | #define DSPDMAC_CHNLSTATUS_AIU_LOBIT 0xF |
| 288 | #define DSPDMAC_CHNLSTATUS_AIU_HIBIT 0xF |
| 289 | #define DSPDMAC_CHNLSTATUS_AIU_MASK 0x8000 |
| 290 | |
| 291 | #define DSPDMAC_CHNLSTATUS_IEN_LOBIT 0x10 |
| 292 | #define DSPDMAC_CHNLSTATUS_IEN_HIBIT 0x1B |
| 293 | #define DSPDMAC_CHNLSTATUS_IEN_MASK 0xFFF0000 |
| 294 | |
| 295 | #define DSPDMAC_CHNLSTATUS_VAI0_LOBIT 0x1C |
| 296 | #define DSPDMAC_CHNLSTATUS_VAI0_HIBIT 0x1F |
| 297 | #define DSPDMAC_CHNLSTATUS_VAI0_MASK 0xF0000000 |
| 298 | |
| 299 | #define DSPDMAC_CHNLPROP_MODULE_OFFSET 0xFF8 |
| 300 | #define DSPDMAC_CHNLPROP_INST_OFFSET \ |
| 301 | (DSPDMAC_CHIP_OFFSET + DSPDMAC_CHNLPROP_MODULE_OFFSET) |
| 302 | |
| 303 | #define DSPDMAC_CHNLPROP_DCON_LOBIT 0x0 |
| 304 | #define DSPDMAC_CHNLPROP_DCON_HIBIT 0xB |
| 305 | #define DSPDMAC_CHNLPROP_DCON_MASK 0xFFF |
| 306 | |
| 307 | #define DSPDMAC_CHNLPROP_FFS_LOBIT 0xC |
| 308 | #define DSPDMAC_CHNLPROP_FFS_HIBIT 0xC |
| 309 | #define DSPDMAC_CHNLPROP_FFS_MASK 0x1000 |
| 310 | |
| 311 | #define DSPDMAC_CHNLPROP_NAJ_LOBIT 0xD |
| 312 | #define DSPDMAC_CHNLPROP_NAJ_HIBIT 0xD |
| 313 | #define DSPDMAC_CHNLPROP_NAJ_MASK 0x2000 |
| 314 | |
| 315 | #define DSPDMAC_CHNLPROP_ENH_LOBIT 0xE |
| 316 | #define DSPDMAC_CHNLPROP_ENH_HIBIT 0xE |
| 317 | #define DSPDMAC_CHNLPROP_ENH_MASK 0x4000 |
| 318 | |
| 319 | #define DSPDMAC_CHNLPROP_MSPCE_LOBIT 0x10 |
| 320 | #define DSPDMAC_CHNLPROP_MSPCE_HIBIT 0x1B |
| 321 | #define DSPDMAC_CHNLPROP_MSPCE_MASK 0xFFF0000 |
| 322 | |
| 323 | #define DSPDMAC_CHNLPROP_AC_LOBIT 0x1C |
| 324 | #define DSPDMAC_CHNLPROP_AC_HIBIT 0x1F |
| 325 | #define DSPDMAC_CHNLPROP_AC_MASK 0xF0000000 |
| 326 | |
| 327 | #define DSPDMAC_ACTIVE_MODULE_OFFSET 0xFFC |
| 328 | #define DSPDMAC_ACTIVE_INST_OFFSET \ |
| 329 | (DSPDMAC_CHIP_OFFSET + DSPDMAC_ACTIVE_MODULE_OFFSET) |
| 330 | |
| 331 | #define DSPDMAC_ACTIVE_AAR_LOBIT 0x0 |
| 332 | #define DSPDMAC_ACTIVE_AAR_HIBIT 0xB |
| 333 | #define DSPDMAC_ACTIVE_AAR_MASK 0xFFF |
| 334 | |
| 335 | #define DSPDMAC_ACTIVE_WFR_LOBIT 0xC |
| 336 | #define DSPDMAC_ACTIVE_WFR_HIBIT 0x17 |
| 337 | #define DSPDMAC_ACTIVE_WFR_MASK 0xFFF000 |
| 338 | |
| 339 | #define DSP_AUX_MEM_BASE 0xE000 |
| 340 | #define INVALID_CHIP_ADDRESS (~0UL) |
| 341 | |
| 342 | #define X_SIZE (XRAM_XRAM_CHANNEL_COUNT * XRAM_XRAM_CHAN_INCR) |
| 343 | #define Y_SIZE (YRAM_YRAM_CHANNEL_COUNT * YRAM_YRAM_CHAN_INCR) |
| 344 | #define AX_SIZE (AXRAM_AXRAM_CHANNEL_COUNT * AXRAM_AXRAM_CHAN_INCR) |
| 345 | #define AY_SIZE (AYRAM_AYRAM_CHANNEL_COUNT * AYRAM_AYRAM_CHAN_INCR) |
| 346 | #define UC_SIZE (UC_UC_CHANNEL_COUNT * UC_UC_CHAN_INCR) |
| 347 | |
| 348 | #define XEXT_SIZE (X_SIZE + AX_SIZE) |
| 349 | #define YEXT_SIZE (Y_SIZE + AY_SIZE) |
| 350 | |
| 351 | #define U64K 0x10000UL |
| 352 | |
| 353 | #define X_END (XRAM_CHIP_OFFSET + X_SIZE) |
| 354 | #define X_EXT (XRAM_CHIP_OFFSET + XEXT_SIZE) |
| 355 | #define AX_END (XRAM_CHIP_OFFSET + U64K*4) |
| 356 | |
| 357 | #define Y_END (YRAM_CHIP_OFFSET + Y_SIZE) |
| 358 | #define Y_EXT (YRAM_CHIP_OFFSET + YEXT_SIZE) |
| 359 | #define AY_END (YRAM_CHIP_OFFSET + U64K*4) |
| 360 | |
| 361 | #define UC_END (UC_CHIP_OFFSET + UC_SIZE) |
| 362 | |
| 363 | #define X_RANGE_MAIN(a, s) \ |
| 364 | (((a)+((s)-1)*XRAM_XRAM_CHAN_INCR < X_END)) |
| 365 | #define X_RANGE_AUX(a, s) \ |
| 366 | (((a) >= X_END) && ((a)+((s)-1)*XRAM_XRAM_CHAN_INCR < AX_END)) |
| 367 | #define X_RANGE_EXT(a, s) \ |
| 368 | (((a)+((s)-1)*XRAM_XRAM_CHAN_INCR < X_EXT)) |
| 369 | #define X_RANGE_ALL(a, s) \ |
| 370 | (((a)+((s)-1)*XRAM_XRAM_CHAN_INCR < AX_END)) |
| 371 | |
| 372 | #define Y_RANGE_MAIN(a, s) \ |
| 373 | (((a) >= YRAM_CHIP_OFFSET) && \ |
| 374 | ((a)+((s)-1)*YRAM_YRAM_CHAN_INCR < Y_END)) |
| 375 | #define Y_RANGE_AUX(a, s) \ |
| 376 | (((a) >= Y_END) && \ |
| 377 | ((a)+((s)-1)*YRAM_YRAM_CHAN_INCR < AY_END)) |
| 378 | #define Y_RANGE_EXT(a, s) \ |
| 379 | (((a) >= YRAM_CHIP_OFFSET) && \ |
| 380 | ((a)+((s)-1)*YRAM_YRAM_CHAN_INCR < Y_EXT)) |
| 381 | #define Y_RANGE_ALL(a, s) \ |
| 382 | (((a) >= YRAM_CHIP_OFFSET) && \ |
| 383 | ((a)+((s)-1)*YRAM_YRAM_CHAN_INCR < AY_END)) |
| 384 | |
| 385 | #define UC_RANGE(a, s) \ |
| 386 | (((a) >= UC_CHIP_OFFSET) && \ |
| 387 | ((a)+((s)-1)*UC_UC_CHAN_INCR < UC_END)) |
| 388 | |
| 389 | #define X_OFF(a) \ |
| 390 | (((a) - XRAM_CHIP_OFFSET) / XRAM_XRAM_CHAN_INCR) |
| 391 | #define AX_OFF(a) \ |
| 392 | (((a) % (AXRAM_AXRAM_CHANNEL_COUNT * \ |
| 393 | AXRAM_AXRAM_CHAN_INCR)) / AXRAM_AXRAM_CHAN_INCR) |
| 394 | |
| 395 | #define Y_OFF(a) \ |
| 396 | (((a) - YRAM_CHIP_OFFSET) / YRAM_YRAM_CHAN_INCR) |
| 397 | #define AY_OFF(a) \ |
| 398 | (((a) % (AYRAM_AYRAM_CHANNEL_COUNT * \ |
| 399 | AYRAM_AYRAM_CHAN_INCR)) / AYRAM_AYRAM_CHAN_INCR) |
| 400 | |
| 401 | #define UC_OFF(a) (((a) - UC_CHIP_OFFSET) / UC_UC_CHAN_INCR) |
| 402 | |
| 403 | #define X_EXT_MAIN_SIZE(a) (XRAM_XRAM_CHANNEL_COUNT - X_OFF(a)) |
| 404 | #define X_EXT_AUX_SIZE(a, s) ((s) - X_EXT_MAIN_SIZE(a)) |
| 405 | |
| 406 | #define Y_EXT_MAIN_SIZE(a) (YRAM_YRAM_CHANNEL_COUNT - Y_OFF(a)) |
| 407 | #define Y_EXT_AUX_SIZE(a, s) ((s) - Y_EXT_MAIN_SIZE(a)) |
| 408 | |
| 409 | #endif |