blob: 2051dc96b8e94aee2b63af14d3d2a8a9486cfdcd [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
3 */
4
Jesse Barnesf8977d02005-10-25 10:28:42 -07005#include <linux/delay.h>
6#include <linux/dmi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -07007#include <linux/pci.h>
8#include <linux/init.h>
9#include "pci.h"
10
11
12static void __devinit pci_fixup_i450nx(struct pci_dev *d)
13{
14 /*
15 * i450NX -- Find and scan all secondary buses on all PXB's.
16 */
17 int pxb, reg;
18 u8 busno, suba, subb;
19
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -070020 dev_warn(&d->dev, "Searching for i450NX host bridges\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070021 reg = 0xd0;
Paolo Ciarrocchi938f6672008-01-30 13:33:00 +010022 for(pxb = 0; pxb < 2; pxb++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070023 pci_read_config_byte(d, reg++, &busno);
24 pci_read_config_byte(d, reg++, &suba);
25 pci_read_config_byte(d, reg++, &subb);
Bjorn Helgaas12c0b202008-07-23 17:00:13 -060026 dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno,
27 suba, subb);
Linus Torvalds1da177e2005-04-16 15:20:36 -070028 if (busno)
Muli Ben-Yehuda73c59af2007-08-10 13:01:19 -070029 pci_scan_bus_with_sysdata(busno); /* Bus A */
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 if (suba < subb)
Muli Ben-Yehuda73c59af2007-08-10 13:01:19 -070031 pci_scan_bus_with_sysdata(suba+1); /* Bus B */
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 }
33 pcibios_last_bus = -1;
34}
35DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
36
37static void __devinit pci_fixup_i450gx(struct pci_dev *d)
38{
39 /*
40 * i450GX and i450KX -- Find and scan all secondary buses.
41 * (called separately for each PCI bridge found)
42 */
43 u8 busno;
44 pci_read_config_byte(d, 0x4a, &busno);
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -070045 dev_info(&d->dev, "i440KX/GX host bridge; secondary bus %02x\n", busno);
Muli Ben-Yehuda73c59af2007-08-10 13:01:19 -070046 pci_scan_bus_with_sysdata(busno);
Linus Torvalds1da177e2005-04-16 15:20:36 -070047 pcibios_last_bus = -1;
48}
49DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx);
50
51static void __devinit pci_fixup_umc_ide(struct pci_dev *d)
52{
53 /*
54 * UM8886BF IDE controller sets region type bits incorrectly,
55 * therefore they look like memory despite of them being I/O.
56 */
57 int i;
58
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -070059 dev_warn(&d->dev, "Fixing base address flags\n");
Paolo Ciarrocchi938f6672008-01-30 13:33:00 +010060 for(i = 0; i < 4; i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -070061 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
62}
63DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);
64
65static void __devinit pci_fixup_ncr53c810(struct pci_dev *d)
66{
67 /*
68 * NCR 53C810 returns class code 0 (at least on some systems).
69 * Fix class to be PCI_CLASS_STORAGE_SCSI
70 */
71 if (!d->class) {
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -070072 dev_warn(&d->dev, "Fixing NCR 53C810 class code\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070073 d->class = PCI_CLASS_STORAGE_SCSI << 8;
74 }
75}
76DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, pci_fixup_ncr53c810);
77
Linus Torvalds1da177e2005-04-16 15:20:36 -070078static void __devinit pci_fixup_latency(struct pci_dev *d)
79{
80 /*
81 * SiS 5597 and 5598 chipsets require latency timer set to
82 * at most 32 to avoid lockups.
83 */
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -070084 dev_dbg(&d->dev, "Setting max latency to 32\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070085 pcibios_max_latency = 32;
86}
87DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
88DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);
89
90static void __devinit pci_fixup_piix4_acpi(struct pci_dev *d)
91{
92 /*
93 * PIIX4 ACPI device: hardwired IRQ9
94 */
95 d->irq = 9;
96}
97DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi);
98
99/*
100 * Addresses issues with problems in the memory write queue timer in
101 * certain VIA Northbridges. This bugfix is per VIA's specifications,
102 * except for the KL133/KM133: clearing bit 5 on those Northbridges seems
103 * to trigger a bug in its integrated ProSavage video card, which
104 * causes screen corruption. We only clear bits 6 and 7 for that chipset,
105 * until VIA can provide us with definitive information on why screen
106 * corruption occurs, and what exactly those bits do.
107 *
108 * VIA 8363,8622,8361 Northbridges:
109 * - bits 5, 6, 7 at offset 0x55 need to be turned off
110 * VIA 8367 (KT266x) Northbridges:
111 * - bits 5, 6, 7 at offset 0x95 need to be turned off
112 * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges:
113 * - bits 6, 7 at offset 0x55 need to be turned off
114 */
115
116#define VIA_8363_KL133_REVISION_ID 0x81
117#define VIA_8363_KM133_REVISION_ID 0x84
118
Alan Cox1597cac2006-12-04 15:14:45 -0800119static void pci_fixup_via_northbridge_bug(struct pci_dev *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120{
121 u8 v;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122 int where = 0x55;
123 int mask = 0x1f; /* clear bits 5, 6, 7 by default */
124
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125 if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
126 /* fix pci bus latency issues resulted by NB bios error
127 it appears on bug free^Wreduced kt266x's bios forces
128 NB latency to zero */
129 pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);
130
Paolo Ciarrocchi938f6672008-01-30 13:33:00 +0100131 where = 0x95; /* the memory write queue timer register is
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132 different for the KT266x's: 0x95 not 0x55 */
133 } else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
Auke Kok44c10132007-06-08 15:46:36 -0700134 (d->revision == VIA_8363_KL133_REVISION_ID ||
135 d->revision == VIA_8363_KM133_REVISION_ID)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700136 mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5
137 causes screen corruption on the KL133/KM133 */
138 }
139
140 pci_read_config_byte(d, where, &v);
141 if (v & ~mask) {
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700142 dev_warn(&d->dev, "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
Auke Kok44c10132007-06-08 15:46:36 -0700143 d->device, d->revision, where, v, mask, v & mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700144 v &= mask;
145 pci_write_config_byte(d, where, v);
146 }
147}
148DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
149DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
150DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
151DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
Alan Cox1597cac2006-12-04 15:14:45 -0800152DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
153DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
154DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
155DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700156
157/*
158 * For some reasons Intel decided that certain parts of their
159 * 815, 845 and some other chipsets must look like PCI-to-PCI bridges
160 * while they are obviously not. The 82801 family (AA, AB, BAM/CAM,
161 * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according
162 * to Intel terminology. These devices do forward all addresses from
163 * system to PCI bus no matter what are their window settings, so they are
164 * "transparent" (or subtractive decoding) from programmers point of view.
165 */
166static void __devinit pci_fixup_transparent_bridge(struct pci_dev *dev)
167{
168 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
169 (dev->device & 0xff00) == 0x2400)
170 dev->transparent = 1;
171}
172DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixup_transparent_bridge);
173
174/*
175 * Fixup for C1 Halt Disconnect problem on nForce2 systems.
176 *
177 * From information provided by "Allen Martin" <AMartin@nvidia.com>:
178 *
179 * A hang is caused when the CPU generates a very fast CONNECT/HALT cycle
180 * sequence. Workaround is to set the SYSTEM_IDLE_TIMEOUT to 80 ns.
181 * This allows the state-machine and timer to return to a proper state within
182 * 80 ns of the CONNECT and probe appearing together. Since the CPU will not
183 * issue another HALT within 80 ns of the initial HALT, the failure condition
184 * is avoided.
185 */
Alan Cox1597cac2006-12-04 15:14:45 -0800186static void pci_fixup_nforce2(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700187{
188 u32 val;
189
190 /*
191 * Chip Old value New value
192 * C17 0x1F0FFF01 0x1F01FF01
193 * C18D 0x9F0FFF01 0x9F01FF01
194 *
195 * Northbridge chip version may be determined by
196 * reading the PCI revision ID (0xC1 or greater is C18D).
197 */
198 pci_read_config_dword(dev, 0x6c, &val);
199
200 /*
201 * Apply fixup if needed, but don't touch disconnect state
202 */
203 if ((val & 0x00FF0000) != 0x00010000) {
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700204 dev_warn(&dev->dev, "nForce2 C1 Halt Disconnect fixup\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700205 pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000);
206 }
207}
208DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
Alan Cox1597cac2006-12-04 15:14:45 -0800209DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700210
211/* Max PCI Express root ports */
212#define MAX_PCIEROOT 6
213static int quirk_aspm_offset[MAX_PCIEROOT << 3];
214
Christoph Lameterff0d2f92005-05-17 08:48:16 -0700215#define GET_INDEX(a, b) ((((a) - PCI_DEVICE_ID_INTEL_MCH_PA) << 3) + ((b) & 7))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216
217static int quirk_pcie_aspm_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
218{
Matthew Wilcoxb6ce0682008-02-10 09:45:28 -0500219 return raw_pci_read(pci_domain_nr(bus), bus->number,
220 devfn, where, size, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221}
222
223/*
224 * Replace the original pci bus ops for write with a new one that will filter
225 * the request to insure ASPM cannot be enabled.
226 */
227static int quirk_pcie_aspm_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
228{
229 u8 offset;
230
231 offset = quirk_aspm_offset[GET_INDEX(bus->self->device, devfn)];
232
233 if ((offset) && (where == offset))
234 value = value & 0xfffffffc;
Paolo Ciarrocchi938f6672008-01-30 13:33:00 +0100235
Matthew Wilcoxb6ce0682008-02-10 09:45:28 -0500236 return raw_pci_write(pci_domain_nr(bus), bus->number,
237 devfn, where, size, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238}
239
240static struct pci_ops quirk_pcie_aspm_ops = {
241 .read = quirk_pcie_aspm_read,
242 .write = quirk_pcie_aspm_write,
243};
244
245/*
246 * Prevents PCI Express ASPM (Active State Power Management) being enabled.
247 *
248 * Save the register offset, where the ASPM control bits are located,
249 * for each PCI Express device that is in the device list of
250 * the root port in an array for fast indexing. Replace the bus ops
251 * with the modified one.
252 */
253static void pcie_rootport_aspm_quirk(struct pci_dev *pdev)
254{
255 int cap_base, i;
256 struct pci_bus *pbus;
257 struct pci_dev *dev;
258
259 if ((pbus = pdev->subordinate) == NULL)
260 return;
261
262 /*
263 * Check if the DID of pdev matches one of the six root ports. This
264 * check is needed in the case this function is called directly by the
265 * hot-plug driver.
266 */
267 if ((pdev->device < PCI_DEVICE_ID_INTEL_MCH_PA) ||
268 (pdev->device > PCI_DEVICE_ID_INTEL_MCH_PC1))
269 return;
270
271 if (list_empty(&pbus->devices)) {
272 /*
273 * If no device is attached to the root port at power-up or
274 * after hot-remove, the pbus->devices is empty and this code
275 * will set the offsets to zero and the bus ops to parent's bus
276 * ops, which is unmodified.
Paolo Ciarrocchi938f6672008-01-30 13:33:00 +0100277 */
278 for (i = GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700279 quirk_aspm_offset[i] = 0;
280
281 pbus->ops = pbus->parent->ops;
282 } else {
283 /*
284 * If devices are attached to the root port at power-up or
285 * after hot-add, the code loops through the device list of
286 * each root port to save the register offsets and replace the
287 * bus ops.
288 */
289 list_for_each_entry(dev, &pbus->devices, bus_list) {
290 /* There are 0 to 8 devices attached to this bus */
291 cap_base = pci_find_capability(dev, PCI_CAP_ID_EXP);
Paolo Ciarrocchi938f6672008-01-30 13:33:00 +0100292 quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)] = cap_base + 0x10;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700293 }
294 pbus->ops = &quirk_pcie_aspm_ops;
295 }
296}
Paolo Ciarrocchi938f6672008-01-30 13:33:00 +0100297DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA, pcie_rootport_aspm_quirk);
298DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA1, pcie_rootport_aspm_quirk);
299DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB, pcie_rootport_aspm_quirk);
300DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB1, pcie_rootport_aspm_quirk);
301DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC, pcie_rootport_aspm_quirk);
302DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC1, pcie_rootport_aspm_quirk);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303
304/*
Eiichiro Oiwa6b5c76b2006-10-23 15:14:07 +0900305 * Fixup to mark boot BIOS video selected by BIOS before it changes
306 *
307 * From information provided by "Jon Smirl" <jonsmirl@gmail.com>
308 *
309 * The standard boot ROM sequence for an x86 machine uses the BIOS
310 * to select an initial video card for boot display. This boot video
311 * card will have it's BIOS copied to C0000 in system RAM.
312 * IORESOURCE_ROM_SHADOW is used to associate the boot video
313 * card with this copy. On laptops this copy has to be used since
314 * the main ROM may be compressed or combined with another image.
315 * See pci_map_rom() for use of this flag. IORESOURCE_ROM_SHADOW
316 * is marked here since the boot video device will be the only enabled
317 * video device at this point.
318 */
319
320static void __devinit pci_fixup_video(struct pci_dev *pdev)
321{
322 struct pci_dev *bridge;
323 struct pci_bus *bus;
324 u16 config;
325
326 if ((pdev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
327 return;
328
329 /* Is VGA routed to us? */
330 bus = pdev->bus;
331 while (bus) {
332 bridge = bus->self;
333
334 /*
335 * From information provided by
336 * "David Miller" <davem@davemloft.net>
337 * The bridge control register is valid for PCI header
338 * type BRIDGE, or CARDBUS. Host to PCI controllers use
339 * PCI header type NORMAL.
340 */
341 if (bridge
Paolo Ciarrocchi938f6672008-01-30 13:33:00 +0100342 && ((bridge->hdr_type == PCI_HEADER_TYPE_BRIDGE)
343 || (bridge->hdr_type == PCI_HEADER_TYPE_CARDBUS))) {
Eiichiro Oiwa6b5c76b2006-10-23 15:14:07 +0900344 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
345 &config);
346 if (!(config & PCI_BRIDGE_CTL_VGA))
347 return;
348 }
349 bus = bus->parent;
350 }
351 pci_read_config_word(pdev, PCI_COMMAND, &config);
352 if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
353 pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW;
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700354 dev_printk(KERN_DEBUG, &pdev->dev, "Boot video device\n");
Eiichiro Oiwa6b5c76b2006-10-23 15:14:07 +0900355 }
356}
Jesse Barnes40ee9e92007-03-24 11:03:32 -0700357DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_video);
Eiichiro Oiwa6b5c76b2006-10-23 15:14:07 +0900358
Johannes Goecke346ca042007-09-10 10:46:52 +0200359
360static struct dmi_system_id __devinitdata msi_k8t_dmi_table[] = {
361 {
362 .ident = "MSI-K8T-Neo2Fir",
363 .matches = {
364 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
365 DMI_MATCH(DMI_PRODUCT_NAME, "MS-6702E"),
366 },
367 },
368 {}
369};
370
371/*
372 * The AMD-Athlon64 board MSI "K8T Neo2-FIR" disables the onboard sound
373 * card if a PCI-soundcard is added.
374 *
375 * The BIOS only gives options "DISABLED" and "AUTO". This code sets
376 * the corresponding register-value to enable the soundcard.
377 *
378 * The soundcard is only enabled, if the mainborad is identified
379 * via DMI-tables and the soundcard is detected to be off.
380 */
381static void __devinit pci_fixup_msi_k8t_onboard_sound(struct pci_dev *dev)
382{
383 unsigned char val;
384 if (!dmi_check_system(msi_k8t_dmi_table))
385 return; /* only applies to MSI K8T Neo2-FIR */
386
387 pci_read_config_byte(dev, 0x50, &val);
388 if (val & 0x40) {
389 pci_write_config_byte(dev, 0x50, val & (~0x40));
390
391 /* verify the change for status output */
392 pci_read_config_byte(dev, 0x50, &val);
393 if (val & 0x40)
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700394 dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "
Johannes Goecke346ca042007-09-10 10:46:52 +0200395 "can't enable onboard soundcard!\n");
396 else
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700397 dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "
398 "enabled onboard soundcard\n");
Johannes Goecke346ca042007-09-10 10:46:52 +0200399 }
400}
401DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
402 pci_fixup_msi_k8t_onboard_sound);
403DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
404 pci_fixup_msi_k8t_onboard_sound);
405
Eiichiro Oiwa6b5c76b2006-10-23 15:14:07 +0900406/*
Jesse Barnesf8977d02005-10-25 10:28:42 -0700407 * Some Toshiba laptops need extra code to enable their TI TSB43AB22/A.
408 *
409 * We pretend to bring them out of full D3 state, and restore the proper
410 * IRQ, PCI cache line size, and BARs, otherwise the device won't function
411 * properly. In some cases, the device will generate an interrupt on
Matt LaPlante4b3f6862006-10-03 22:21:02 +0200412 * the wrong IRQ line, causing any devices sharing the line it's
Jesse Barnesf8977d02005-10-25 10:28:42 -0700413 * *supposed* to use to be disabled by the kernel's IRQ debug code.
414 */
415static u16 toshiba_line_size;
416
Roland Dreier1d373742005-10-28 21:50:35 -0700417static struct dmi_system_id __devinitdata toshiba_ohci1394_dmi_table[] = {
Jesse Barnesf8977d02005-10-25 10:28:42 -0700418 {
419 .ident = "Toshiba PS5 based laptop",
420 .matches = {
421 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
422 DMI_MATCH(DMI_PRODUCT_VERSION, "PS5"),
423 },
424 },
425 {
426 .ident = "Toshiba PSM4 based laptop",
427 .matches = {
428 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
429 DMI_MATCH(DMI_PRODUCT_VERSION, "PSM4"),
430 },
431 },
Jesse Barnes19272682005-12-17 09:27:50 -0800432 {
433 .ident = "Toshiba A40 based laptop",
434 .matches = {
435 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
436 DMI_MATCH(DMI_PRODUCT_VERSION, "PSA40U"),
437 },
438 },
Jesse Barnesf8977d02005-10-25 10:28:42 -0700439 { }
440};
441
442static void __devinit pci_pre_fixup_toshiba_ohci1394(struct pci_dev *dev)
443{
444 if (!dmi_check_system(toshiba_ohci1394_dmi_table))
445 return; /* only applies to certain Toshibas (so far) */
446
447 dev->current_state = PCI_D3cold;
448 pci_read_config_word(dev, PCI_CACHE_LINE_SIZE, &toshiba_line_size);
449}
450DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0x8032,
451 pci_pre_fixup_toshiba_ohci1394);
452
453static void __devinit pci_post_fixup_toshiba_ohci1394(struct pci_dev *dev)
454{
455 if (!dmi_check_system(toshiba_ohci1394_dmi_table))
456 return; /* only applies to certain Toshibas (so far) */
457
458 /* Restore config space on Toshiba laptops */
Jesse Barnesf8977d02005-10-25 10:28:42 -0700459 pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, toshiba_line_size);
Jesse Barnes6e6ece52005-11-08 20:13:02 -0800460 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, (u8 *)&dev->irq);
Jesse Barnesf8977d02005-10-25 10:28:42 -0700461 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
462 pci_resource_start(dev, 0));
463 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
464 pci_resource_start(dev, 1));
465}
466DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_TI, 0x8032,
467 pci_post_fixup_toshiba_ohci1394);
David Vrabela80da732006-01-14 13:21:23 -0800468
469
470/*
471 * Prevent the BIOS trapping accesses to the Cyrix CS5530A video device
472 * configuration space.
473 */
Alan Cox1597cac2006-12-04 15:14:45 -0800474static void pci_early_fixup_cyrix_5530(struct pci_dev *dev)
David Vrabela80da732006-01-14 13:21:23 -0800475{
476 u8 r;
477 /* clear 'F4 Video Configuration Trap' bit */
478 pci_read_config_byte(dev, 0x42, &r);
479 r &= 0xfd;
480 pci_write_config_byte(dev, 0x42, r);
481}
482DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
483 pci_early_fixup_cyrix_5530);
Alan Cox1597cac2006-12-04 15:14:45 -0800484DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
485 pci_early_fixup_cyrix_5530);
Ivan Kokshaysky73a74ed2007-05-23 14:50:02 -0700486
487/*
488 * Siemens Nixdorf AG FSC Multiprocessor Interrupt Controller:
489 * prevent update of the BAR0, which doesn't look like a normal BAR.
490 */
491static void __devinit pci_siemens_interrupt_controller(struct pci_dev *dev)
492{
493 dev->resource[0].flags |= IORESOURCE_PCI_FIXED;
494}
495DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015,
496 pci_siemens_interrupt_controller);
Yinghai Lu57741a72008-02-15 01:32:50 -0800497
498/*
Andreas Herrmannffd565a2008-11-25 17:18:03 +0100499 * Regular PCI devices have 256 bytes, but AMD Family 10h/11h CPUs have
500 * 4096 bytes configuration space for each function of their processor
501 * configuration space.
Yinghai Lu57741a72008-02-15 01:32:50 -0800502 */
Andreas Herrmannffd565a2008-11-25 17:18:03 +0100503static void amd_cpu_pci_cfg_space_size(struct pci_dev *dev)
Yinghai Lu57741a72008-02-15 01:32:50 -0800504{
Yinghai Lu70b9f7d2008-04-28 16:27:23 -0700505 dev->cfg_size = pci_cfg_space_size_ext(dev);
Yinghai Lu57741a72008-02-15 01:32:50 -0800506}
Andreas Herrmannffd565a2008-11-25 17:18:03 +0100507DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1200, amd_cpu_pci_cfg_space_size);
508DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1201, amd_cpu_pci_cfg_space_size);
509DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1202, amd_cpu_pci_cfg_space_size);
510DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1203, amd_cpu_pci_cfg_space_size);
511DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1204, amd_cpu_pci_cfg_space_size);
512DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1300, amd_cpu_pci_cfg_space_size);
513DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1301, amd_cpu_pci_cfg_space_size);
514DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1302, amd_cpu_pci_cfg_space_size);
515DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1303, amd_cpu_pci_cfg_space_size);
516DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1304, amd_cpu_pci_cfg_space_size);
Jordan Croused7451fc2008-09-12 11:45:22 -0600517
518/*
519 * SB600: Disable BAR1 on device 14.0 to avoid HPET resources from
520 * confusing the PCI engine:
521 */
522static void sb600_disable_hpet_bar(struct pci_dev *dev)
523{
524 u8 val;
525
526 /*
527 * The SB600 and SB700 both share the same device
528 * ID, but the PM register 0x55 does something different
529 * for the SB700, so make sure we are dealing with the
530 * SB600 before touching the bit:
531 */
532
533 pci_read_config_byte(dev, 0x08, &val);
534
535 if (val < 0x2F) {
536 outb(0x55, 0xCD6);
537 val = inb(0xCD7);
538
539 /* Set bit 7 in PM register 0x55 */
540 outb(0x55, 0xCD6);
541 outb(val | 0x80, 0xCD7);
542 }
543}
544DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4385, sb600_disable_hpet_bar);