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Santosh Shilimkar98272662011-08-16 17:31:40 +05301/*
Santosh Shilimkardb4f3da2013-04-05 18:29:03 +05302 * OMAP4+ CPU idle Routines
Santosh Shilimkar98272662011-08-16 17:31:40 +05303 *
Santosh Shilimkardb4f3da2013-04-05 18:29:03 +05304 * Copyright (C) 2011-2013 Texas Instruments, Inc.
Santosh Shilimkar98272662011-08-16 17:31:40 +05305 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * Rajendra Nayak <rnayak@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/sched.h>
14#include <linux/cpuidle.h>
15#include <linux/cpu_pm.h>
16#include <linux/export.h>
Thomas Gleixnerfa8589f2015-04-03 02:02:47 +020017#include <linux/tick.h>
Santosh Shilimkar98272662011-08-16 17:31:40 +053018
Daniel Lezcano0e9e8b42013-04-23 08:54:39 +000019#include <asm/cpuidle.h>
Santosh Shilimkar98272662011-08-16 17:31:40 +053020
21#include "common.h"
22#include "pm.h"
23#include "prm.h"
Santosh Shilimkardd3ad972011-12-25 21:00:40 +053024#include "clockdomain.h"
Santosh Shilimkar98272662011-08-16 17:31:40 +053025
Santosh Shilimkar865da012014-02-17 13:22:55 +053026#define MAX_CPUS 2
27
Daniel Lezcano7aeb658d2012-04-24 16:05:27 +020028/* Machine specific information */
Santosh Shilimkardb4f3da2013-04-05 18:29:03 +053029struct idle_statedata {
Santosh Shilimkar98272662011-08-16 17:31:40 +053030 u32 cpu_state;
31 u32 mpu_logic_state;
32 u32 mpu_state;
Santosh Shilimkar98272662011-08-16 17:31:40 +053033};
34
Santosh Shilimkardb4f3da2013-04-05 18:29:03 +053035static struct idle_statedata omap4_idle_data[] = {
Daniel Lezcanod0d133d2012-04-24 16:05:26 +020036 {
37 .cpu_state = PWRDM_POWER_ON,
38 .mpu_state = PWRDM_POWER_ON,
39 .mpu_logic_state = PWRDM_POWER_RET,
40 },
41 {
42 .cpu_state = PWRDM_POWER_OFF,
43 .mpu_state = PWRDM_POWER_RET,
44 .mpu_logic_state = PWRDM_POWER_RET,
45 },
46 {
47 .cpu_state = PWRDM_POWER_OFF,
48 .mpu_state = PWRDM_POWER_RET,
49 .mpu_logic_state = PWRDM_POWER_OFF,
50 },
51};
Santosh Shilimkar98272662011-08-16 17:31:40 +053052
Santosh Shilimkar865da012014-02-17 13:22:55 +053053static struct powerdomain *mpu_pd, *cpu_pd[MAX_CPUS];
54static struct clockdomain *cpu_clkdm[MAX_CPUS];
Santosh Shilimkar98272662011-08-16 17:31:40 +053055
Kevin Hilman5b4d5bc2012-03-14 17:26:17 -070056static atomic_t abort_barrier;
Santosh Shilimkar865da012014-02-17 13:22:55 +053057static bool cpu_done[MAX_CPUS];
Santosh Shilimkardb4f3da2013-04-05 18:29:03 +053058static struct idle_statedata *state_ptr = &omap4_idle_data[0];
Santosh Shilimkar98272662011-08-16 17:31:40 +053059
Paul Walmsley9db316b2012-12-15 01:39:19 -070060/* Private functions */
61
Santosh Shilimkar98272662011-08-16 17:31:40 +053062/**
Santosh Shilimkardb4f3da2013-04-05 18:29:03 +053063 * omap_enter_idle_[simple/coupled] - OMAP4PLUS cpuidle entry functions
Santosh Shilimkar98272662011-08-16 17:31:40 +053064 * @dev: cpuidle device
65 * @drv: cpuidle driver
66 * @index: the index of state to be entered
67 *
68 * Called from the CPUidle framework to program the device to the
69 * specified low power state selected by the governor.
70 * Returns the amount of time spent in the low power state.
71 */
Santosh Shilimkardb4f3da2013-04-05 18:29:03 +053072static int omap_enter_idle_simple(struct cpuidle_device *dev,
Santosh Shilimkardd3ad972011-12-25 21:00:40 +053073 struct cpuidle_driver *drv,
74 int index)
75{
Santosh Shilimkardd3ad972011-12-25 21:00:40 +053076 omap_do_wfi();
Santosh Shilimkardd3ad972011-12-25 21:00:40 +053077 return index;
78}
79
Santosh Shilimkardb4f3da2013-04-05 18:29:03 +053080static int omap_enter_idle_coupled(struct cpuidle_device *dev,
Santosh Shilimkar98272662011-08-16 17:31:40 +053081 struct cpuidle_driver *drv,
82 int index)
83{
Santosh Shilimkardb4f3da2013-04-05 18:29:03 +053084 struct idle_statedata *cx = state_ptr + index;
Strashko, Grygorii74ed7bd2013-10-22 22:07:15 +030085 u32 mpuss_can_lose_context = 0;
Santosh Shilimkar98272662011-08-16 17:31:40 +053086
Santosh Shilimkar98272662011-08-16 17:31:40 +053087 /*
Santosh Shilimkardd3ad972011-12-25 21:00:40 +053088 * CPU0 has to wait and stay ON until CPU1 is OFF state.
Santosh Shilimkar98272662011-08-16 17:31:40 +053089 * This is necessary to honour hardware recommondation
90 * of triggeing all the possible low power modes once CPU1 is
91 * out of coherency and in OFF mode.
Santosh Shilimkar98272662011-08-16 17:31:40 +053092 */
Santosh Shilimkardd3ad972011-12-25 21:00:40 +053093 if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
Kevin Hilman5b4d5bc2012-03-14 17:26:17 -070094 while (pwrdm_read_pwrst(cpu_pd[1]) != PWRDM_POWER_OFF) {
Santosh Shilimkardd3ad972011-12-25 21:00:40 +053095 cpu_relax();
Kevin Hilman5b4d5bc2012-03-14 17:26:17 -070096
97 /*
98 * CPU1 could have already entered & exited idle
99 * without hitting off because of a wakeup
100 * or a failed attempt to hit off mode. Check for
101 * that here, otherwise we could spin forever
102 * waiting for CPU1 off.
103 */
104 if (cpu_done[1])
105 goto fail;
106
107 }
Santosh Shilimkar98272662011-08-16 17:31:40 +0530108 }
109
Strashko, Grygorii74ed7bd2013-10-22 22:07:15 +0300110 mpuss_can_lose_context = (cx->mpu_state == PWRDM_POWER_RET) &&
111 (cx->mpu_logic_state == PWRDM_POWER_OFF);
112
Thomas Gleixnerfb7f0392015-04-03 02:31:29 +0200113 tick_broadcast_enter();
Santosh Shilimkar4b353a72014-05-12 17:37:59 -0400114
Santosh Shilimkar98272662011-08-16 17:31:40 +0530115 /*
116 * Call idle CPU PM enter notifier chain so that
117 * VFP and per CPU interrupt context is saved.
118 */
Santosh Shilimkardd3ad972011-12-25 21:00:40 +0530119 cpu_pm_enter();
Santosh Shilimkar98272662011-08-16 17:31:40 +0530120
Santosh Shilimkardd3ad972011-12-25 21:00:40 +0530121 if (dev->cpu == 0) {
122 pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
123 omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
Santosh Shilimkar98272662011-08-16 17:31:40 +0530124
Santosh Shilimkardd3ad972011-12-25 21:00:40 +0530125 /*
126 * Call idle CPU cluster PM enter notifier chain
127 * to save GIC and wakeupgen context.
128 */
Strashko, Grygorii74ed7bd2013-10-22 22:07:15 +0300129 if (mpuss_can_lose_context)
130 cpu_cluster_pm_enter();
Santosh Shilimkardd3ad972011-12-25 21:00:40 +0530131 }
Santosh Shilimkar98272662011-08-16 17:31:40 +0530132
133 omap4_enter_lowpower(dev->cpu, cx->cpu_state);
Kevin Hilman5b4d5bc2012-03-14 17:26:17 -0700134 cpu_done[dev->cpu] = true;
Santosh Shilimkar98272662011-08-16 17:31:40 +0530135
Santosh Shilimkardd3ad972011-12-25 21:00:40 +0530136 /* Wakeup CPU1 only if it is not offlined */
137 if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
Strashko, Grygorii74ed7bd2013-10-22 22:07:15 +0300138
139 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) &&
140 mpuss_can_lose_context)
141 gic_dist_disable();
142
Santosh Shilimkardd3ad972011-12-25 21:00:40 +0530143 clkdm_wakeup(cpu_clkdm[1]);
Santosh Shilimkarb7806dc2013-02-08 22:50:58 +0530144 omap_set_pwrdm_state(cpu_pd[1], PWRDM_POWER_ON);
Santosh Shilimkardd3ad972011-12-25 21:00:40 +0530145 clkdm_allow_idle(cpu_clkdm[1]);
Strashko, Grygorii74ed7bd2013-10-22 22:07:15 +0300146
147 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) &&
148 mpuss_can_lose_context) {
149 while (gic_dist_disabled()) {
150 udelay(1);
151 cpu_relax();
152 }
153 gic_timer_retrigger();
154 }
Santosh Shilimkardd3ad972011-12-25 21:00:40 +0530155 }
Santosh Shilimkar98272662011-08-16 17:31:40 +0530156
157 /*
158 * Call idle CPU PM exit notifier chain to restore
Santosh Shilimkardd3ad972011-12-25 21:00:40 +0530159 * VFP and per CPU IRQ context.
Santosh Shilimkar98272662011-08-16 17:31:40 +0530160 */
Santosh Shilimkardd3ad972011-12-25 21:00:40 +0530161 cpu_pm_exit();
Santosh Shilimkar98272662011-08-16 17:31:40 +0530162
163 /*
164 * Call idle CPU cluster PM exit notifier chain
165 * to restore GIC and wakeupgen context.
166 */
Strashko, Grygorii74ed7bd2013-10-22 22:07:15 +0300167 if (dev->cpu == 0 && mpuss_can_lose_context)
Santosh Shilimkar98272662011-08-16 17:31:40 +0530168 cpu_cluster_pm_exit();
169
Thomas Gleixnerfb7f0392015-04-03 02:31:29 +0200170 tick_broadcast_exit();
Santosh Shilimkar4b353a72014-05-12 17:37:59 -0400171
Kevin Hilman5b4d5bc2012-03-14 17:26:17 -0700172fail:
173 cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
174 cpu_done[dev->cpu] = false;
Santosh Shilimkar98be0dd2011-01-16 00:42:31 +0530175
Santosh Shilimkar98272662011-08-16 17:31:40 +0530176 return index;
177}
178
Santosh Shilimkar4b353a72014-05-12 17:37:59 -0400179/*
180 * For each cpu, setup the broadcast timer because local timers
181 * stops for the states above C1.
182 */
183static void omap_setup_broadcast_timer(void *arg)
184{
Thomas Gleixnerfa8589f2015-04-03 02:02:47 +0200185 tick_broadcast_enable();
Santosh Shilimkar4b353a72014-05-12 17:37:59 -0400186}
187
Paul Walmsley9db316b2012-12-15 01:39:19 -0700188static struct cpuidle_driver omap4_idle_driver = {
Robert Leed13e9262012-03-20 15:22:47 -0500189 .name = "omap4_idle",
190 .owner = THIS_MODULE,
Daniel Lezcano78e90162012-04-24 16:05:23 +0200191 .states = {
192 {
193 /* C1 - CPU0 ON + CPU1 ON + MPU ON */
194 .exit_latency = 2 + 2,
195 .target_residency = 5,
Santosh Shilimkardb4f3da2013-04-05 18:29:03 +0530196 .enter = omap_enter_idle_simple,
Daniel Lezcano78e90162012-04-24 16:05:23 +0200197 .name = "C1",
Santosh Shilimkareb495d32013-03-25 15:35:06 +0530198 .desc = "CPUx ON, MPUSS ON"
Daniel Lezcano78e90162012-04-24 16:05:23 +0200199 },
200 {
Paul Walmsley9db316b2012-12-15 01:39:19 -0700201 /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
Daniel Lezcano78e90162012-04-24 16:05:23 +0200202 .exit_latency = 328 + 440,
203 .target_residency = 960,
Daniel Lezcanob82b6cc2014-11-12 16:03:50 +0100204 .flags = CPUIDLE_FLAG_COUPLED,
Santosh Shilimkardb4f3da2013-04-05 18:29:03 +0530205 .enter = omap_enter_idle_coupled,
Daniel Lezcano78e90162012-04-24 16:05:23 +0200206 .name = "C2",
Santosh Shilimkareb495d32013-03-25 15:35:06 +0530207 .desc = "CPUx OFF, MPUSS CSWR",
Daniel Lezcano78e90162012-04-24 16:05:23 +0200208 },
209 {
210 /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
211 .exit_latency = 460 + 518,
212 .target_residency = 1100,
Daniel Lezcanob82b6cc2014-11-12 16:03:50 +0100213 .flags = CPUIDLE_FLAG_COUPLED,
Santosh Shilimkardb4f3da2013-04-05 18:29:03 +0530214 .enter = omap_enter_idle_coupled,
Daniel Lezcano78e90162012-04-24 16:05:23 +0200215 .name = "C3",
Santosh Shilimkareb495d32013-03-25 15:35:06 +0530216 .desc = "CPUx OFF, MPUSS OSWR",
Daniel Lezcano78e90162012-04-24 16:05:23 +0200217 },
218 },
Daniel Lezcanod0d133d2012-04-24 16:05:26 +0200219 .state_count = ARRAY_SIZE(omap4_idle_data),
Daniel Lezcano78e90162012-04-24 16:05:23 +0200220 .safe_state_index = 0,
Santosh Shilimkar98272662011-08-16 17:31:40 +0530221};
222
Paul Walmsley9db316b2012-12-15 01:39:19 -0700223/* Public functions */
Santosh Shilimkarb93d70a2012-04-17 15:09:20 +0530224
Santosh Shilimkar98272662011-08-16 17:31:40 +0530225/**
Santosh Shilimkardb4f3da2013-04-05 18:29:03 +0530226 * omap4_idle_init - Init routine for OMAP4+ idle
Santosh Shilimkar98272662011-08-16 17:31:40 +0530227 *
Santosh Shilimkardb4f3da2013-04-05 18:29:03 +0530228 * Registers the OMAP4+ specific cpuidle driver to the cpuidle
Santosh Shilimkar98272662011-08-16 17:31:40 +0530229 * framework with the valid set of states.
230 */
231int __init omap4_idle_init(void)
232{
Santosh Shilimkar98272662011-08-16 17:31:40 +0530233 mpu_pd = pwrdm_lookup("mpu_pwrdm");
Santosh Shilimkardd3ad972011-12-25 21:00:40 +0530234 cpu_pd[0] = pwrdm_lookup("cpu0_pwrdm");
235 cpu_pd[1] = pwrdm_lookup("cpu1_pwrdm");
236 if ((!mpu_pd) || (!cpu_pd[0]) || (!cpu_pd[1]))
Santosh Shilimkar98272662011-08-16 17:31:40 +0530237 return -ENODEV;
238
Santosh Shilimkardd3ad972011-12-25 21:00:40 +0530239 cpu_clkdm[0] = clkdm_lookup("mpu0_clkdm");
240 cpu_clkdm[1] = clkdm_lookup("mpu1_clkdm");
241 if (!cpu_clkdm[0] || !cpu_clkdm[1])
242 return -ENODEV;
Santosh Shilimkar98272662011-08-16 17:31:40 +0530243
Santosh Shilimkar4b353a72014-05-12 17:37:59 -0400244 /* Configure the broadcast timer on each cpu */
245 on_each_cpu(omap_setup_broadcast_timer, NULL, 1);
246
Daniel Lezcano0e9e8b42013-04-23 08:54:39 +0000247 return cpuidle_register(&omap4_idle_driver, cpu_online_mask);
Santosh Shilimkar98272662011-08-16 17:31:40 +0530248}