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Vladimir Barinov3d9edf02007-07-10 13:03:43 +01001/*
2 * TI DaVinci GPIO Support
3 *
David Brownelldce11152008-09-07 23:41:04 -07004 * Copyright (c) 2006-2007 David Brownell
Vladimir Barinov3d9edf02007-07-10 13:03:43 +01005 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
Russell King2f8163b2011-07-26 10:53:52 +010012#include <linux/gpio.h>
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010013#include <linux/errno.h>
14#include <linux/kernel.h>
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010015#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/io.h>
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010018
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010019#include <asm/mach/irq.h>
20
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040021struct davinci_gpio_regs {
22 u32 dir;
23 u32 out_data;
24 u32 set_data;
25 u32 clr_data;
26 u32 in_data;
27 u32 set_rising;
28 u32 clr_rising;
29 u32 set_falling;
30 u32 clr_falling;
31 u32 intstat;
32};
33
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040034#define chip2controller(chip) \
Cyril Chemparathy99e9e522010-05-01 18:37:52 -040035 container_of(chip, struct davinci_gpio_controller, chip)
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040036
Cyril Chemparathy99e9e522010-05-01 18:37:52 -040037static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040038static void __iomem *gpio_base;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010039
Cyril Chemparathy99e9e522010-05-01 18:37:52 -040040static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010041{
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040042 void __iomem *ptr;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040043
44 if (gpio < 32 * 1)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040045 ptr = gpio_base + 0x10;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040046 else if (gpio < 32 * 2)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040047 ptr = gpio_base + 0x38;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040048 else if (gpio < 32 * 3)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040049 ptr = gpio_base + 0x60;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040050 else if (gpio < 32 * 4)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040051 ptr = gpio_base + 0x88;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040052 else if (gpio < 32 * 5)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040053 ptr = gpio_base + 0xb0;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040054 else
55 ptr = NULL;
56 return ptr;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010057}
58
Cyril Chemparathy99e9e522010-05-01 18:37:52 -040059static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
Kevin Hilman21ce8732010-02-25 16:49:56 -080060{
Cyril Chemparathy99e9e522010-05-01 18:37:52 -040061 struct davinci_gpio_regs __iomem *g;
Kevin Hilman21ce8732010-02-25 16:49:56 -080062
Thomas Gleixner6845664a2011-03-24 13:25:22 +010063 g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
Kevin Hilman21ce8732010-02-25 16:49:56 -080064
65 return g;
66}
67
Kevin Hilmandc756022009-05-11 11:04:53 -070068static int __init davinci_gpio_irq_setup(void);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010069
70/*--------------------------------------------------------------------------*/
71
Cyril Chemparathy5b3a05c2010-05-01 18:38:27 -040072/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040073static inline int __davinci_direction(struct gpio_chip *chip,
74 unsigned offset, bool out, int value)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010075{
Cyril Chemparathy99e9e522010-05-01 18:37:52 -040076 struct davinci_gpio_controller *d = chip2controller(chip);
77 struct davinci_gpio_regs __iomem *g = d->regs;
Cyril Chemparathyb27b6d02010-05-01 18:37:55 -040078 unsigned long flags;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010079 u32 temp;
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040080 u32 mask = 1 << offset;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010081
Cyril Chemparathyb27b6d02010-05-01 18:37:55 -040082 spin_lock_irqsave(&d->lock, flags);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010083 temp = __raw_readl(&g->dir);
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040084 if (out) {
85 temp &= ~mask;
86 __raw_writel(mask, value ? &g->set_data : &g->clr_data);
87 } else {
88 temp |= mask;
89 }
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010090 __raw_writel(temp, &g->dir);
Cyril Chemparathyb27b6d02010-05-01 18:37:55 -040091 spin_unlock_irqrestore(&d->lock, flags);
David Brownelldce11152008-09-07 23:41:04 -070092
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010093 return 0;
94}
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010095
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040096static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
97{
98 return __davinci_direction(chip, offset, false, 0);
99}
100
101static int
102davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
103{
104 return __davinci_direction(chip, offset, true, value);
105}
106
David Brownelldce11152008-09-07 23:41:04 -0700107/*
108 * Read the pin's value (works even if it's set up as output);
109 * returns zero/nonzero.
110 *
111 * Note that changes are synched to the GPIO clock, so reading values back
112 * right after you've set them may give old values.
113 */
114static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100115{
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400116 struct davinci_gpio_controller *d = chip2controller(chip);
117 struct davinci_gpio_regs __iomem *g = d->regs;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100118
David Brownelldce11152008-09-07 23:41:04 -0700119 return (1 << offset) & __raw_readl(&g->in_data);
120}
121
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100122/*
David Brownelldce11152008-09-07 23:41:04 -0700123 * Assuming the pin is muxed as a gpio output, set its output value.
124 */
125static void
126davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
127{
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400128 struct davinci_gpio_controller *d = chip2controller(chip);
129 struct davinci_gpio_regs __iomem *g = d->regs;
David Brownelldce11152008-09-07 23:41:04 -0700130
131 __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
132}
133
134static int __init davinci_gpio_setup(void)
135{
136 int i, base;
Mark A. Greera9949552009-04-15 12:40:35 -0700137 unsigned ngpio;
138 struct davinci_soc_info *soc_info = &davinci_soc_info;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -0400139 struct davinci_gpio_regs *regs;
David Brownelldce11152008-09-07 23:41:04 -0700140
Cyril Chemparathy686b6342010-05-01 18:37:54 -0400141 if (soc_info->gpio_type != GPIO_TYPE_DAVINCI)
142 return 0;
143
Mark A. Greera9949552009-04-15 12:40:35 -0700144 /*
145 * The gpio banks conceptually expose a segmented bitmap,
David Brownell474dad52008-12-07 11:46:23 -0800146 * and "ngpio" is one more than the largest zero-based
147 * bit index that's valid.
148 */
Mark A. Greera9949552009-04-15 12:40:35 -0700149 ngpio = soc_info->gpio_num;
150 if (ngpio == 0) {
David Brownell474dad52008-12-07 11:46:23 -0800151 pr_err("GPIO setup: how many GPIOs?\n");
152 return -EINVAL;
153 }
154
155 if (WARN_ON(DAVINCI_N_GPIO < ngpio))
156 ngpio = DAVINCI_N_GPIO;
157
Cyril Chemparathyb8d44292010-05-07 17:06:32 -0400158 gpio_base = ioremap(soc_info->gpio_base, SZ_4K);
159 if (WARN_ON(!gpio_base))
160 return -ENOMEM;
161
David Brownell474dad52008-12-07 11:46:23 -0800162 for (i = 0, base = 0; base < ngpio; i++, base += 32) {
David Brownelldce11152008-09-07 23:41:04 -0700163 chips[i].chip.label = "DaVinci";
164
165 chips[i].chip.direction_input = davinci_direction_in;
166 chips[i].chip.get = davinci_gpio_get;
167 chips[i].chip.direction_output = davinci_direction_out;
168 chips[i].chip.set = davinci_gpio_set;
169
170 chips[i].chip.base = base;
David Brownell474dad52008-12-07 11:46:23 -0800171 chips[i].chip.ngpio = ngpio - base;
David Brownelldce11152008-09-07 23:41:04 -0700172 if (chips[i].chip.ngpio > 32)
173 chips[i].chip.ngpio = 32;
174
Cyril Chemparathyb27b6d02010-05-01 18:37:55 -0400175 spin_lock_init(&chips[i].lock);
176
Cyril Chemparathyc12f4152010-05-01 18:37:53 -0400177 regs = gpio2regs(base);
178 chips[i].regs = regs;
179 chips[i].set_data = &regs->set_data;
180 chips[i].clr_data = &regs->clr_data;
181 chips[i].in_data = &regs->in_data;
David Brownelldce11152008-09-07 23:41:04 -0700182
183 gpiochip_add(&chips[i].chip);
184 }
185
Cyril Chemparathyc12f4152010-05-01 18:37:53 -0400186 soc_info->gpio_ctlrs = chips;
187 soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
188
Kevin Hilmandc756022009-05-11 11:04:53 -0700189 davinci_gpio_irq_setup();
David Brownelldce11152008-09-07 23:41:04 -0700190 return 0;
191}
192pure_initcall(davinci_gpio_setup);
193
194/*--------------------------------------------------------------------------*/
195/*
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100196 * We expect irqs will normally be set up as input pins, but they can also be
197 * used as output pins ... which is convenient for testing.
198 *
David Brownell474dad52008-12-07 11:46:23 -0800199 * NOTE: The first few GPIOs also have direct INTC hookups in addition
David Brownell7a360712009-06-25 17:01:31 -0700200 * to their GPIOBNK0 irq, with a bit less overhead.
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100201 *
David Brownell474dad52008-12-07 11:46:23 -0800202 * All those INTC hookups (direct, plus several IRQ banks) can also
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100203 * serve as EDMA event triggers.
204 */
205
Lennert Buytenhek23265442010-11-29 10:27:27 +0100206static void gpio_irq_disable(struct irq_data *d)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100207{
Lennert Buytenhek23265442010-11-29 10:27:27 +0100208 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100209 u32 mask = (u32) irq_data_get_irq_handler_data(d);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100210
211 __raw_writel(mask, &g->clr_falling);
212 __raw_writel(mask, &g->clr_rising);
213}
214
Lennert Buytenhek23265442010-11-29 10:27:27 +0100215static void gpio_irq_enable(struct irq_data *d)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100216{
Lennert Buytenhek23265442010-11-29 10:27:27 +0100217 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100218 u32 mask = (u32) irq_data_get_irq_handler_data(d);
Thomas Gleixner5093aec2011-03-24 12:47:04 +0100219 unsigned status = irqd_get_trigger_type(d);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100220
David Brownelldf4aab42009-05-04 13:14:27 -0700221 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
222 if (!status)
223 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
224
225 if (status & IRQ_TYPE_EDGE_FALLING)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100226 __raw_writel(mask, &g->set_falling);
David Brownelldf4aab42009-05-04 13:14:27 -0700227 if (status & IRQ_TYPE_EDGE_RISING)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100228 __raw_writel(mask, &g->set_rising);
229}
230
Lennert Buytenhek23265442010-11-29 10:27:27 +0100231static int gpio_irq_type(struct irq_data *d, unsigned trigger)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100232{
Lennert Buytenhek23265442010-11-29 10:27:27 +0100233 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100234 u32 mask = (u32) irq_data_get_irq_handler_data(d);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100235
236 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
237 return -EINVAL;
238
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100239 return 0;
240}
241
242static struct irq_chip gpio_irqchip = {
243 .name = "GPIO",
Lennert Buytenhek23265442010-11-29 10:27:27 +0100244 .irq_enable = gpio_irq_enable,
245 .irq_disable = gpio_irq_disable,
246 .irq_set_type = gpio_irq_type,
Thomas Gleixner5093aec2011-03-24 12:47:04 +0100247 .flags = IRQCHIP_SET_TYPE_MASKED,
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100248};
249
250static void
251gpio_irq_handler(unsigned irq, struct irq_desc *desc)
252{
Thomas Gleixner74164012011-06-06 11:51:43 +0200253 struct davinci_gpio_regs __iomem *g;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100254 u32 mask = 0xffff;
Ido Yarivf299bb92011-07-12 00:03:11 +0300255 struct davinci_gpio_controller *d;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100256
Ido Yarivf299bb92011-07-12 00:03:11 +0300257 d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
258 g = (struct davinci_gpio_regs __iomem *)d->regs;
Thomas Gleixner74164012011-06-06 11:51:43 +0200259
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100260 /* we only care about one bank */
261 if (irq & 1)
262 mask <<= 16;
263
264 /* temporarily mask (level sensitive) parent IRQ */
Lennert Buytenhek23265442010-11-29 10:27:27 +0100265 desc->irq_data.chip->irq_mask(&desc->irq_data);
266 desc->irq_data.chip->irq_ack(&desc->irq_data);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100267 while (1) {
268 u32 status;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100269 int n;
270 int res;
271
272 /* ack any irqs */
273 status = __raw_readl(&g->intstat) & mask;
274 if (!status)
275 break;
276 __raw_writel(status, &g->intstat);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100277
278 /* now demux them to the right lowlevel handler */
Ido Yarivf299bb92011-07-12 00:03:11 +0300279 n = d->irq_base;
280 if (irq & 1) {
281 n += 16;
282 status >>= 16;
283 }
284
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100285 while (status) {
286 res = ffs(status);
287 n += res;
Dmitry Baryshkovd8aa0252008-10-09 13:36:24 +0100288 generic_handle_irq(n - 1);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100289 status >>= res;
290 }
291 }
Lennert Buytenhek23265442010-11-29 10:27:27 +0100292 desc->irq_data.chip->irq_unmask(&desc->irq_data);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100293 /* now it may re-trigger */
294}
295
David Brownell7a360712009-06-25 17:01:31 -0700296static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
297{
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400298 struct davinci_gpio_controller *d = chip2controller(chip);
David Brownell7a360712009-06-25 17:01:31 -0700299
300 if (d->irq_base >= 0)
301 return d->irq_base + offset;
302 else
303 return -ENODEV;
304}
305
306static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
307{
308 struct davinci_soc_info *soc_info = &davinci_soc_info;
309
310 /* NOTE: we assume for now that only irqs in the first gpio_chip
311 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
312 */
313 if (offset < soc_info->gpio_unbanked)
314 return soc_info->gpio_irq + offset;
315 else
316 return -ENODEV;
317}
318
Lennert Buytenhek23265442010-11-29 10:27:27 +0100319static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger)
David Brownell7a360712009-06-25 17:01:31 -0700320{
Lennert Buytenhek23265442010-11-29 10:27:27 +0100321 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100322 u32 mask = (u32) irq_data_get_irq_handler_data(d);
David Brownell7a360712009-06-25 17:01:31 -0700323
324 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
325 return -EINVAL;
326
327 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
328 ? &g->set_falling : &g->clr_falling);
329 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
330 ? &g->set_rising : &g->clr_rising);
331
332 return 0;
333}
334
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100335/*
David Brownell474dad52008-12-07 11:46:23 -0800336 * NOTE: for suspend/resume, probably best to make a platform_device with
337 * suspend_late/resume_resume calls hooking into results of the set_wake()
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100338 * calls ... so if no gpios are wakeup events the clock can be disabled,
339 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
David Brownell474dad52008-12-07 11:46:23 -0800340 * (dm6446) can be set appropriately for GPIOV33 pins.
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100341 */
342
343static int __init davinci_gpio_irq_setup(void)
344{
345 unsigned gpio, irq, bank;
346 struct clk *clk;
David Brownell474dad52008-12-07 11:46:23 -0800347 u32 binten = 0;
Mark A. Greera9949552009-04-15 12:40:35 -0700348 unsigned ngpio, bank_irq;
349 struct davinci_soc_info *soc_info = &davinci_soc_info;
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400350 struct davinci_gpio_regs __iomem *g;
David Brownell474dad52008-12-07 11:46:23 -0800351
Mark A. Greera9949552009-04-15 12:40:35 -0700352 ngpio = soc_info->gpio_num;
353
354 bank_irq = soc_info->gpio_irq;
355 if (bank_irq == 0) {
David Brownell474dad52008-12-07 11:46:23 -0800356 printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
357 return -EINVAL;
358 }
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100359
360 clk = clk_get(NULL, "gpio");
361 if (IS_ERR(clk)) {
362 printk(KERN_ERR "Error %ld getting gpio clock?\n",
363 PTR_ERR(clk));
David Brownell474dad52008-12-07 11:46:23 -0800364 return PTR_ERR(clk);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100365 }
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100366 clk_enable(clk);
367
David Brownell7a360712009-06-25 17:01:31 -0700368 /* Arrange gpio_to_irq() support, handling either direct IRQs or
369 * banked IRQs. Having GPIOs in the first GPIO bank use direct
370 * IRQs, while the others use banked IRQs, would need some setup
371 * tweaks to recognize hardware which can do that.
372 */
373 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
374 chips[bank].chip.to_irq = gpio_to_irq_banked;
375 chips[bank].irq_base = soc_info->gpio_unbanked
376 ? -EINVAL
377 : (soc_info->intc_irq_num + gpio);
378 }
379
380 /*
381 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
382 * controller only handling trigger modes. We currently assume no
383 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
384 */
385 if (soc_info->gpio_unbanked) {
386 static struct irq_chip gpio_irqchip_unbanked;
387
388 /* pass "bank 0" GPIO IRQs to AINTC */
389 chips[0].chip.to_irq = gpio_to_irq_unbanked;
390 binten = BIT(0);
391
392 /* AINTC handles mask/unmask; GPIO handles triggering */
393 irq = bank_irq;
Thomas Gleixner5093aec2011-03-24 12:47:04 +0100394 gpio_irqchip_unbanked = *irq_get_chip(irq);
David Brownell7a360712009-06-25 17:01:31 -0700395 gpio_irqchip_unbanked.name = "GPIO-AINTC";
Lennert Buytenhek23265442010-11-29 10:27:27 +0100396 gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked;
David Brownell7a360712009-06-25 17:01:31 -0700397
398 /* default trigger: both edges */
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400399 g = gpio2regs(0);
David Brownell7a360712009-06-25 17:01:31 -0700400 __raw_writel(~0, &g->set_falling);
401 __raw_writel(~0, &g->set_rising);
402
403 /* set the direct IRQs up to use that irqchip */
404 for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100405 irq_set_chip(irq, &gpio_irqchip_unbanked);
406 irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
407 irq_set_chip_data(irq, (__force void *)g);
Thomas Gleixner5093aec2011-03-24 12:47:04 +0100408 irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
David Brownell7a360712009-06-25 17:01:31 -0700409 }
410
411 goto done;
412 }
413
414 /*
415 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
416 * then chain through our own handler.
417 */
David Brownell474dad52008-12-07 11:46:23 -0800418 for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
419 gpio < ngpio;
420 bank++, bank_irq++) {
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100421 unsigned i;
422
David Brownell7a360712009-06-25 17:01:31 -0700423 /* disabled by default, enabled only as needed */
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400424 g = gpio2regs(gpio);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100425 __raw_writel(~0, &g->clr_falling);
426 __raw_writel(~0, &g->clr_rising);
427
428 /* set up all irqs in this bank */
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100429 irq_set_chained_handler(bank_irq, gpio_irq_handler);
Ido Yarivf299bb92011-07-12 00:03:11 +0300430
431 /*
432 * Each chip handles 32 gpios, and each irq bank consists of 16
433 * gpio irqs. Pass the irq bank's corresponding controller to
434 * the chained irq handler.
435 */
436 irq_set_handler_data(bank_irq, &chips[gpio / 32]);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100437
David Brownell474dad52008-12-07 11:46:23 -0800438 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100439 irq_set_chip(irq, &gpio_irqchip);
440 irq_set_chip_data(irq, (__force void *)g);
441 irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
442 irq_set_handler(irq, handle_simple_irq);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100443 set_irq_flags(irq, IRQF_VALID);
444 }
David Brownell474dad52008-12-07 11:46:23 -0800445
446 binten |= BIT(bank);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100447 }
448
David Brownell7a360712009-06-25 17:01:31 -0700449done:
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100450 /* BINTEN -- per-bank interrupt enable. genirq would also let these
451 * bits be set/cleared dynamically.
452 */
Cyril Chemparathyb8d44292010-05-07 17:06:32 -0400453 __raw_writel(binten, gpio_base + 0x08);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100454
455 printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
456
457 return 0;
458}