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Paul Walmsley69d88a02008-03-18 10:02:50 +02001#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
2#define __ARCH_ARM_MACH_OMAP2_PRM_H
3
4/*
5 * OMAP2/3 Power/Reset Management (PRM) register definitions
6 *
7 * Copyright (C) 2007 Texas Instruments, Inc.
8 * Copyright (C) 2007 Nokia Corporation
9 *
10 * Written by Paul Walmsley
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include "prcm-common.h"
18
19#ifndef __ASSEMBLER__
20#define OMAP_PRM_REGADDR(module, reg) \
Russell Kinge8a91c92008-09-01 22:07:37 +010021 IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg))
Paul Walmsley69d88a02008-03-18 10:02:50 +020022#else
23#define OMAP2420_PRM_REGADDR(module, reg) \
24 IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
25#define OMAP2430_PRM_REGADDR(module, reg) \
26 IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
27#define OMAP34XX_PRM_REGADDR(module, reg) \
28 IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
29#endif
30
31/*
32 * Architecture-specific global PRM registers
Kalle Jokiniemidfa3d032008-05-06 10:33:01 +030033 * Use __raw_{read,write}l() with these registers.
Paul Walmsley69d88a02008-03-18 10:02:50 +020034 *
35 * With a few exceptions, these are the register names beginning with
36 * PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the
37 * IRQSTATUS and IRQENABLE bits.)
38 *
39 */
40
Tony Lindgrenc2d43e32008-07-03 12:24:38 +030041/* Global 24xx registers in GR_MOD (Same as OCP_MOD for 24xx) */
42#define OMAP24XX_PRCM_VOLTCTRL_OFFSET 0x0050
43#define OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET 0x0080
44
45/* 242x GR_MOD registers, use these only for assembly code */
46#define OMAP242X_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD, \
47 OMAP24XX_PRCM_VOLTCTRL_OFFSET)
48#define OMAP242X_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD, \
49 OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET)
50
51/* 243x GR_MOD registers, use these only for assembly code */
52#define OMAP243X_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD, \
53 OMAP24XX_PRCM_VOLTCTRL_OFFSET)
54#define OMAP243X_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD, \
55 OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET)
56
57/* These will disappear */
Paul Walmsley69d88a02008-03-18 10:02:50 +020058#define OMAP24XX_PRCM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0000)
59#define OMAP24XX_PRCM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0010)
60
61#define OMAP24XX_PRCM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
62#define OMAP24XX_PRCM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
63
Paul Walmsley69d88a02008-03-18 10:02:50 +020064#define OMAP24XX_PRCM_VOLTST OMAP_PRM_REGADDR(OCP_MOD, 0x0054)
65#define OMAP24XX_PRCM_CLKSRC_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0060)
66#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0070)
67#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0078)
68#define OMAP24XX_PRCM_CLKCFG_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0080)
69#define OMAP24XX_PRCM_CLKCFG_STATUS OMAP_PRM_REGADDR(OCP_MOD, 0x0084)
70#define OMAP24XX_PRCM_VOLTSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0090)
71#define OMAP24XX_PRCM_CLKSSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0094)
72#define OMAP24XX_PRCM_POLCTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0098)
73
74#define OMAP3430_PRM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0004)
75#define OMAP3430_PRM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0014)
76
77#define OMAP3430_PRM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
78#define OMAP3430_PRM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
79
80
81#define OMAP3430_PRM_VC_SMPS_SA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
82#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
83#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
84#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
85#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
86#define OMAP3430_PRM_VC_CH_CONF OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
87#define OMAP3430_PRM_VC_I2C_CFG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
88#define OMAP3430_PRM_VC_BYPASS_VAL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
89#define OMAP3430_PRM_RSTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
90#define OMAP3430_PRM_RSTTIME OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
91#define OMAP3430_PRM_RSTST OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
92#define OMAP3430_PRM_VOLTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
93#define OMAP3430_PRM_SRAM_PCHARGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
94#define OMAP3430_PRM_CLKSRC_CTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
95#define OMAP3430_PRM_VOLTSETUP1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
96#define OMAP3430_PRM_VOLTOFFSET OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
97#define OMAP3430_PRM_CLKSETUP OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
98#define OMAP3430_PRM_POLCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
99#define OMAP3430_PRM_VOLTSETUP2 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
100#define OMAP3430_PRM_VP1_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
101#define OMAP3430_PRM_VP1_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
102#define OMAP3430_PRM_VP1_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
103#define OMAP3430_PRM_VP1_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
104#define OMAP3430_PRM_VP1_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
105#define OMAP3430_PRM_VP1_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
106#define OMAP3430_PRM_VP2_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
107#define OMAP3430_PRM_VP2_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
108#define OMAP3430_PRM_VP2_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
109#define OMAP3430_PRM_VP2_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
110#define OMAP3430_PRM_VP2_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
111#define OMAP3430_PRM_VP2_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
112
113#define OMAP3430_PRM_CLKSEL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
114#define OMAP3430_PRM_CLKOUT_CTRL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
115
116/*
117 * Module specific PRM registers from PRM_BASE + domain offset
118 *
119 * Use prm_{read,write}_mod_reg() with these registers.
120 *
121 * With a few exceptions, these are the register names beginning with
122 * {PM,RM}_* on both architectures. (The exceptions are the IRQSTATUS
123 * and IRQENABLE bits.)
124 *
125 */
126
127/* Registers appearing on both 24xx and 34xx */
128
129#define RM_RSTCTRL 0x0050
130#define RM_RSTTIME 0x0054
131#define RM_RSTST 0x0058
132
133#define PM_WKEN 0x00a0
134#define PM_WKEN1 PM_WKEN
135#define PM_WKST 0x00b0
136#define PM_WKST1 PM_WKST
137#define PM_WKDEP 0x00c8
138#define PM_EVGENCTRL 0x00d4
139#define PM_EVGENONTIM 0x00d8
140#define PM_EVGENOFFTIM 0x00dc
141#define PM_PWSTCTRL 0x00e0
142#define PM_PWSTST 0x00e4
143
144#define OMAP3430_PM_MPUGRPSEL 0x00a4
145#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL
146
147#define OMAP3430_PM_IVAGRPSEL 0x00a8
148#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL
149
150#define OMAP3430_PM_PREPWSTST 0x00e8
151
152#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8
153#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
154
155
156/* Architecture-specific registers */
157
158#define OMAP24XX_PM_WKEN2 0x00a4
159#define OMAP24XX_PM_WKST2 0x00b4
160
161#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
162#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
163#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
164#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
165
166#ifndef __ASSEMBLER__
167
168/* Power/reset management domain register get/set */
Tony Lindgrena58caad2008-07-03 12:24:44 +0300169extern u32 prm_read_mod_reg(s16 module, u16 idx);
170extern void prm_write_mod_reg(u32 val, s16 module, u16 idx);
Tony Lindgrenff00fcc2008-07-03 12:24:44 +0300171extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
172
173/* Read-modify-write bits in a PRM register (by domain) */
174static inline u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
175{
176 return prm_rmw_mod_reg_bits(bits, bits, module, idx);
177}
178
179static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
180{
181 return prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
182}
Paul Walmsley69d88a02008-03-18 10:02:50 +0200183
184#endif
185
186/*
187 * Bits common to specific registers
188 *
189 * The 3430 register and bit names are generally used,
190 * since they tend to make more sense
191 */
192
193/* PM_EVGENONTIM_MPU */
194/* Named PM_EVEGENONTIM_MPU on the 24XX */
195#define OMAP_ONTIMEVAL_SHIFT 0
196#define OMAP_ONTIMEVAL_MASK (0xffffffff << 0)
197
198/* PM_EVGENOFFTIM_MPU */
199/* Named PM_EVEGENOFFTIM_MPU on the 24XX */
200#define OMAP_OFFTIMEVAL_SHIFT 0
201#define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0)
202
203/* PRM_CLKSETUP and PRCM_VOLTSETUP */
204/* Named PRCM_CLKSSETUP on the 24XX */
205#define OMAP_SETUP_TIME_SHIFT 0
206#define OMAP_SETUP_TIME_MASK (0xffff << 0)
207
208/* PRM_CLKSRC_CTRL */
209/* Named PRCM_CLKSRC_CTRL on the 24XX */
210#define OMAP_SYSCLKDIV_SHIFT 6
211#define OMAP_SYSCLKDIV_MASK (0x3 << 6)
212#define OMAP_AUTOEXTCLKMODE_SHIFT 3
213#define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3)
214#define OMAP_SYSCLKSEL_SHIFT 0
215#define OMAP_SYSCLKSEL_MASK (0x3 << 0)
216
217/* PM_EVGENCTRL_MPU */
218#define OMAP_OFFLOADMODE_SHIFT 3
219#define OMAP_OFFLOADMODE_MASK (0x3 << 3)
220#define OMAP_ONLOADMODE_SHIFT 1
221#define OMAP_ONLOADMODE_MASK (0x3 << 1)
222#define OMAP_ENABLE (1 << 0)
223
224/* PRM_RSTTIME */
225/* Named RM_RSTTIME_WKUP on the 24xx */
226#define OMAP_RSTTIME2_SHIFT 8
227#define OMAP_RSTTIME2_MASK (0x1f << 8)
228#define OMAP_RSTTIME1_SHIFT 0
229#define OMAP_RSTTIME1_MASK (0xff << 0)
230
231
232/* PRM_RSTCTRL */
233/* Named RM_RSTCTRL_WKUP on the 24xx */
234/* 2420 calls RST_DPLL3 'RST_DPLL' */
235#define OMAP_RST_DPLL3 (1 << 2)
236#define OMAP_RST_GS (1 << 1)
237
238
239/*
240 * Bits common to module-shared registers
241 *
242 * Not all registers of a particular type support all of these bits -
243 * check TRM if you are unsure
244 */
245
246/*
247 * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
248 *
249 * 2430: PM_PWSTST_MDM
250 *
251 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
252 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
253 * PM_PWSTST_NEON
254 */
255#define OMAP_INTRANSITION (1 << 20)
256
257
258/*
259 * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
260 *
261 * 2430: PM_PWSTST_MDM
262 *
263 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
264 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
265 * PM_PWSTST_NEON
266 */
267#define OMAP_POWERSTATEST_SHIFT 0
268#define OMAP_POWERSTATEST_MASK (0x3 << 0)
269
270/*
271 * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
272 * called 'COREWKUP_RST'
273 *
274 * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
275 * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
276 */
277#define OMAP_COREDOMAINWKUP_RST (1 << 3)
278
279/*
280 * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
281 *
282 * 2430: RM_RSTST_MDM
283 *
284 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
285 */
286#define OMAP_DOMAINWKUP_RST (1 << 2)
287
288/*
289 * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
290 * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
291 *
292 * 2430: RM_RSTST_MDM
293 *
294 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
295 */
296#define OMAP_GLOBALWARM_RST (1 << 1)
297#define OMAP_GLOBALCOLD_RST (1 << 0)
298
299/*
300 * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
301 * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
302 *
303 * 2430: PM_WKDEP_MDM
304 *
305 * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
306 * PM_WKDEP_PER
307 */
Paul Walmsley97171002008-08-19 11:08:40 +0300308#define OMAP_EN_WKUP_SHIFT 4
309#define OMAP_EN_WKUP_MASK (1 << 4)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200310
311/*
312 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
313 * PM_PWSTCTRL_DSP
314 *
315 * 2430: PM_PWSTCTRL_MDM
316 *
317 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
318 * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
319 * PM_PWSTCTRL_NEON
320 */
321#define OMAP_LOGICRETSTATE (1 << 2)
322
323/*
324 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
325 * PM_PWSTCTRL_DSP, PM_PWSTST_MPU
326 *
327 * 2430: PM_PWSTCTRL_MDM shared bits
328 *
329 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
330 * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
331 * PM_PWSTCTRL_NEON shared bits
332 */
333#define OMAP_POWERSTATE_SHIFT 0
334#define OMAP_POWERSTATE_MASK (0x3 << 0)
335
336
337#endif