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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/************************************************************************
ravinandan.arakali@neterion.com776bd202005-09-06 21:36:56 -07002 * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
Ramkrishna Vepa0c61ed52007-03-09 18:28:32 -08003 * Copyright(c) 2002-2007 Neterion Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07004
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 ************************************************************************/
13#ifndef _S2IO_H
14#define _S2IO_H
15
16#define TBD 0
17#define BIT(loc) (0x8000000000000000ULL >> (loc))
18#define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
19#define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
20
21#ifndef BOOL
22#define BOOL int
23#endif
24
25#ifndef TRUE
26#define TRUE 1
27#define FALSE 0
28#endif
29
30#undef SUCCESS
31#define SUCCESS 0
32#define FAILURE -1
Sivakumar Subramani19a60522007-01-31 13:30:49 -050033#define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL
34#define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100
Sivakumar Subramani9fc93a42007-02-24 01:57:32 -050035#define S2IO_BIT_RESET 1
36#define S2IO_BIT_SET 2
Ananda Rajubd1034f2006-04-21 19:20:22 -040037#define CHECKBIT(value, nbit) (value & (1 << nbit))
38
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -070039/* Maximum time to flicker LED when asked to identify NIC using ethtool */
40#define MAX_FLICKER_TIME 60000 /* 60 Secs */
41
Linus Torvalds1da177e2005-04-16 15:20:36 -070042/* Maximum outstanding splits to be configured into xena. */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -050043enum {
Linus Torvalds1da177e2005-04-16 15:20:36 -070044 XENA_ONE_SPLIT_TRANSACTION = 0,
45 XENA_TWO_SPLIT_TRANSACTION = 1,
46 XENA_THREE_SPLIT_TRANSACTION = 2,
47 XENA_FOUR_SPLIT_TRANSACTION = 3,
48 XENA_EIGHT_SPLIT_TRANSACTION = 4,
49 XENA_TWELVE_SPLIT_TRANSACTION = 5,
50 XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
51 XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
Ralf Baechle1ee6dd72007-01-31 14:09:29 -050052};
Linus Torvalds1da177e2005-04-16 15:20:36 -070053#define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
54
55/* OS concerned variables and constants */
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -070056#define WATCH_DOG_TIMEOUT 15*HZ
57#define EFILL 0x1234
58#define ALIGN_SIZE 127
59#define PCIX_COMMAND_REGISTER 0x62
Linus Torvalds1da177e2005-04-16 15:20:36 -070060
61/*
62 * Debug related variables.
63 */
64/* different debug levels. */
65#define ERR_DBG 0
66#define INIT_DBG 1
67#define INFO_DBG 2
68#define TX_DBG 3
69#define INTR_DBG 4
70
71/* Global variable that defines the present debug level of the driver. */
Adrian Bunk26df54b2006-01-14 03:09:40 +010072static int debug_level = ERR_DBG;
Linus Torvalds1da177e2005-04-16 15:20:36 -070073
74/* DEBUG message print. */
75#define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args)
76
Veena Parat491abf22007-07-23 02:37:14 -040077#ifndef DMA_ERROR_CODE
78#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
79#endif
80
Linus Torvalds1da177e2005-04-16 15:20:36 -070081/* Protocol assist features of the NIC */
82#define L3_CKSUM_OK 0xFFFF
83#define L4_CKSUM_OK 0xFFFF
84#define S2IO_JUMBO_SIZE 9600
85
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -070086/* Driver statistics maintained by driver */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -050087struct swStat {
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -070088 unsigned long long single_ecc_errs;
89 unsigned long long double_ecc_errs;
Ananda Rajubd1034f2006-04-21 19:20:22 -040090 unsigned long long parity_err_cnt;
91 unsigned long long serious_err_cnt;
92 unsigned long long soft_reset_cnt;
93 unsigned long long fifo_full_cnt;
94 unsigned long long ring_full_cnt;
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -050095 /* LRO statistics */
96 unsigned long long clubbed_frms_cnt;
97 unsigned long long sending_both;
98 unsigned long long outof_sequence_pkts;
99 unsigned long long flush_max_pkts;
100 unsigned long long sum_avg_pkts_aggregated;
101 unsigned long long num_aggregations;
Sreenivasa Honnurc53d4942007-05-10 04:18:54 -0400102 /* Other statistics */
103 unsigned long long mem_alloc_fail_cnt;
Veena Parat491abf22007-07-23 02:37:14 -0400104 unsigned long long pci_map_fail_cnt;
Sreenivasa Honnurc53d4942007-05-10 04:18:54 -0400105 unsigned long long watchdog_timer_cnt;
Sreenivasa Honnur491976b2007-05-10 04:22:25 -0400106 unsigned long long mem_allocated;
107 unsigned long long mem_freed;
108 unsigned long long link_up_cnt;
109 unsigned long long link_down_cnt;
110 unsigned long long link_up_time;
111 unsigned long long link_down_time;
112
113 /* Transfer Code statistics */
114 unsigned long long tx_buf_abort_cnt;
115 unsigned long long tx_desc_abort_cnt;
116 unsigned long long tx_parity_err_cnt;
117 unsigned long long tx_link_loss_cnt;
118 unsigned long long tx_list_proc_err_cnt;
119
120 unsigned long long rx_parity_err_cnt;
121 unsigned long long rx_abort_cnt;
122 unsigned long long rx_parity_abort_cnt;
123 unsigned long long rx_rda_fail_cnt;
124 unsigned long long rx_unkn_prot_cnt;
125 unsigned long long rx_fcs_err_cnt;
126 unsigned long long rx_buf_size_err_cnt;
127 unsigned long long rx_rxd_corrupt_cnt;
128 unsigned long long rx_unkn_err_cnt;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500129};
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700130
Ananda Rajubd1034f2006-04-21 19:20:22 -0400131/* Xpak releated alarm and warnings */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500132struct xpakStat {
Ananda Rajubd1034f2006-04-21 19:20:22 -0400133 u64 alarm_transceiver_temp_high;
134 u64 alarm_transceiver_temp_low;
135 u64 alarm_laser_bias_current_high;
136 u64 alarm_laser_bias_current_low;
137 u64 alarm_laser_output_power_high;
138 u64 alarm_laser_output_power_low;
139 u64 warn_transceiver_temp_high;
140 u64 warn_transceiver_temp_low;
141 u64 warn_laser_bias_current_high;
142 u64 warn_laser_bias_current_low;
143 u64 warn_laser_output_power_high;
144 u64 warn_laser_output_power_low;
145 u64 xpak_regs_stat;
146 u32 xpak_timer_count;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500147};
Ananda Rajubd1034f2006-04-21 19:20:22 -0400148
149
Linus Torvalds1da177e2005-04-16 15:20:36 -0700150/* The statistics block of Xena */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500151struct stat_block {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700152/* Tx MAC statistics counters. */
Al Viro107c3a72006-08-13 15:38:04 -0400153 __le32 tmac_data_octets;
154 __le32 tmac_frms;
155 __le64 tmac_drop_frms;
156 __le32 tmac_bcst_frms;
157 __le32 tmac_mcst_frms;
158 __le64 tmac_pause_ctrl_frms;
159 __le32 tmac_ucst_frms;
160 __le32 tmac_ttl_octets;
161 __le32 tmac_any_err_frms;
162 __le32 tmac_nucst_frms;
163 __le64 tmac_ttl_less_fb_octets;
164 __le64 tmac_vld_ip_octets;
165 __le32 tmac_drop_ip;
166 __le32 tmac_vld_ip;
167 __le32 tmac_rst_tcp;
168 __le32 tmac_icmp;
169 __le64 tmac_tcp;
170 __le32 reserved_0;
171 __le32 tmac_udp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700172
173/* Rx MAC Statistics counters. */
Al Viro107c3a72006-08-13 15:38:04 -0400174 __le32 rmac_data_octets;
175 __le32 rmac_vld_frms;
176 __le64 rmac_fcs_err_frms;
177 __le64 rmac_drop_frms;
178 __le32 rmac_vld_bcst_frms;
179 __le32 rmac_vld_mcst_frms;
180 __le32 rmac_out_rng_len_err_frms;
181 __le32 rmac_in_rng_len_err_frms;
182 __le64 rmac_long_frms;
183 __le64 rmac_pause_ctrl_frms;
184 __le64 rmac_unsup_ctrl_frms;
185 __le32 rmac_accepted_ucst_frms;
186 __le32 rmac_ttl_octets;
187 __le32 rmac_discarded_frms;
188 __le32 rmac_accepted_nucst_frms;
189 __le32 reserved_1;
190 __le32 rmac_drop_events;
191 __le64 rmac_ttl_less_fb_octets;
192 __le64 rmac_ttl_frms;
193 __le64 reserved_2;
194 __le32 rmac_usized_frms;
195 __le32 reserved_3;
196 __le32 rmac_frag_frms;
197 __le32 rmac_osized_frms;
198 __le32 reserved_4;
199 __le32 rmac_jabber_frms;
200 __le64 rmac_ttl_64_frms;
201 __le64 rmac_ttl_65_127_frms;
202 __le64 reserved_5;
203 __le64 rmac_ttl_128_255_frms;
204 __le64 rmac_ttl_256_511_frms;
205 __le64 reserved_6;
206 __le64 rmac_ttl_512_1023_frms;
207 __le64 rmac_ttl_1024_1518_frms;
208 __le32 rmac_ip;
209 __le32 reserved_7;
210 __le64 rmac_ip_octets;
211 __le32 rmac_drop_ip;
212 __le32 rmac_hdr_err_ip;
213 __le32 reserved_8;
214 __le32 rmac_icmp;
215 __le64 rmac_tcp;
216 __le32 rmac_err_drp_udp;
217 __le32 rmac_udp;
218 __le64 rmac_xgmii_err_sym;
219 __le64 rmac_frms_q0;
220 __le64 rmac_frms_q1;
221 __le64 rmac_frms_q2;
222 __le64 rmac_frms_q3;
223 __le64 rmac_frms_q4;
224 __le64 rmac_frms_q5;
225 __le64 rmac_frms_q6;
226 __le64 rmac_frms_q7;
227 __le16 rmac_full_q3;
228 __le16 rmac_full_q2;
229 __le16 rmac_full_q1;
230 __le16 rmac_full_q0;
231 __le16 rmac_full_q7;
232 __le16 rmac_full_q6;
233 __le16 rmac_full_q5;
234 __le16 rmac_full_q4;
235 __le32 reserved_9;
236 __le32 rmac_pause_cnt;
237 __le64 rmac_xgmii_data_err_cnt;
238 __le64 rmac_xgmii_ctrl_err_cnt;
239 __le32 rmac_err_tcp;
240 __le32 rmac_accepted_ip;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700241
242/* PCI/PCI-X Read transaction statistics. */
Al Viro107c3a72006-08-13 15:38:04 -0400243 __le32 new_rd_req_cnt;
244 __le32 rd_req_cnt;
245 __le32 rd_rtry_cnt;
246 __le32 new_rd_req_rtry_cnt;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700247
248/* PCI/PCI-X Write/Read transaction statistics. */
Al Viro107c3a72006-08-13 15:38:04 -0400249 __le32 wr_req_cnt;
250 __le32 wr_rtry_rd_ack_cnt;
251 __le32 new_wr_req_rtry_cnt;
252 __le32 new_wr_req_cnt;
253 __le32 wr_disc_cnt;
254 __le32 wr_rtry_cnt;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700255
256/* PCI/PCI-X Write / DMA Transaction statistics. */
Al Viro107c3a72006-08-13 15:38:04 -0400257 __le32 txp_wr_cnt;
258 __le32 rd_rtry_wr_ack_cnt;
259 __le32 txd_wr_cnt;
260 __le32 txd_rd_cnt;
261 __le32 rxd_wr_cnt;
262 __le32 rxd_rd_cnt;
263 __le32 rxf_wr_cnt;
264 __le32 txf_rd_cnt;
raghavendra.koushik@neterion.com7ba013a2005-08-03 12:29:20 -0700265
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700266/* Tx MAC statistics overflow counters. */
Al Viro107c3a72006-08-13 15:38:04 -0400267 __le32 tmac_data_octets_oflow;
268 __le32 tmac_frms_oflow;
269 __le32 tmac_bcst_frms_oflow;
270 __le32 tmac_mcst_frms_oflow;
271 __le32 tmac_ucst_frms_oflow;
272 __le32 tmac_ttl_octets_oflow;
273 __le32 tmac_any_err_frms_oflow;
274 __le32 tmac_nucst_frms_oflow;
275 __le64 tmac_vlan_frms;
276 __le32 tmac_drop_ip_oflow;
277 __le32 tmac_vld_ip_oflow;
278 __le32 tmac_rst_tcp_oflow;
279 __le32 tmac_icmp_oflow;
280 __le32 tpa_unknown_protocol;
281 __le32 tmac_udp_oflow;
282 __le32 reserved_10;
283 __le32 tpa_parse_failure;
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700284
285/* Rx MAC Statistics overflow counters. */
Al Viro107c3a72006-08-13 15:38:04 -0400286 __le32 rmac_data_octets_oflow;
287 __le32 rmac_vld_frms_oflow;
288 __le32 rmac_vld_bcst_frms_oflow;
289 __le32 rmac_vld_mcst_frms_oflow;
290 __le32 rmac_accepted_ucst_frms_oflow;
291 __le32 rmac_ttl_octets_oflow;
292 __le32 rmac_discarded_frms_oflow;
293 __le32 rmac_accepted_nucst_frms_oflow;
294 __le32 rmac_usized_frms_oflow;
295 __le32 rmac_drop_events_oflow;
296 __le32 rmac_frag_frms_oflow;
297 __le32 rmac_osized_frms_oflow;
298 __le32 rmac_ip_oflow;
299 __le32 rmac_jabber_frms_oflow;
300 __le32 rmac_icmp_oflow;
301 __le32 rmac_drop_ip_oflow;
302 __le32 rmac_err_drp_udp_oflow;
303 __le32 rmac_udp_oflow;
304 __le32 reserved_11;
305 __le32 rmac_pause_cnt_oflow;
306 __le64 rmac_ttl_1519_4095_frms;
307 __le64 rmac_ttl_4096_8191_frms;
308 __le64 rmac_ttl_8192_max_frms;
309 __le64 rmac_ttl_gt_max_frms;
310 __le64 rmac_osized_alt_frms;
311 __le64 rmac_jabber_alt_frms;
312 __le64 rmac_gt_max_alt_frms;
313 __le64 rmac_vlan_frms;
314 __le32 rmac_len_discard;
315 __le32 rmac_fcs_discard;
316 __le32 rmac_pf_discard;
317 __le32 rmac_da_discard;
318 __le32 rmac_red_discard;
319 __le32 rmac_rts_discard;
320 __le32 reserved_12;
321 __le32 rmac_ingm_full_discard;
322 __le32 reserved_13;
323 __le32 rmac_accepted_ip_oflow;
324 __le32 reserved_14;
325 __le32 link_fault_cnt;
Ananda Rajubd1034f2006-04-21 19:20:22 -0400326 u8 buffer[20];
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500327 struct swStat sw_stat;
328 struct xpakStat xpak_stat;
329};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700330
Sivakumar Subramani926930b2007-02-24 01:59:39 -0500331/* Default value for 'vlan_strip_tag' configuration parameter */
332#define NO_STRIP_IN_PROMISC 2
333
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700334/*
335 * Structures representing different init time configuration
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336 * parameters of the NIC.
337 */
338
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700339#define MAX_TX_FIFOS 8
340#define MAX_RX_RINGS 8
341
Sreenivasa Honnur0cec35e2007-05-10 04:06:28 -0400342#define MAX_RX_DESC_1 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 127 )
343#define MAX_RX_DESC_2 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
344#define MAX_RX_DESC_3 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
345#define MAX_TX_DESC (MAX_AVAILABLE_TXDS)
346
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700347/* FIFO mappings for all possible number of fifos configured */
Adrian Bunk26df54b2006-01-14 03:09:40 +0100348static int fifo_map[][MAX_TX_FIFOS] = {
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700349 {0, 0, 0, 0, 0, 0, 0, 0},
350 {0, 0, 0, 0, 1, 1, 1, 1},
351 {0, 0, 0, 1, 1, 1, 2, 2},
352 {0, 0, 1, 1, 2, 2, 3, 3},
353 {0, 0, 1, 1, 2, 2, 3, 4},
354 {0, 0, 1, 1, 2, 3, 4, 5},
355 {0, 0, 1, 2, 3, 4, 5, 6},
356 {0, 1, 2, 3, 4, 5, 6, 7},
357};
358
Linus Torvalds1da177e2005-04-16 15:20:36 -0700359/* Maintains Per FIFO related information. */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500360struct tx_fifo_config {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700361#define MAX_AVAILABLE_TXDS 8192
362 u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */
363/* Priority definition */
364#define TX_FIFO_PRI_0 0 /*Highest */
365#define TX_FIFO_PRI_1 1
366#define TX_FIFO_PRI_2 2
367#define TX_FIFO_PRI_3 3
368#define TX_FIFO_PRI_4 4
369#define TX_FIFO_PRI_5 5
370#define TX_FIFO_PRI_6 6
371#define TX_FIFO_PRI_7 7 /*lowest */
372 u8 fifo_priority; /* specifies pointer level for FIFO */
373 /* user should not set twos fifos with same pri */
374 u8 f_no_snoop;
375#define NO_SNOOP_TXD 0x01
376#define NO_SNOOP_TXD_BUFFER 0x02
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500377};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378
379
380/* Maintains per Ring related information */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500381struct rx_ring_config {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700382 u32 num_rxd; /*No of RxDs per Rx Ring */
383#define RX_RING_PRI_0 0 /* highest */
384#define RX_RING_PRI_1 1
385#define RX_RING_PRI_2 2
386#define RX_RING_PRI_3 3
387#define RX_RING_PRI_4 4
388#define RX_RING_PRI_5 5
389#define RX_RING_PRI_6 6
390#define RX_RING_PRI_7 7 /* lowest */
391
392 u8 ring_priority; /*Specifies service priority of ring */
393 /* OSM should not set any two rings with same priority */
394 u8 ring_org; /*Organization of ring */
395#define RING_ORG_BUFF1 0x01
396#define RX_RING_ORG_BUFF3 0x03
397#define RX_RING_ORG_BUFF5 0x05
398
399 u8 f_no_snoop;
400#define NO_SNOOP_RXD 0x01
401#define NO_SNOOP_RXD_BUFFER 0x02
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500402};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700403
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700404/* This structure provides contains values of the tunable parameters
405 * of the H/W
Linus Torvalds1da177e2005-04-16 15:20:36 -0700406 */
407struct config_param {
408/* Tx Side */
409 u32 tx_fifo_num; /*Number of Tx FIFOs */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700410
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700411 u8 fifo_mapping[MAX_TX_FIFOS];
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500412 struct tx_fifo_config tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700413 u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */
414 u64 tx_intr_type;
415 /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
416
417/* Rx Side */
418 u32 rx_ring_num; /*Number of receive rings */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700419#define MAX_RX_BLOCKS_PER_RING 150
420
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500421 struct rx_ring_config rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
raghavendra.koushik@neterion.comb6e3f982005-08-03 12:38:01 -0700422 u8 bimodal; /*Flag for setting bimodal interrupts*/
Linus Torvalds1da177e2005-04-16 15:20:36 -0700423
424#define HEADER_ETHERNET_II_802_3_SIZE 14
425#define HEADER_802_2_SIZE 3
426#define HEADER_SNAP_SIZE 5
427#define HEADER_VLAN_SIZE 4
428
429#define MIN_MTU 46
430#define MAX_PYLD 1500
431#define MAX_MTU (MAX_PYLD+18)
432#define MAX_MTU_VLAN (MAX_PYLD+22)
433#define MAX_PYLD_JUMBO 9600
434#define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
435#define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700436 u16 bus_speed;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700437};
438
439/* Structure representing MAC Addrs */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500440struct mac_addr {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700441 u8 mac_addr[ETH_ALEN];
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500442};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700443
444/* Structure that represent every FIFO element in the BAR1
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700445 * Address location.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500447struct TxFIFO_element {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448 u64 TxDL_Pointer;
449
450 u64 List_Control;
451#define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
452#define TX_FIFO_FIRST_LIST BIT(14)
453#define TX_FIFO_LAST_LIST BIT(15)
454#define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
455#define TX_FIFO_SPECIAL_FUNC BIT(23)
456#define TX_FIFO_DS_NO_SNOOP BIT(31)
457#define TX_FIFO_BUFF_NO_SNOOP BIT(30)
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500458};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700459
460/* Tx descriptor structure */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500461struct TxD {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700462 u64 Control_1;
463/* bit mask */
464#define TXD_LIST_OWN_XENA BIT(7)
465#define TXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
466#define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE))
467#define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12)
468#define TXD_GATHER_CODE (BIT(22) | BIT(23))
469#define TXD_GATHER_CODE_FIRST BIT(22)
470#define TXD_GATHER_CODE_LAST BIT(23)
471#define TXD_TCP_LSO_EN BIT(30)
472#define TXD_UDP_COF_EN BIT(31)
Ananda Rajufed5ecc2005-11-14 15:25:08 -0500473#define TXD_UFO_EN BIT(31) | BIT(30)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700474#define TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
Ananda Rajufed5ecc2005-11-14 15:25:08 -0500475#define TXD_UFO_MSS(val) vBIT(val,34,14)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700476#define TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
477
478 u64 Control_2;
479#define TXD_TX_CKO_CONTROL (BIT(5)|BIT(6)|BIT(7))
480#define TXD_TX_CKO_IPV4_EN BIT(5)
481#define TXD_TX_CKO_TCP_EN BIT(6)
482#define TXD_TX_CKO_UDP_EN BIT(7)
483#define TXD_VLAN_ENABLE BIT(15)
484#define TXD_VLAN_TAG(val) vBIT(val,16,16)
485#define TXD_INT_NUMBER(val) vBIT(val,34,6)
486#define TXD_INT_TYPE_PER_LIST BIT(47)
487#define TXD_INT_TYPE_UTILZ BIT(46)
488#define TXD_SET_MARKER vBIT(0x6,0,4)
489
490 u64 Buffer_Pointer;
491 u64 Host_Control; /* reserved for host */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500492};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700493
494/* Structure to hold the phy and virt addr of every TxDL. */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500495struct list_info_hold {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700496 dma_addr_t list_phy_addr;
497 void *list_virt_addr;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500498};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700499
Ananda Rajuda6971d2005-10-31 16:55:31 -0500500/* Rx descriptor structure for 1 buffer mode */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500501struct RxD_t {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700502 u64 Host_Control; /* reserved for host */
503 u64 Control_1;
504#define RXD_OWN_XENA BIT(7)
505#define RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
506#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
507#define RXD_FRAME_PROTO_IPV4 BIT(27)
508#define RXD_FRAME_PROTO_IPV6 BIT(28)
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700509#define RXD_FRAME_IP_FRAG BIT(29)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700510#define RXD_FRAME_PROTO_TCP BIT(30)
511#define RXD_FRAME_PROTO_UDP BIT(31)
512#define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
513#define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF)
514#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
515
516 u64 Control_2;
raghavendra.koushik@neterion.com5e25b9d2005-08-03 12:27:09 -0700517#define THE_RXD_MARK 0x3
518#define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2)
519#define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62)
520
Linus Torvalds1da177e2005-04-16 15:20:36 -0700521#define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
522#define SET_VLAN_TAG(val) vBIT(val,48,16)
523#define SET_NUM_TAG(val) vBIT(val,16,32)
524
Ananda Rajuda6971d2005-10-31 16:55:31 -0500525
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500526};
Ananda Rajuda6971d2005-10-31 16:55:31 -0500527/* Rx descriptor structure for 1 buffer mode */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500528struct RxD1 {
529 struct RxD_t h;
Ananda Rajuda6971d2005-10-31 16:55:31 -0500530
531#define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14)
532#define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14)
533#define RXD_GET_BUFFER0_SIZE_1(_Control_2) \
534 (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48)
535 u64 Buffer0_ptr;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500536};
Ananda Rajuda6971d2005-10-31 16:55:31 -0500537/* Rx descriptor structure for 3 or 2 buffer mode */
538
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500539struct RxD3 {
540 struct RxD_t h;
Ananda Rajuda6971d2005-10-31 16:55:31 -0500541
542#define MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14)
543#define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16)
544#define MASK_BUFFER2_SIZE_3 vBIT(0xFFFF,32,16)
545#define SET_BUFFER0_SIZE_3(val) vBIT(val,8,8)
546#define SET_BUFFER1_SIZE_3(val) vBIT(val,16,16)
547#define SET_BUFFER2_SIZE_3(val) vBIT(val,32,16)
548#define RXD_GET_BUFFER0_SIZE_3(Control_2) \
549 (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48)
550#define RXD_GET_BUFFER1_SIZE_3(Control_2) \
551 (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32)
552#define RXD_GET_BUFFER2_SIZE_3(Control_2) \
553 (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700554#define BUF0_LEN 40
555#define BUF1_LEN 1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700556
557 u64 Buffer0_ptr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700558 u64 Buffer1_ptr;
559 u64 Buffer2_ptr;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500560};
Ananda Rajuda6971d2005-10-31 16:55:31 -0500561
Linus Torvalds1da177e2005-04-16 15:20:36 -0700562
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700563/* Structure that represents the Rx descriptor block which contains
Linus Torvalds1da177e2005-04-16 15:20:36 -0700564 * 128 Rx descriptors.
565 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500566struct RxD_block {
Ananda Rajuda6971d2005-10-31 16:55:31 -0500567#define MAX_RXDS_PER_BLOCK_1 127
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500568 struct RxD1 rxd[MAX_RXDS_PER_BLOCK_1];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700569
570 u64 reserved_0;
571#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700572 u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
Linus Torvalds1da177e2005-04-16 15:20:36 -0700573 * Rxd in this blk */
574 u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
575 u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700576 * the upper 32 bits should
Linus Torvalds1da177e2005-04-16 15:20:36 -0700577 * be 0 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500578};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700579
Linus Torvalds1da177e2005-04-16 15:20:36 -0700580#define SIZE_OF_BLOCK 4096
581
Sivakumar Subramani19a60522007-01-31 13:30:49 -0500582#define RXD_MODE_1 0 /* One Buffer mode */
Veena Parat6d517a22007-07-23 02:20:51 -0400583#define RXD_MODE_3B 1 /* Two Buffer mode */
Ananda Rajuda6971d2005-10-31 16:55:31 -0500584
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700585/* Structure to hold virtual addresses of Buf0 and Buf1 in
Linus Torvalds1da177e2005-04-16 15:20:36 -0700586 * 2buf mode. */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500587struct buffAdd {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700588 void *ba_0_org;
589 void *ba_1_org;
590 void *ba_0;
591 void *ba_1;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500592};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700593
594/* Structure which stores all the MAC control parameters */
595
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700596/* This structure stores the offset of the RxD in the ring
597 * from which the Rx Interrupt processor can start picking
Linus Torvalds1da177e2005-04-16 15:20:36 -0700598 * up the RxDs for processing.
599 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500600struct rx_curr_get_info {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700601 u32 block_index;
602 u32 offset;
603 u32 ring_len;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500604};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700605
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500606struct rx_curr_put_info {
607 u32 block_index;
608 u32 offset;
609 u32 ring_len;
610};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700611
612/* This structure stores the offset of the TxDl in the FIFO
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700613 * from which the Tx Interrupt processor can start picking
Linus Torvalds1da177e2005-04-16 15:20:36 -0700614 * up the TxDLs for send complete interrupt processing.
615 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500616struct tx_curr_get_info {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700617 u32 offset;
618 u32 fifo_len;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500619};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700620
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500621struct tx_curr_put_info {
622 u32 offset;
623 u32 fifo_len;
624};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700625
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500626struct rxd_info {
Ananda Rajuda6971d2005-10-31 16:55:31 -0500627 void *virt_addr;
628 dma_addr_t dma_addr;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500629};
Ananda Rajuda6971d2005-10-31 16:55:31 -0500630
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700631/* Structure that holds the Phy and virt addresses of the Blocks */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500632struct rx_block_info {
Ananda Rajuda6971d2005-10-31 16:55:31 -0500633 void *block_virt_addr;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700634 dma_addr_t block_dma_addr;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500635 struct rxd_info *rxds;
636};
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700637
638/* Ring specific structure */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500639struct ring_info {
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700640 /* The ring number */
641 int ring_no;
642
643 /*
644 * Place holders for the virtual and physical addresses of
645 * all the Rx Blocks
646 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500647 struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING];
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700648 int block_count;
649 int pkt_cnt;
650
651 /*
652 * Put pointer info which indictes which RxD has to be replenished
653 * with a new buffer.
654 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500655 struct rx_curr_put_info rx_curr_put_info;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700656
657 /*
658 * Get pointer info which indictes which is the last RxD that was
659 * processed by the driver.
660 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500661 struct rx_curr_get_info rx_curr_get_info;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700662
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700663 /* Index to the absolute position of the put pointer of Rx ring */
664 int put_pos;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700665
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700666 /* Buffer Address store. */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500667 struct buffAdd **ba;
668 struct s2io_nic *nic;
669};
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700670
671/* Fifo specific structure */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500672struct fifo_info {
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700673 /* FIFO number */
674 int fifo_no;
675
676 /* Maximum TxDs per TxDL */
677 int max_txds;
678
679 /* Place holder of all the TX List's Phy and Virt addresses. */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500680 struct list_info_hold *list_info;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700681
682 /*
683 * Current offset within the tx FIFO where driver would write
684 * new Tx frame
685 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500686 struct tx_curr_put_info tx_curr_put_info;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700687
688 /*
689 * Current offset within tx FIFO from where the driver would start freeing
690 * the buffers
691 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500692 struct tx_curr_get_info tx_curr_get_info;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700693
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500694 struct s2io_nic *nic;
695};
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700696
Adrian Bunk47bdd712006-06-30 18:25:18 +0200697/* Information related to the Tx and Rx FIFOs and Rings of Xena
Linus Torvalds1da177e2005-04-16 15:20:36 -0700698 * is maintained in this structure.
699 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500700struct mac_info {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700701/* tx side stuff */
702 /* logical pointer of start of each Tx FIFO */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500703 struct TxFIFO_element __iomem *tx_FIFO_start[MAX_TX_FIFOS];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700704
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700705 /* Fifo specific structure */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500706 struct fifo_info fifos[MAX_TX_FIFOS];
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700707
ravinandan.arakali@neterion.com776bd202005-09-06 21:36:56 -0700708 /* Save virtual address of TxD page with zero DMA addr(if any) */
709 void *zerodma_virt_addr;
710
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700711/* rx side stuff */
712 /* Ring specific structure */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500713 struct ring_info rings[MAX_RX_RINGS];
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700714
715 u16 rmac_pause_time;
716 u16 mc_pause_threshold_q0q3;
717 u16 mc_pause_threshold_q4q7;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700718
719 void *stats_mem; /* orignal pointer to allocated mem */
720 dma_addr_t stats_mem_phy; /* Physical address of the stat block */
721 u32 stats_mem_sz;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500722 struct stat_block *stats_info; /* Logical address of the stat block */
723};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700724
725/* structure representing the user defined MAC addresses */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500726struct usr_addr {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700727 char addr[ETH_ALEN];
728 int usage_cnt;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500729};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700730
Linus Torvalds1da177e2005-04-16 15:20:36 -0700731/* Default Tunable parameters of the NIC. */
Ananda Raju9dc737a2006-04-21 19:05:41 -0400732#define DEFAULT_FIFO_0_LEN 4096
733#define DEFAULT_FIFO_1_7_LEN 512
Ananda Rajuc92ca042006-04-21 19:18:03 -0400734#define SMALL_BLK_CNT 30
735#define LARGE_BLK_CNT 100
Linus Torvalds1da177e2005-04-16 15:20:36 -0700736
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400737/*
738 * Structure to keep track of the MSI-X vectors and the corresponding
739 * argument registered against each vector
740 */
741#define MAX_REQUESTED_MSI_X 17
742struct s2io_msix_entry
743{
744 u16 vector;
745 u16 entry;
746 void *arg;
747
748 u8 type;
749#define MSIX_FIFO_TYPE 1
750#define MSIX_RING_TYPE 2
751
752 u8 in_use;
753#define MSIX_REGISTERED_SUCCESS 0xAA
754};
755
756struct msix_info_st {
757 u64 addr;
758 u64 data;
759};
760
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500761/* Data structure to represent a LRO session */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500762struct lro {
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500763 struct sk_buff *parent;
Ananda Raju75c30b12006-07-24 19:55:09 -0400764 struct sk_buff *last_frag;
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500765 u8 *l2h;
766 struct iphdr *iph;
767 struct tcphdr *tcph;
768 u32 tcp_next_seq;
Al Virobd4f3ae2007-02-09 16:40:15 +0000769 __be32 tcp_ack;
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500770 int total_len;
771 int frags_len;
772 int sg_num;
773 int in_use;
Al Virobd4f3ae2007-02-09 16:40:15 +0000774 __be16 window;
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500775 u32 cur_tsval;
776 u32 cur_tsecr;
777 u8 saw_ts;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500778};
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500779
Linus Torvalds1da177e2005-04-16 15:20:36 -0700780/* Structure representing one instance of the NIC */
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700781struct s2io_nic {
Ananda Rajuda6971d2005-10-31 16:55:31 -0500782 int rxd_mode;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700783 /*
784 * Count of packets to be processed in a given iteration, it will be indicated
785 * by the quota field of the device structure when NAPI is enabled.
786 */
787 int pkts_to_process;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700788 struct net_device *dev;
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700789 struct napi_struct napi;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500790 struct mac_info mac_control;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700791 struct config_param config;
792 struct pci_dev *pdev;
793 void __iomem *bar0;
794 void __iomem *bar1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700795#define MAX_MAC_SUPPORTED 16
796#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
797
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500798 struct mac_addr def_mac_addr[MAX_MAC_SUPPORTED];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700799
800 struct net_device_stats stats;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700801 int high_dma_flag;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700802 int device_enabled_once;
803
Ananda Rajuc92ca042006-04-21 19:18:03 -0400804 char name[60];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700805 struct tasklet_struct task;
806 volatile unsigned long tasklet_status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807
raghavendra.koushik@neterion.com25fff882005-08-03 12:34:11 -0700808 /* Timer that handles I/O errors/exceptions */
809 struct timer_list alarm_timer;
810
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700811 /* Space to back up the PCI config space */
812 u32 config_space[256 / sizeof(u32)];
813
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814 atomic_t rx_bufs_left[MAX_RX_RINGS];
815
816 spinlock_t tx_lock;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700817 spinlock_t put_lock;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700818
819#define PROMISC 1
820#define ALL_MULTI 2
821
822#define MAX_ADDRS_SUPPORTED 64
823 u16 usr_addr_count;
824 u16 mc_addr_count;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500825 struct usr_addr usr_addrs[MAX_ADDRS_SUPPORTED];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700826
827 u16 m_cast_flg;
828 u16 all_multi_pos;
829 u16 promisc_flg;
830
Linus Torvalds1da177e2005-04-16 15:20:36 -0700831 /* Id timer, used to blink NIC to physically identify NIC. */
832 struct timer_list id_timer;
833
834 /* Restart timer, used to restart NIC if the device is stuck and
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700835 * a schedule task that will set the correct Link state once the
Linus Torvalds1da177e2005-04-16 15:20:36 -0700836 * NIC's PHY has stabilized after a state change.
837 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700838 struct work_struct rst_timer_task;
839 struct work_struct set_link_task;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700840
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700841 /* Flag that can be used to turn on or turn off the Rx checksum
Linus Torvalds1da177e2005-04-16 15:20:36 -0700842 * offload feature.
843 */
844 int rx_csum;
845
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700846 /* after blink, the adapter must be restored with original
Linus Torvalds1da177e2005-04-16 15:20:36 -0700847 * values.
848 */
849 u64 adapt_ctrl_org;
850
851 /* Last known link state. */
852 u16 last_link_state;
853#define LINK_DOWN 1
854#define LINK_UP 2
855
Linus Torvalds1da177e2005-04-16 15:20:36 -0700856 int task_flag;
Sreenivasa Honnur491976b2007-05-10 04:22:25 -0400857 unsigned long long start_time;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700858#define CARD_DOWN 1
859#define CARD_UP 2
860 atomic_t card_state;
861 volatile unsigned long link_state;
raghavendra.koushik@neterion.combe3a6b02005-08-03 12:35:55 -0700862 struct vlan_group *vlgrp;
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400863#define MSIX_FLG 0xA5
864 struct msix_entry *entries;
865 struct s2io_msix_entry *s2io_entries;
Ananda Rajue6a8fee2006-07-06 23:58:23 -0700866 char desc[MAX_REQUESTED_MSI_X][25];
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400867
Ananda Rajuc92ca042006-04-21 19:18:03 -0400868 int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
869
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400870 struct msix_info_st msix_info[0x3f];
871
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700872#define XFRAME_I_DEVICE 1
873#define XFRAME_II_DEVICE 2
874 u8 device_type;
raghavendra.koushik@neterion.combe3a6b02005-08-03 12:35:55 -0700875
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500876#define MAX_LRO_SESSIONS 32
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500877 struct lro lro0_n[MAX_LRO_SESSIONS];
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500878 unsigned long clubbed_frms_cnt;
879 unsigned long sending_both;
880 u8 lro;
881 u16 lro_max_aggr_per_sess;
882
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400883#define INTA 0
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400884#define MSI_X 2
885 u8 intr_type;
886
raghavendra.koushik@neterion.com7ba013a2005-08-03 12:29:20 -0700887 spinlock_t rx_lock;
888 atomic_t isr_cnt;
Ananda Rajufed5ecc2005-11-14 15:25:08 -0500889 u64 *ufo_in_band_v;
Sivakumar Subramani19a60522007-01-31 13:30:49 -0500890#define VPD_STRING_LEN 80
891 u8 product_name[VPD_STRING_LEN];
892 u8 serial_num[VPD_STRING_LEN];
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700893};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700894
895#define RESET_ERROR 1;
896#define CMD_ERROR 2;
897
898/* OS related system calls */
899#ifndef readq
900static inline u64 readq(void __iomem *addr)
901{
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700902 u64 ret = 0;
903 ret = readl(addr + 4);
Andrew Morton7ef24b62005-08-25 17:14:46 -0700904 ret <<= 32;
905 ret |= readl(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700906
907 return ret;
908}
909#endif
910
911#ifndef writeq
912static inline void writeq(u64 val, void __iomem *addr)
913{
914 writel((u32) (val), addr);
915 writel((u32) (val >> 32), (addr + 4));
916}
Ananda Rajuc92ca042006-04-21 19:18:03 -0400917#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700918
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400919/*
920 * Some registers have to be written in a particular order to
921 * expect correct hardware operation. The macro SPECIAL_REG_WRITE
922 * is used to perform such ordered writes. Defines UF (Upper First)
Ananda Rajuc92ca042006-04-21 19:18:03 -0400923 * and LF (Lower First) will be used to specify the required write order.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700924 */
925#define UF 1
926#define LF 2
927static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
928{
Ananda Rajuc92ca042006-04-21 19:18:03 -0400929 u32 ret;
930
Linus Torvalds1da177e2005-04-16 15:20:36 -0700931 if (order == LF) {
932 writel((u32) (val), addr);
Ananda Rajuc92ca042006-04-21 19:18:03 -0400933 ret = readl(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700934 writel((u32) (val >> 32), (addr + 4));
Ananda Rajuc92ca042006-04-21 19:18:03 -0400935 ret = readl(addr + 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700936 } else {
937 writel((u32) (val >> 32), (addr + 4));
Ananda Rajuc92ca042006-04-21 19:18:03 -0400938 ret = readl(addr + 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700939 writel((u32) (val), addr);
Ananda Rajuc92ca042006-04-21 19:18:03 -0400940 ret = readl(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700941 }
942}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700943
944/* Interrupt related values of Xena */
945
946#define ENABLE_INTRS 1
947#define DISABLE_INTRS 2
948
949/* Highest level interrupt blocks */
950#define TX_PIC_INTR (0x0001<<0)
951#define TX_DMA_INTR (0x0001<<1)
952#define TX_MAC_INTR (0x0001<<2)
953#define TX_XGXS_INTR (0x0001<<3)
954#define TX_TRAFFIC_INTR (0x0001<<4)
955#define RX_PIC_INTR (0x0001<<5)
956#define RX_DMA_INTR (0x0001<<6)
957#define RX_MAC_INTR (0x0001<<7)
958#define RX_XGXS_INTR (0x0001<<8)
959#define RX_TRAFFIC_INTR (0x0001<<9)
960#define MC_INTR (0x0001<<10)
961#define ENA_ALL_INTRS ( TX_PIC_INTR | \
962 TX_DMA_INTR | \
963 TX_MAC_INTR | \
964 TX_XGXS_INTR | \
965 TX_TRAFFIC_INTR | \
966 RX_PIC_INTR | \
967 RX_DMA_INTR | \
968 RX_MAC_INTR | \
969 RX_XGXS_INTR | \
970 RX_TRAFFIC_INTR | \
971 MC_INTR )
972
973/* Interrupt masks for the general interrupt mask register */
974#define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL
975
976#define TXPIC_INT_M BIT(0)
977#define TXDMA_INT_M BIT(1)
978#define TXMAC_INT_M BIT(2)
979#define TXXGXS_INT_M BIT(3)
980#define TXTRAFFIC_INT_M BIT(8)
981#define PIC_RX_INT_M BIT(32)
982#define RXDMA_INT_M BIT(33)
983#define RXMAC_INT_M BIT(34)
984#define MC_INT_M BIT(35)
985#define RXXGXS_INT_M BIT(36)
986#define RXTRAFFIC_INT_M BIT(40)
987
988/* PIC level Interrupts TODO*/
989
990/* DMA level Inressupts */
991#define TXDMA_PFC_INT_M BIT(0)
992#define TXDMA_PCC_INT_M BIT(2)
993
994/* PFC block interrupts */
995#define PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO full */
996
997/* PCC block interrupts. */
998#define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
999 PCC_FB_ECC Error. */
1000
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -07001001#define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001002/*
1003 * Prototype declaration.
1004 */
1005static int __devinit s2io_init_nic(struct pci_dev *pdev,
1006 const struct pci_device_id *pre);
1007static void __devexit s2io_rem_nic(struct pci_dev *pdev);
1008static int init_shared_mem(struct s2io_nic *sp);
1009static void free_shared_mem(struct s2io_nic *sp);
1010static int init_nic(struct s2io_nic *nic);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001011static void rx_intr_handler(struct ring_info *ring_data);
1012static void tx_intr_handler(struct fifo_info *fifo_data);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001013static void alarm_intr_handler(struct s2io_nic *sp);
1014
1015static int s2io_starter(void);
Sivakumar Subramani19a60522007-01-31 13:30:49 -05001016static void s2io_closer(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001017static void s2io_tx_watchdog(struct net_device *dev);
1018static void s2io_tasklet(unsigned long dev_addr);
1019static void s2io_set_multicast(struct net_device *dev);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001020static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp);
1021static void s2io_link(struct s2io_nic * sp, int link);
1022static void s2io_reset(struct s2io_nic * sp);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001023static int s2io_poll(struct napi_struct *napi, int budget);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001024static void s2io_init_pci(struct s2io_nic * sp);
Adrian Bunk26df54b2006-01-14 03:09:40 +01001025static int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
raghavendra.koushik@neterion.com25fff882005-08-03 12:34:11 -07001026static void s2io_alarm_handle(unsigned long data);
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -04001027static irqreturn_t
David Howells7d12e782006-10-05 14:55:46 +01001028s2io_msix_ring_handle(int irq, void *dev_id);
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -04001029static irqreturn_t
David Howells7d12e782006-10-05 14:55:46 +01001030s2io_msix_fifo_handle(int irq, void *dev_id);
1031static irqreturn_t s2io_isr(int irq, void *dev_id);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001032static int verify_xena_quiescence(struct s2io_nic *sp);
Jeff Garzik7282d492006-09-13 14:30:00 -04001033static const struct ethtool_ops netdev_ethtool_ops;
David Howellsc4028952006-11-22 14:57:56 +00001034static void s2io_set_link(struct work_struct *work);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001035static int s2io_set_swapper(struct s2io_nic * sp);
1036static void s2io_card_down(struct s2io_nic *nic);
1037static int s2io_card_up(struct s2io_nic *nic);
Sivakumar Subramani9fc93a42007-02-24 01:57:32 -05001038static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
1039 int bit_state);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001040static int s2io_add_isr(struct s2io_nic * sp);
1041static void s2io_rem_isr(struct s2io_nic * sp);
Sivakumar Subramani19a60522007-01-31 13:30:49 -05001042
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001043static void restore_xmsi_data(struct s2io_nic *nic);
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -05001044
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001045static int
1046s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
1047 struct RxD_t *rxdp, struct s2io_nic *sp);
1048static void clear_lro_session(struct lro *lro);
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -05001049static void queue_rx_frame(struct sk_buff *skb);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001050static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro);
1051static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
1052 struct sk_buff *skb, u32 tcp_len);
Sivakumar Subramani9fc93a42007-02-24 01:57:32 -05001053static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring);
Ananda Rajub41477f2006-07-24 19:52:49 -04001054
Linas Vepstasd796fdb2007-05-14 18:37:30 -05001055static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
1056 pci_channel_state_t state);
1057static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev);
1058static void s2io_io_resume(struct pci_dev *pdev);
1059
Ananda Raju75c30b12006-07-24 19:55:09 -04001060#define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size
1061#define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size
1062#define s2io_offload_type(skb) skb_shinfo(skb)->gso_type
1063
Ananda Rajub41477f2006-07-24 19:52:49 -04001064#define S2IO_PARM_INT(X, def_val) \
1065 static unsigned int X = def_val;\
1066 module_param(X , uint, 0);
1067
Linus Torvalds1da177e2005-04-16 15:20:36 -07001068#endif /* _S2IO_H */