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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 drivers/net/tulip/tulip.h
3
4 Copyright 2000,2001 The Linux Kernel Team
5 Written/copyright 1994-2001 by Donald Becker.
6
7 This software may be used and distributed according to the terms
8 of the GNU General Public License, incorporated herein by reference.
9
10 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
11 for more information on this driver, or visit the project
12 Web page at http://sourceforge.net/projects/tulip/
13
14*/
15
16#ifndef __NET_TULIP_H__
17#define __NET_TULIP_H__
18
Linus Torvalds1da177e2005-04-16 15:20:36 -070019#include <linux/kernel.h>
20#include <linux/types.h>
21#include <linux/spinlock.h>
22#include <linux/netdevice.h>
23#include <linux/timer.h>
24#include <linux/delay.h>
Jean Delvare6473d162007-03-06 02:45:12 -080025#include <linux/pci.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070026#include <asm/io.h>
27#include <asm/irq.h>
28
29
30
31/* undefine, or define to various debugging levels (>4 == obscene levels) */
32#define TULIP_DEBUG 1
33
Linus Torvalds1da177e2005-04-16 15:20:36 -070034#ifdef CONFIG_TULIP_MMIO
Grant Grundler7f2b1242006-09-08 11:15:39 -070035#define TULIP_BAR 1 /* CBMA */
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#else
Grant Grundler7f2b1242006-09-08 11:15:39 -070037#define TULIP_BAR 0 /* CBIO */
Linus Torvalds1da177e2005-04-16 15:20:36 -070038#endif
39
40
41
42struct tulip_chip_table {
43 char *chip_name;
44 int io_size;
45 int valid_intrs; /* CSR7 interrupt enable settings */
46 int flags;
Francois Romieu0bb3cf72006-09-08 11:15:38 -070047 void (*media_timer) (unsigned long);
David Howellsc4028952006-11-22 14:57:56 +000048 work_func_t media_task;
Linus Torvalds1da177e2005-04-16 15:20:36 -070049};
50
51
52enum tbl_flag {
53 HAS_MII = 0x0001,
54 HAS_MEDIA_TABLE = 0x0002,
55 CSR12_IN_SROM = 0x0004,
56 ALWAYS_CHECK_MII = 0x0008,
57 HAS_ACPI = 0x0010,
58 MC_HASH_ONLY = 0x0020, /* Hash-only multicast filter. */
59 HAS_PNICNWAY = 0x0080,
60 HAS_NWAY = 0x0040, /* Uses internal NWay xcvr. */
61 HAS_INTR_MITIGATION = 0x0100,
62 IS_ASIX = 0x0200,
63 HAS_8023X = 0x0400,
64 COMET_MAC_ADDR = 0x0800,
65 HAS_PCI_MWI = 0x1000,
66 HAS_PHY_IRQ = 0x2000,
67 HAS_SWAPPED_SEEPROM = 0x4000,
68 NEEDS_FAKE_MEDIA_TABLE = 0x8000,
69};
70
71
72/* chip types. careful! order is VERY IMPORTANT here, as these
73 * are used throughout the driver as indices into arrays */
74/* Note 21142 == 21143. */
75enum chips {
76 DC21040 = 0,
77 DC21041 = 1,
78 DC21140 = 2,
79 DC21142 = 3, DC21143 = 3,
80 LC82C168,
81 MX98713,
82 MX98715,
83 MX98725,
84 AX88140,
85 PNIC2,
86 COMET,
87 COMPEX9881,
88 I21145,
89 DM910X,
90 CONEXANT,
Linus Torvalds1da177e2005-04-16 15:20:36 -070091};
92
93
94enum MediaIs {
95 MediaIsFD = 1,
96 MediaAlwaysFD = 2,
97 MediaIsMII = 4,
98 MediaIsFx = 8,
99 MediaIs100 = 16
100};
101
102
103/* Offsets to the Command and Status Registers, "CSRs". All accesses
104 must be longword instructions and quadword aligned. */
105enum tulip_offsets {
106 CSR0 = 0,
107 CSR1 = 0x08,
108 CSR2 = 0x10,
109 CSR3 = 0x18,
110 CSR4 = 0x20,
111 CSR5 = 0x28,
112 CSR6 = 0x30,
113 CSR7 = 0x38,
114 CSR8 = 0x40,
115 CSR9 = 0x48,
116 CSR10 = 0x50,
117 CSR11 = 0x58,
118 CSR12 = 0x60,
119 CSR13 = 0x68,
120 CSR14 = 0x70,
121 CSR15 = 0x78,
122};
123
124/* register offset and bits for CFDD PCI config reg */
125enum pci_cfg_driver_reg {
126 CFDD = 0x40,
127 CFDD_Sleep = (1 << 31),
128 CFDD_Snooze = (1 << 30),
129};
130
131#define RxPollInt (RxIntr|RxNoBuf|RxDied|RxJabber)
132
133/* The bits in the CSR5 status registers, mostly interrupt sources. */
134enum status_bits {
135 TimerInt = 0x800,
Valerie Henson1ddb9862007-03-12 02:31:33 -0700136 SystemError = 0x2000,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137 TPLnkFail = 0x1000,
138 TPLnkPass = 0x10,
139 NormalIntr = 0x10000,
140 AbnormalIntr = 0x8000,
141 RxJabber = 0x200,
142 RxDied = 0x100,
143 RxNoBuf = 0x80,
144 RxIntr = 0x40,
145 TxFIFOUnderflow = 0x20,
Grant Grundler7f2b1242006-09-08 11:15:39 -0700146 RxErrIntr = 0x10,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147 TxJabber = 0x08,
148 TxNoBuf = 0x04,
149 TxDied = 0x02,
150 TxIntr = 0x01,
151};
152
153/* bit mask for CSR5 TX/RX process state */
154#define CSR5_TS 0x00700000
155#define CSR5_RS 0x000e0000
156
157enum tulip_mode_bits {
158 TxThreshold = (1 << 22),
159 FullDuplex = (1 << 9),
160 TxOn = 0x2000,
161 AcceptBroadcast = 0x0100,
162 AcceptAllMulticast = 0x0080,
163 AcceptAllPhys = 0x0040,
164 AcceptRunt = 0x0008,
165 RxOn = 0x0002,
166 RxTx = (TxOn | RxOn),
167};
168
169
170enum tulip_busconfig_bits {
171 MWI = (1 << 24),
172 MRL = (1 << 23),
173 MRM = (1 << 21),
174 CALShift = 14,
175 BurstLenShift = 8,
176};
177
178
179/* The Tulip Rx and Tx buffer descriptors. */
180struct tulip_rx_desc {
181 s32 status;
182 s32 length;
183 u32 buffer1;
184 u32 buffer2;
185};
186
187
188struct tulip_tx_desc {
189 s32 status;
190 s32 length;
191 u32 buffer1;
192 u32 buffer2; /* We use only buffer 1. */
193};
194
195
196enum desc_status_bits {
Grant Grundler7f2b1242006-09-08 11:15:39 -0700197 DescOwned = 0x80000000,
198 DescWholePkt = 0x60000000,
199 DescEndPkt = 0x40000000,
200 DescStartPkt = 0x20000000,
201 DescEndRing = 0x02000000,
202 DescUseLink = 0x01000000,
203 RxDescFatalErr = 0x008000,
204 RxWholePkt = 0x00000300,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700205};
206
207
208enum t21143_csr6_bits {
209 csr6_sc = (1<<31),
210 csr6_ra = (1<<30),
211 csr6_ign_dest_msb = (1<<26),
212 csr6_mbo = (1<<25),
213 csr6_scr = (1<<24), /* scramble mode flag: can't be set */
214 csr6_pcs = (1<<23), /* Enables PCS functions (symbol mode requires csr6_ps be set) default is set */
215 csr6_ttm = (1<<22), /* Transmit Threshold Mode, set for 10baseT, 0 for 100BaseTX */
216 csr6_sf = (1<<21), /* Store and forward. If set ignores TR bits */
217 csr6_hbd = (1<<19), /* Heart beat disable. Disables SQE function in 10baseT */
218 csr6_ps = (1<<18), /* Port Select. 0 (defualt) = 10baseT, 1 = 100baseTX: can't be set */
219 csr6_ca = (1<<17), /* Collision Offset Enable. If set uses special algorithm in low collision situations */
220 csr6_trh = (1<<15), /* Transmit Threshold high bit */
221 csr6_trl = (1<<14), /* Transmit Threshold low bit */
222
223 /***************************************************************
224 * This table shows transmit threshold values based on media *
225 * and these two registers (from PNIC1 & 2 docs) Note: this is *
226 * all meaningless if sf is set. *
227 ***************************************************************/
228
229 /***********************************
230 * (trh,trl) * 100BaseTX * 10BaseT *
231 ***********************************
232 * (0,0) * 128 * 72 *
233 * (0,1) * 256 * 96 *
234 * (1,0) * 512 * 128 *
235 * (1,1) * 1024 * 160 *
236 ***********************************/
237
238 csr6_fc = (1<<12), /* Forces a collision in next transmission (for testing in loopback mode) */
239 csr6_om_int_loop = (1<<10), /* internal (FIFO) loopback flag */
240 csr6_om_ext_loop = (1<<11), /* external (PMD) loopback flag */
241 /* set both and you get (PHY) loopback */
242 csr6_fd = (1<<9), /* Full duplex mode, disables hearbeat, no loopback */
243 csr6_pm = (1<<7), /* Pass All Multicast */
244 csr6_pr = (1<<6), /* Promiscuous mode */
245 csr6_sb = (1<<5), /* Start(1)/Stop(0) backoff counter */
246 csr6_if = (1<<4), /* Inverse Filtering, rejects only addresses in address table: can't be set */
247 csr6_pb = (1<<3), /* Pass Bad Frames, (1) causes even bad frames to be passed on */
248 csr6_ho = (1<<2), /* Hash-only filtering mode: can't be set */
249 csr6_hp = (1<<0), /* Hash/Perfect Receive Filtering Mode: can't be set */
250
251 csr6_mask_capture = (csr6_sc | csr6_ca),
252 csr6_mask_defstate = (csr6_mask_capture | csr6_mbo),
253 csr6_mask_hdcap = (csr6_mask_defstate | csr6_hbd | csr6_ps),
254 csr6_mask_hdcaptt = (csr6_mask_hdcap | csr6_trh | csr6_trl),
255 csr6_mask_fullcap = (csr6_mask_hdcaptt | csr6_fd),
256 csr6_mask_fullpromisc = (csr6_pr | csr6_pm),
257 csr6_mask_filters = (csr6_hp | csr6_ho | csr6_if),
258 csr6_mask_100bt = (csr6_scr | csr6_pcs | csr6_hbd),
259};
260
261
262/* Keep the ring sizes a power of two for efficiency.
263 Making the Tx ring too large decreases the effectiveness of channel
264 bonding and packet priority.
265 There are no ill effects from too-large receive rings. */
266
267#define TX_RING_SIZE 32
Jeff Garzikf3b197a2006-05-26 21:39:03 -0400268#define RX_RING_SIZE 128
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269#define MEDIA_MASK 31
270
271#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
272
273#define TULIP_MIN_CACHE_LINE 8 /* in units of 32-bit words */
274
275#if defined(__sparc__) || defined(__hppa__)
276/* The UltraSparc PCI controllers will disconnect at every 64-byte
277 * crossing anyways so it makes no sense to tell Tulip to burst
278 * any more than that.
279 */
280#define TULIP_MAX_CACHE_LINE 16 /* in units of 32-bit words */
281#else
282#define TULIP_MAX_CACHE_LINE 32 /* in units of 32-bit words */
283#endif
284
285
286/* Ring-wrap flag in length field, use for last ring entry.
287 0x01000000 means chain on buffer2 address,
288 0x02000000 means use the ring start address in CSR2/3.
289 Note: Some work-alike chips do not function correctly in chained mode.
290 The ASIX chip works only in chained mode.
291 Thus we indicates ring mode, but always write the 'next' field for
292 chained mode as well.
293*/
294#define DESC_RING_WRAP 0x02000000
295
296
297#define EEPROM_SIZE 512 /* 2 << EEPROM_ADDRLEN */
298
299
300#define RUN_AT(x) (jiffies + (x))
301
302#if defined(__i386__) /* AKA get_unaligned() */
303#define get_u16(ptr) (*(u16 *)(ptr))
304#else
305#define get_u16(ptr) (((u8*)(ptr))[0] + (((u8*)(ptr))[1]<<8))
306#endif
307
308struct medialeaf {
309 u8 type;
310 u8 media;
311 unsigned char *leafdata;
312};
313
314
315struct mediatable {
316 u16 defaultmedia;
317 u8 leafcount;
318 u8 csr12dir; /* General purpose pin directions. */
319 unsigned has_mii:1;
320 unsigned has_nonmii:1;
321 unsigned has_reset:6;
322 u32 csr15dir;
323 u32 csr15val; /* 21143 NWay setting. */
324 struct medialeaf mleaf[0];
325};
326
327
328struct mediainfo {
329 struct mediainfo *next;
330 int info_type;
331 int index;
332 unsigned char *info;
333};
334
335struct ring_info {
336 struct sk_buff *skb;
337 dma_addr_t mapping;
338};
339
340
341struct tulip_private {
342 const char *product_name;
343 struct net_device *next_module;
344 struct tulip_rx_desc *rx_ring;
345 struct tulip_tx_desc *tx_ring;
346 dma_addr_t rx_ring_dma;
347 dma_addr_t tx_ring_dma;
348 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
349 struct ring_info tx_buffers[TX_RING_SIZE];
350 /* The addresses of receive-in-place skbuffs. */
351 struct ring_info rx_buffers[RX_RING_SIZE];
352 u16 setup_frame[96]; /* Pseudo-Tx frame to init address table. */
353 int chip_id;
354 int revision;
355 int flags;
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700356 struct napi_struct napi;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700357 struct net_device_stats stats;
358 struct timer_list timer; /* Media selection timer. */
359 struct timer_list oom_timer; /* Out of memory timer. */
360 u32 mc_filter[2];
361 spinlock_t lock;
362 spinlock_t mii_lock;
363 unsigned int cur_rx, cur_tx; /* The next free ring entry */
364 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
365
366#ifdef CONFIG_TULIP_NAPI_HW_MITIGATION
367 int mit_on;
368#endif
369 unsigned int full_duplex:1; /* Full-duplex operation requested. */
370 unsigned int full_duplex_lock:1;
371 unsigned int fake_addr:1; /* Multiport board faked address. */
372 unsigned int default_port:4; /* Last dev->if_port value. */
373 unsigned int media2:4; /* Secondary monitored media port. */
374 unsigned int medialock:1; /* Don't sense media type. */
375 unsigned int mediasense:1; /* Media sensing in progress. */
376 unsigned int nway:1, nwayset:1; /* 21143 internal NWay. */
Francois Romieu0bb3cf72006-09-08 11:15:38 -0700377 unsigned int timeout_recovery:1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378 unsigned int csr0; /* CSR0 setting. */
379 unsigned int csr6; /* Current CSR6 control settings. */
380 unsigned char eeprom[EEPROM_SIZE]; /* Serial EEPROM contents. */
381 void (*link_change) (struct net_device * dev, int csr5);
382 u16 sym_advertise, mii_advertise; /* NWay capabilities advertised. */
383 u16 lpar; /* 21143 Link partner ability. */
384 u16 advertising[4];
385 signed char phys[4], mii_cnt; /* MII device addresses. */
386 struct mediatable *mtable;
387 int cur_index; /* Current media index. */
388 int saved_if_port;
389 struct pci_dev *pdev;
390 int ttimer;
391 int susp_rx;
392 unsigned long nir;
393 void __iomem *base_addr;
394 int csr12_shadow;
395 int pad0; /* Used for 8-byte alignment */
Francois Romieu0bb3cf72006-09-08 11:15:38 -0700396 struct work_struct media_work;
David Howellsc4028952006-11-22 14:57:56 +0000397 struct net_device *dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700398};
399
400
401struct eeprom_fixup {
402 char *name;
403 unsigned char addr0;
404 unsigned char addr1;
405 unsigned char addr2;
406 u16 newtable[32]; /* Max length below. */
407};
408
409
410/* 21142.c */
411extern u16 t21142_csr14[];
David Howellsc4028952006-11-22 14:57:56 +0000412void t21142_media_task(struct work_struct *work);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700413void t21142_start_nway(struct net_device *dev);
414void t21142_lnk_change(struct net_device *dev, int csr5);
415
416
417/* PNIC2.c */
418void pnic2_lnk_change(struct net_device *dev, int csr5);
419void pnic2_timer(unsigned long data);
420void pnic2_start_nway(struct net_device *dev);
421void pnic2_lnk_change(struct net_device *dev, int csr5);
422
423/* eeprom.c */
424void tulip_parse_eeprom(struct net_device *dev);
425int tulip_read_eeprom(struct net_device *dev, int location, int addr_len);
426
427/* interrupt.c */
428extern unsigned int tulip_max_interrupt_work;
429extern int tulip_rx_copybreak;
David Howells7d12e782006-10-05 14:55:46 +0100430irqreturn_t tulip_interrupt(int irq, void *dev_instance);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431int tulip_refill_rx(struct net_device *dev);
432#ifdef CONFIG_TULIP_NAPI
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700433int tulip_poll(struct napi_struct *napi, int budget);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700434#endif
435
436
437/* media.c */
438int tulip_mdio_read(struct net_device *dev, int phy_id, int location);
439void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int value);
440void tulip_select_media(struct net_device *dev, int startup);
441int tulip_check_duplex(struct net_device *dev);
442void tulip_find_mii (struct net_device *dev, int board_idx);
443
444/* pnic.c */
445void pnic_do_nway(struct net_device *dev);
446void pnic_lnk_change(struct net_device *dev, int csr5);
447void pnic_timer(unsigned long data);
448
449/* timer.c */
David Howellsc4028952006-11-22 14:57:56 +0000450void tulip_media_task(struct work_struct *work);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700451void mxic_timer(unsigned long data);
452void comet_timer(unsigned long data);
453
454/* tulip_core.c */
455extern int tulip_debug;
456extern const char * const medianame[];
457extern const char tulip_media_cap[];
458extern struct tulip_chip_table tulip_tbl[];
459void oom_timer(unsigned long data);
460extern u8 t21040_csr13[];
461
462static inline void tulip_start_rxtx(struct tulip_private *tp)
463{
464 void __iomem *ioaddr = tp->base_addr;
465 iowrite32(tp->csr6 | RxTx, ioaddr + CSR6);
466 barrier();
467 (void) ioread32(ioaddr + CSR6); /* mmio sync */
468}
469
470static inline void tulip_stop_rxtx(struct tulip_private *tp)
471{
472 void __iomem *ioaddr = tp->base_addr;
473 u32 csr6 = ioread32(ioaddr + CSR6);
474
475 if (csr6 & RxTx) {
476 unsigned i=1300/10;
477 iowrite32(csr6 & ~RxTx, ioaddr + CSR6);
478 barrier();
479 /* wait until in-flight frame completes.
480 * Max time @ 10BT: 1500*8b/10Mbps == 1200us (+ 100us margin)
481 * Typically expect this loop to end in < 50 us on 100BT.
482 */
483 while (--i && (ioread32(ioaddr + CSR5) & (CSR5_TS|CSR5_RS)))
484 udelay(10);
485
486 if (!i)
Valerie Hensonb3bff392007-03-12 02:31:29 -0700487 printk(KERN_DEBUG "%s: tulip_stop_rxtx() failed"
488 " (CSR5 0x%x CSR6 0x%x)\n",
489 pci_name(tp->pdev),
490 ioread32(ioaddr + CSR5),
491 ioread32(ioaddr + CSR6));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700492 }
493}
494
495static inline void tulip_restart_rxtx(struct tulip_private *tp)
496{
Peer Chenea8f4002005-08-11 15:09:23 -0400497 tulip_stop_rxtx(tp);
498 udelay(5);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700499 tulip_start_rxtx(tp);
500}
501
Francois Romieu0bb3cf72006-09-08 11:15:38 -0700502static inline void tulip_tx_timeout_complete(struct tulip_private *tp, void __iomem *ioaddr)
503{
504 /* Stop and restart the chip's Tx processes. */
505 tulip_restart_rxtx(tp);
506 /* Trigger an immediate transmit demand. */
507 iowrite32(0, ioaddr + CSR1);
508
509 tp->stats.tx_errors++;
510}
511
Linus Torvalds1da177e2005-04-16 15:20:36 -0700512#endif /* __NET_TULIP_H__ */