blob: 92c334ff450885a8d06179ac14a4276c3805b933 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * drivers/mtd/nand/au1550nd.c
3 *
4 * Copyright (C) 2004 Embedded Edge, LLC
5 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <linux/slab.h>
13#include <linux/init.h>
14#include <linux/module.h>
Sergei Shtylyov35af68b2006-05-16 20:52:06 +040015#include <linux/interrupt.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070016#include <linux/mtd/mtd.h>
17#include <linux/mtd/nand.h>
18#include <linux/mtd/partitions.h>
19#include <asm/io.h>
20
Pete Popovef6f0d12005-09-23 02:44:58 +010021#include <asm/mach-au1x00/au1xxx.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070022
23/*
24 * MTD structure for NAND controller
25 */
26static struct mtd_info *au1550_mtd = NULL;
27static void __iomem *p_nand;
David Woodhousee0c7d762006-05-13 18:07:53 +010028static int nand_width = 1; /* default x8 */
Thomas Gleixnercad74f22006-05-23 23:28:48 +020029static void (*au1550_write_byte)(struct mtd_info *, u_char);
Linus Torvalds1da177e2005-04-16 15:20:36 -070030
Linus Torvalds1da177e2005-04-16 15:20:36 -070031/*
32 * Define partitions for flash device
33 */
Jesper Juhl3c6bee12006-01-09 20:54:01 -080034static const struct mtd_partition partition_info[] = {
Thomas Gleixner61b03bd2005-11-07 11:15:49 +000035 {
David Woodhousee0c7d762006-05-13 18:07:53 +010036 .name = "NAND FS 0",
37 .offset = 0,
38 .size = 8 * 1024 * 1024},
Thomas Gleixner61b03bd2005-11-07 11:15:49 +000039 {
David Woodhousee0c7d762006-05-13 18:07:53 +010040 .name = "NAND FS 1",
41 .offset = MTDPART_OFS_APPEND,
42 .size = MTDPART_SIZ_FULL}
Linus Torvalds1da177e2005-04-16 15:20:36 -070043};
Linus Torvalds1da177e2005-04-16 15:20:36 -070044
45/**
46 * au_read_byte - read one byte from the chip
47 * @mtd: MTD device structure
48 *
49 * read function for 8bit buswith
50 */
51static u_char au_read_byte(struct mtd_info *mtd)
52{
53 struct nand_chip *this = mtd->priv;
54 u_char ret = readb(this->IO_ADDR_R);
55 au_sync();
56 return ret;
57}
58
59/**
60 * au_write_byte - write one byte to the chip
61 * @mtd: MTD device structure
62 * @byte: pointer to data byte to write
63 *
64 * write function for 8it buswith
65 */
66static void au_write_byte(struct mtd_info *mtd, u_char byte)
67{
68 struct nand_chip *this = mtd->priv;
69 writeb(byte, this->IO_ADDR_W);
70 au_sync();
71}
72
73/**
74 * au_read_byte16 - read one byte endianess aware from the chip
75 * @mtd: MTD device structure
76 *
Thomas Gleixner61b03bd2005-11-07 11:15:49 +000077 * read function for 16bit buswith with
Linus Torvalds1da177e2005-04-16 15:20:36 -070078 * endianess conversion
79 */
80static u_char au_read_byte16(struct mtd_info *mtd)
81{
82 struct nand_chip *this = mtd->priv;
83 u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
84 au_sync();
85 return ret;
86}
87
88/**
89 * au_write_byte16 - write one byte endianess aware to the chip
90 * @mtd: MTD device structure
91 * @byte: pointer to data byte to write
92 *
93 * write function for 16bit buswith with
94 * endianess conversion
95 */
96static void au_write_byte16(struct mtd_info *mtd, u_char byte)
97{
98 struct nand_chip *this = mtd->priv;
99 writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
100 au_sync();
101}
102
103/**
104 * au_read_word - read one word from the chip
105 * @mtd: MTD device structure
106 *
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000107 * read function for 16bit buswith without
Linus Torvalds1da177e2005-04-16 15:20:36 -0700108 * endianess conversion
109 */
110static u16 au_read_word(struct mtd_info *mtd)
111{
112 struct nand_chip *this = mtd->priv;
113 u16 ret = readw(this->IO_ADDR_R);
114 au_sync();
115 return ret;
116}
117
118/**
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119 * au_write_buf - write buffer to chip
120 * @mtd: MTD device structure
121 * @buf: data buffer
122 * @len: number of bytes to write
123 *
124 * write function for 8bit buswith
125 */
126static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
127{
128 int i;
129 struct nand_chip *this = mtd->priv;
130
David Woodhousee0c7d762006-05-13 18:07:53 +0100131 for (i = 0; i < len; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132 writeb(buf[i], this->IO_ADDR_W);
133 au_sync();
134 }
135}
136
137/**
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000138 * au_read_buf - read chip data into buffer
Linus Torvalds1da177e2005-04-16 15:20:36 -0700139 * @mtd: MTD device structure
140 * @buf: buffer to store date
141 * @len: number of bytes to read
142 *
143 * read function for 8bit buswith
144 */
145static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
146{
147 int i;
148 struct nand_chip *this = mtd->priv;
149
David Woodhousee0c7d762006-05-13 18:07:53 +0100150 for (i = 0; i < len; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151 buf[i] = readb(this->IO_ADDR_R);
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000152 au_sync();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153 }
154}
155
156/**
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000157 * au_verify_buf - Verify chip data against buffer
Linus Torvalds1da177e2005-04-16 15:20:36 -0700158 * @mtd: MTD device structure
159 * @buf: buffer containing the data to compare
160 * @len: number of bytes to compare
161 *
162 * verify function for 8bit buswith
163 */
164static int au_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
165{
166 int i;
167 struct nand_chip *this = mtd->priv;
168
David Woodhousee0c7d762006-05-13 18:07:53 +0100169 for (i = 0; i < len; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700170 if (buf[i] != readb(this->IO_ADDR_R))
171 return -EFAULT;
172 au_sync();
173 }
174
175 return 0;
176}
177
178/**
179 * au_write_buf16 - write buffer to chip
180 * @mtd: MTD device structure
181 * @buf: data buffer
182 * @len: number of bytes to write
183 *
184 * write function for 16bit buswith
185 */
186static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
187{
188 int i;
189 struct nand_chip *this = mtd->priv;
190 u16 *p = (u16 *) buf;
191 len >>= 1;
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000192
David Woodhousee0c7d762006-05-13 18:07:53 +0100193 for (i = 0; i < len; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700194 writew(p[i], this->IO_ADDR_W);
195 au_sync();
196 }
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000197
Linus Torvalds1da177e2005-04-16 15:20:36 -0700198}
199
200/**
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000201 * au_read_buf16 - read chip data into buffer
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202 * @mtd: MTD device structure
203 * @buf: buffer to store date
204 * @len: number of bytes to read
205 *
206 * read function for 16bit buswith
207 */
208static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
209{
210 int i;
211 struct nand_chip *this = mtd->priv;
212 u16 *p = (u16 *) buf;
213 len >>= 1;
214
David Woodhousee0c7d762006-05-13 18:07:53 +0100215 for (i = 0; i < len; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216 p[i] = readw(this->IO_ADDR_R);
217 au_sync();
218 }
219}
220
221/**
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000222 * au_verify_buf16 - Verify chip data against buffer
Linus Torvalds1da177e2005-04-16 15:20:36 -0700223 * @mtd: MTD device structure
224 * @buf: buffer containing the data to compare
225 * @len: number of bytes to compare
226 *
227 * verify function for 16bit buswith
228 */
229static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len)
230{
231 int i;
232 struct nand_chip *this = mtd->priv;
233 u16 *p = (u16 *) buf;
234 len >>= 1;
235
David Woodhousee0c7d762006-05-13 18:07:53 +0100236 for (i = 0; i < len; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237 if (p[i] != readw(this->IO_ADDR_R))
238 return -EFAULT;
239 au_sync();
240 }
241 return 0;
242}
243
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200244/* Select the chip by setting nCE to low */
245#define NAND_CTL_SETNCE 1
246/* Deselect the chip by setting nCE to high */
247#define NAND_CTL_CLRNCE 2
248/* Select the command latch by setting CLE to high */
249#define NAND_CTL_SETCLE 3
250/* Deselect the command latch by setting CLE to low */
251#define NAND_CTL_CLRCLE 4
252/* Select the address latch by setting ALE to high */
253#define NAND_CTL_SETALE 5
254/* Deselect the address latch by setting ALE to low */
255#define NAND_CTL_CLRALE 6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256
257static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
258{
259 register struct nand_chip *this = mtd->priv;
260
David Woodhousee0c7d762006-05-13 18:07:53 +0100261 switch (cmd) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700262
David Woodhousee0c7d762006-05-13 18:07:53 +0100263 case NAND_CTL_SETCLE:
264 this->IO_ADDR_W = p_nand + MEM_STNAND_CMD;
265 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700266
David Woodhousee0c7d762006-05-13 18:07:53 +0100267 case NAND_CTL_CLRCLE:
268 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
269 break;
270
271 case NAND_CTL_SETALE:
272 this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR;
273 break;
274
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000275 case NAND_CTL_CLRALE:
276 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
David Woodhousee0c7d762006-05-13 18:07:53 +0100277 /* FIXME: Nobody knows why this is necessary,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700278 * but it works only that way */
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000279 udelay(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280 break;
281
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000282 case NAND_CTL_SETNCE:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700283 /* assert (force assert) chip enable */
David Woodhousee0c7d762006-05-13 18:07:53 +0100284 au_writel((1 << (4 + NAND_CS)), MEM_STNDCTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285 break;
286
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000287 case NAND_CTL_CLRNCE:
David Woodhousee0c7d762006-05-13 18:07:53 +0100288 /* deassert chip enable */
289 au_writel(0, MEM_STNDCTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700290 break;
291 }
292
293 this->IO_ADDR_R = this->IO_ADDR_W;
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000294
Linus Torvalds1da177e2005-04-16 15:20:36 -0700295 /* Drain the writebuffer */
296 au_sync();
297}
298
299int au1550_device_ready(struct mtd_info *mtd)
300{
301 int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0;
302 au_sync();
303 return ret;
304}
305
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400306/**
307 * au1550_select_chip - control -CE line
308 * Forbid driving -CE manually permitting the NAND controller to do this.
309 * Keeping -CE asserted during the whole sector reads interferes with the
310 * NOR flash and PCMCIA drivers as it causes contention on the static bus.
311 * We only have to hold -CE low for the NAND read commands since the flash
312 * chip needs it to be asserted during chip not ready time but the NAND
313 * controller keeps it released.
314 *
315 * @mtd: MTD device structure
316 * @chip: chipnumber to select, -1 for deselect
317 */
318static void au1550_select_chip(struct mtd_info *mtd, int chip)
319{
320}
321
322/**
323 * au1550_command - Send command to NAND device
324 * @mtd: MTD device structure
325 * @command: the command to be sent
326 * @column: the column address for this command, -1 if none
327 * @page_addr: the page address for this command, -1 if none
328 */
329static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
330{
331 register struct nand_chip *this = mtd->priv;
332 int ce_override = 0, i;
333 ulong flags;
334
335 /* Begin command latch cycle */
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200336 au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400337 /*
338 * Write out the command to the device.
339 */
340 if (command == NAND_CMD_SEQIN) {
341 int readcmd;
342
Joern Engel28318772006-05-22 23:18:05 +0200343 if (column >= mtd->writesize) {
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400344 /* OOB area */
Joern Engel28318772006-05-22 23:18:05 +0200345 column -= mtd->writesize;
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400346 readcmd = NAND_CMD_READOOB;
347 } else if (column < 256) {
348 /* First 256 bytes --> READ0 */
349 readcmd = NAND_CMD_READ0;
350 } else {
351 column -= 256;
352 readcmd = NAND_CMD_READ1;
353 }
Thomas Gleixnercad74f22006-05-23 23:28:48 +0200354 au1550_write_byte(mtd, readcmd);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400355 }
Thomas Gleixnercad74f22006-05-23 23:28:48 +0200356 au1550_write_byte(mtd, command);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400357
358 /* Set ALE and clear CLE to start address cycle */
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200359 au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400360
361 if (column != -1 || page_addr != -1) {
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200362 au1550_hwcontrol(mtd, NAND_CTL_SETALE);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400363
364 /* Serially input address */
365 if (column != -1) {
366 /* Adjust columns for 16 bit buswidth */
367 if (this->options & NAND_BUSWIDTH_16)
368 column >>= 1;
Thomas Gleixnercad74f22006-05-23 23:28:48 +0200369 au1550_write_byte(mtd, column);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400370 }
371 if (page_addr != -1) {
Thomas Gleixnercad74f22006-05-23 23:28:48 +0200372 au1550_write_byte(mtd, (u8)(page_addr & 0xff));
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400373
374 if (command == NAND_CMD_READ0 ||
375 command == NAND_CMD_READ1 ||
376 command == NAND_CMD_READOOB) {
377 /*
378 * NAND controller will release -CE after
379 * the last address byte is written, so we'll
380 * have to forcibly assert it. No interrupts
381 * are allowed while we do this as we don't
382 * want the NOR flash or PCMCIA drivers to
383 * steal our precious bytes of data...
384 */
385 ce_override = 1;
386 local_irq_save(flags);
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200387 au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400388 }
389
Thomas Gleixnercad74f22006-05-23 23:28:48 +0200390 au1550_write_byte(mtd, (u8)(page_addr >> 8));
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400391
392 /* One more address cycle for devices > 32MiB */
393 if (this->chipsize > (32 << 20))
Thomas Gleixnercad74f22006-05-23 23:28:48 +0200394 au1550_write_byte(mtd, (u8)((page_addr >> 16) & 0x0f));
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400395 }
396 /* Latch in address */
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200397 au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400398 }
399
400 /*
401 * Program and erase have their own busy handlers.
402 * Status and sequential in need no delay.
403 */
404 switch (command) {
405
406 case NAND_CMD_PAGEPROG:
407 case NAND_CMD_ERASE1:
408 case NAND_CMD_ERASE2:
409 case NAND_CMD_SEQIN:
410 case NAND_CMD_STATUS:
411 return;
412
413 case NAND_CMD_RESET:
414 break;
415
416 case NAND_CMD_READ0:
417 case NAND_CMD_READ1:
418 case NAND_CMD_READOOB:
419 /* Check if we're really driving -CE low (just in case) */
420 if (unlikely(!ce_override))
421 break;
422
423 /* Apply a short delay always to ensure that we do wait tWB. */
424 ndelay(100);
425 /* Wait for a chip to become ready... */
426 for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i)
427 udelay(1);
428
429 /* Release -CE and re-enable interrupts. */
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200430 au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400431 local_irq_restore(flags);
432 return;
433 }
434 /* Apply this short delay always to ensure that we do wait tWB. */
435 ndelay(100);
436
437 while(!this->dev_ready(mtd));
438}
439
440
Linus Torvalds1da177e2005-04-16 15:20:36 -0700441/*
442 * Main initialization routine
443 */
David Woodhousecead4db2006-05-16 13:54:50 +0100444static int __init au1xxx_nand_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700445{
446 struct nand_chip *this;
David Woodhousee0c7d762006-05-13 18:07:53 +0100447 u16 boot_swapboot = 0; /* default value */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448 int retval;
Pete Popovef6f0d12005-09-23 02:44:58 +0100449 u32 mem_staddr;
450 u32 nand_phys;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700451
452 /* Allocate memory for MTD device structure and private data */
David Woodhousee0c7d762006-05-13 18:07:53 +0100453 au1550_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700454 if (!au1550_mtd) {
David Woodhousee0c7d762006-05-13 18:07:53 +0100455 printk("Unable to allocate NAND MTD dev structure.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700456 return -ENOMEM;
457 }
458
459 /* Get pointer to private data */
David Woodhousee0c7d762006-05-13 18:07:53 +0100460 this = (struct nand_chip *)(&au1550_mtd[1]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700461
462 /* Initialize structures */
David Woodhousee0c7d762006-05-13 18:07:53 +0100463 memset(au1550_mtd, 0, sizeof(struct mtd_info));
464 memset(this, 0, sizeof(struct nand_chip));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700465
466 /* Link the private data with the MTD structure */
467 au1550_mtd->priv = this;
David Woodhouse552d9202006-05-14 01:20:46 +0100468 au1550_mtd->owner = THIS_MODULE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700469
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000470
Sergei Shtylyov155285c2006-05-16 20:16:41 +0400471 /* MEM_STNDCTL: disable ints, disable nand boot */
472 au_writel(0, MEM_STNDCTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473
474#ifdef CONFIG_MIPS_PB1550
475 /* set gpio206 high */
David Woodhousee0c7d762006-05-13 18:07:53 +0100476 au_writel(au_readl(GPIO2_DIR) & ~(1 << 6), GPIO2_DIR);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700477
David Woodhousee0c7d762006-05-13 18:07:53 +0100478 boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr->status >> 6) & 0x1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700479 switch (boot_swapboot) {
David Woodhousee0c7d762006-05-13 18:07:53 +0100480 case 0:
481 case 2:
482 case 8:
483 case 0xC:
484 case 0xD:
485 /* x16 NAND Flash */
486 nand_width = 0;
487 break;
488 case 1:
489 case 9:
490 case 3:
491 case 0xE:
492 case 0xF:
493 /* x8 NAND Flash */
494 nand_width = 1;
495 break;
496 default:
497 printk("Pb1550 NAND: bad boot:swap\n");
498 retval = -EINVAL;
499 goto outmem;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700500 }
501#endif
502
Pete Popovef6f0d12005-09-23 02:44:58 +0100503 /* Configure chip-select; normally done by boot code, e.g. YAMON */
504#ifdef NAND_STCFG
505 if (NAND_CS == 0) {
506 au_writel(NAND_STCFG, MEM_STCFG0);
507 au_writel(NAND_STTIME, MEM_STTIME0);
508 au_writel(NAND_STADDR, MEM_STADDR0);
509 }
510 if (NAND_CS == 1) {
511 au_writel(NAND_STCFG, MEM_STCFG1);
512 au_writel(NAND_STTIME, MEM_STTIME1);
513 au_writel(NAND_STADDR, MEM_STADDR1);
514 }
515 if (NAND_CS == 2) {
516 au_writel(NAND_STCFG, MEM_STCFG2);
517 au_writel(NAND_STTIME, MEM_STTIME2);
518 au_writel(NAND_STADDR, MEM_STADDR2);
519 }
520 if (NAND_CS == 3) {
521 au_writel(NAND_STCFG, MEM_STCFG3);
522 au_writel(NAND_STTIME, MEM_STTIME3);
523 au_writel(NAND_STADDR, MEM_STADDR3);
524 }
525#endif
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000526
Pete Popovef6f0d12005-09-23 02:44:58 +0100527 /* Locate NAND chip-select in order to determine NAND phys address */
528 mem_staddr = 0x00000000;
529 if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0))
530 mem_staddr = au_readl(MEM_STADDR0);
531 else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1))
532 mem_staddr = au_readl(MEM_STADDR1);
533 else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2))
534 mem_staddr = au_readl(MEM_STADDR2);
535 else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3))
536 mem_staddr = au_readl(MEM_STADDR3);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700537
Pete Popovef6f0d12005-09-23 02:44:58 +0100538 if (mem_staddr == 0x00000000) {
539 printk("Au1xxx NAND: ERROR WITH NAND CHIP-SELECT\n");
540 kfree(au1550_mtd);
541 return 1;
542 }
543 nand_phys = (mem_staddr << 4) & 0xFFFC0000;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700544
Pete Popovef6f0d12005-09-23 02:44:58 +0100545 p_nand = (void __iomem *)ioremap(nand_phys, 0x1000);
546
547 /* make controller and MTD agree */
548 if (NAND_CS == 0)
David Woodhousee0c7d762006-05-13 18:07:53 +0100549 nand_width = au_readl(MEM_STCFG0) & (1 << 22);
Pete Popovef6f0d12005-09-23 02:44:58 +0100550 if (NAND_CS == 1)
David Woodhousee0c7d762006-05-13 18:07:53 +0100551 nand_width = au_readl(MEM_STCFG1) & (1 << 22);
Pete Popovef6f0d12005-09-23 02:44:58 +0100552 if (NAND_CS == 2)
David Woodhousee0c7d762006-05-13 18:07:53 +0100553 nand_width = au_readl(MEM_STCFG2) & (1 << 22);
Pete Popovef6f0d12005-09-23 02:44:58 +0100554 if (NAND_CS == 3)
David Woodhousee0c7d762006-05-13 18:07:53 +0100555 nand_width = au_readl(MEM_STCFG3) & (1 << 22);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700556
557 /* Set address of hardware control function */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700558 this->dev_ready = au1550_device_ready;
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400559 this->select_chip = au1550_select_chip;
560 this->cmdfunc = au1550_command;
561
Linus Torvalds1da177e2005-04-16 15:20:36 -0700562 /* 30 us command delay time */
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000563 this->chip_delay = 30;
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200564 this->ecc.mode = NAND_ECC_SOFT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565
566 this->options = NAND_NO_AUTOINCR;
567
568 if (!nand_width)
569 this->options |= NAND_BUSWIDTH_16;
570
571 this->read_byte = (!nand_width) ? au_read_byte16 : au_read_byte;
Thomas Gleixnercad74f22006-05-23 23:28:48 +0200572 au1550_write_byte = (!nand_width) ? au_write_byte16 : au_write_byte;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700573 this->read_word = au_read_word;
574 this->write_buf = (!nand_width) ? au_write_buf16 : au_write_buf;
575 this->read_buf = (!nand_width) ? au_read_buf16 : au_read_buf;
576 this->verify_buf = (!nand_width) ? au_verify_buf16 : au_verify_buf;
577
578 /* Scan to find existence of the device */
David Woodhousee0c7d762006-05-13 18:07:53 +0100579 if (nand_scan(au1550_mtd, 1)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700580 retval = -ENXIO;
581 goto outio;
582 }
583
584 /* Register the partitions */
Tobias Klauser87d10f32006-03-31 02:29:45 -0800585 add_mtd_partitions(au1550_mtd, partition_info, ARRAY_SIZE(partition_info));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700586
587 return 0;
588
589 outio:
David Woodhousee0c7d762006-05-13 18:07:53 +0100590 iounmap((void *)p_nand);
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000591
Linus Torvalds1da177e2005-04-16 15:20:36 -0700592 outmem:
David Woodhousee0c7d762006-05-13 18:07:53 +0100593 kfree(au1550_mtd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700594 return retval;
595}
596
Pete Popovef6f0d12005-09-23 02:44:58 +0100597module_init(au1xxx_nand_init);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700598
599/*
600 * Clean up routine
601 */
David Woodhousee0c7d762006-05-13 18:07:53 +0100602static void __exit au1550_cleanup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700603{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700604 /* Release resources, unregister device */
David Woodhousee0c7d762006-05-13 18:07:53 +0100605 nand_release(au1550_mtd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700606
607 /* Free the MTD device structure */
David Woodhousee0c7d762006-05-13 18:07:53 +0100608 kfree(au1550_mtd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700609
610 /* Unmap */
David Woodhousee0c7d762006-05-13 18:07:53 +0100611 iounmap((void *)p_nand);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700612}
David Woodhousee0c7d762006-05-13 18:07:53 +0100613
Linus Torvalds1da177e2005-04-16 15:20:36 -0700614module_exit(au1550_cleanup);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700615
616MODULE_LICENSE("GPL");
617MODULE_AUTHOR("Embedded Edge, LLC");
618MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");