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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * sata_sil.c - Silicon Image SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2003-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 * Copyright 2003 Benjamin Herrenschmidt
10 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070011 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040012 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
Linus Torvalds1da177e2005-04-16 15:20:36 -070029 *
Jeff Garzik953d1132005-08-26 19:46:24 -040030 * Documentation for SiI 3112:
31 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
32 *
33 * Other errata and documentation available under NDA.
34 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070035 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/init.h>
41#include <linux/blkdev.h>
42#include <linux/delay.h>
43#include <linux/interrupt.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050044#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#include <scsi/scsi_host.h>
46#include <linux/libata.h>
47
48#define DRV_NAME "sata_sil"
Alan Cox9d2c7c72007-03-08 23:09:12 +000049#define DRV_VERSION "2.2"
Linus Torvalds1da177e2005-04-16 15:20:36 -070050
51enum {
Tejun Heo0d5ff562007-02-01 15:06:36 +090052 SIL_MMIO_BAR = 5,
53
Tejun Heoe653a1e2006-03-05 16:03:52 +090054 /*
55 * host flags
56 */
Tejun Heo201ce852006-06-26 21:23:52 +090057 SIL_FLAG_NO_SATA_IRQ = (1 << 28),
Tejun Heoe4e10e32006-02-25 13:52:30 +090058 SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29),
Tejun Heoe4deec62005-08-23 07:27:25 +090059 SIL_FLAG_MOD15WRITE = (1 << 30),
Tejun Heo20888d82006-05-31 18:27:53 +090060
Jeff Garzikcca39742006-08-24 03:19:22 -040061 SIL_DFL_PORT_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
Tejun Heoe5738902006-05-31 18:28:16 +090062 ATA_FLAG_MMIO | ATA_FLAG_HRST_TO_RESUME,
Tejun Heoe4deec62005-08-23 07:27:25 +090063
Tejun Heoe653a1e2006-03-05 16:03:52 +090064 /*
65 * Controller IDs
66 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070067 sil_3112 = 0,
Tejun Heo201ce852006-06-26 21:23:52 +090068 sil_3112_no_sata_irq = 1,
69 sil_3512 = 2,
70 sil_3114 = 3,
Linus Torvalds1da177e2005-04-16 15:20:36 -070071
Tejun Heoe653a1e2006-03-05 16:03:52 +090072 /*
73 * Register offsets
74 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070075 SIL_SYSCFG = 0x48,
Tejun Heoe653a1e2006-03-05 16:03:52 +090076
77 /*
78 * Register bits
79 */
80 /* SYSCFG */
Linus Torvalds1da177e2005-04-16 15:20:36 -070081 SIL_MASK_IDE0_INT = (1 << 22),
82 SIL_MASK_IDE1_INT = (1 << 23),
83 SIL_MASK_IDE2_INT = (1 << 24),
84 SIL_MASK_IDE3_INT = (1 << 25),
85 SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
86 SIL_MASK_4PORT = SIL_MASK_2PORT |
87 SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
88
Tejun Heoe653a1e2006-03-05 16:03:52 +090089 /* BMDMA/BMDMA2 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070090 SIL_INTR_STEERING = (1 << 1),
Tejun Heoe653a1e2006-03-05 16:03:52 +090091
Tejun Heo20888d82006-05-31 18:27:53 +090092 SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */
93 SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */
94 SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */
95 SIL_DMA_ACTIVE = (1 << 16), /* DMA running */
96 SIL_DMA_ERROR = (1 << 17), /* PCI bus error */
97 SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */
98 SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */
99 SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */
100 SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */
101 SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */
102
103 /* SIEN */
104 SIL_SIEN_N = (1 << 16), /* triggered by SError.N */
105
Tejun Heoe653a1e2006-03-05 16:03:52 +0900106 /*
107 * Others
108 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109 SIL_QUIRK_MOD15WRITE = (1 << 0),
110 SIL_QUIRK_UDMA5MAX = (1 << 1),
111};
112
113static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700114#ifdef CONFIG_PM
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900115static int sil_pci_device_resume(struct pci_dev *pdev);
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700116#endif
Alancd0d3bb2007-03-02 00:56:15 +0000117static void sil_dev_config(struct ata_device *dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
119static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
Alan Cox9d2c7c72007-03-08 23:09:12 +0000120static int sil_set_mode (struct ata_port *ap, struct ata_device **r_failed);
Tejun Heof6aae272006-05-15 20:58:27 +0900121static void sil_freeze(struct ata_port *ap);
122static void sil_thaw(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123
Jeff Garzik374b1872005-08-30 05:42:52 -0400124
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500125static const struct pci_device_id sil_pci_tbl[] = {
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400126 { PCI_VDEVICE(CMD, 0x3112), sil_3112 },
127 { PCI_VDEVICE(CMD, 0x0240), sil_3112 },
128 { PCI_VDEVICE(CMD, 0x3512), sil_3512 },
129 { PCI_VDEVICE(CMD, 0x3114), sil_3114 },
130 { PCI_VDEVICE(ATI, 0x436e), sil_3112 },
131 { PCI_VDEVICE(ATI, 0x4379), sil_3112_no_sata_irq },
132 { PCI_VDEVICE(ATI, 0x437a), sil_3112_no_sata_irq },
133
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134 { } /* terminate list */
135};
136
137
138/* TODO firmware versions should be added - eric */
139static const struct sil_drivelist {
140 const char * product;
141 unsigned int quirk;
142} sil_blacklist [] = {
143 { "ST320012AS", SIL_QUIRK_MOD15WRITE },
144 { "ST330013AS", SIL_QUIRK_MOD15WRITE },
145 { "ST340017AS", SIL_QUIRK_MOD15WRITE },
146 { "ST360015AS", SIL_QUIRK_MOD15WRITE },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147 { "ST380023AS", SIL_QUIRK_MOD15WRITE },
148 { "ST3120023AS", SIL_QUIRK_MOD15WRITE },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700149 { "ST340014ASL", SIL_QUIRK_MOD15WRITE },
150 { "ST360014ASL", SIL_QUIRK_MOD15WRITE },
151 { "ST380011ASL", SIL_QUIRK_MOD15WRITE },
152 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
153 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
154 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
155 { }
156};
157
158static struct pci_driver sil_pci_driver = {
159 .name = DRV_NAME,
160 .id_table = sil_pci_tbl,
161 .probe = sil_init_one,
162 .remove = ata_pci_remove_one,
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700163#ifdef CONFIG_PM
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900164 .suspend = ata_pci_device_suspend,
165 .resume = sil_pci_device_resume,
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700166#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700167};
168
Jeff Garzik193515d2005-11-07 00:59:37 -0500169static struct scsi_host_template sil_sht = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700170 .module = THIS_MODULE,
171 .name = DRV_NAME,
172 .ioctl = ata_scsi_ioctl,
173 .queuecommand = ata_scsi_queuecmd,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700174 .can_queue = ATA_DEF_QUEUE,
175 .this_id = ATA_SHT_THIS_ID,
176 .sg_tablesize = LIBATA_MAX_PRD,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
178 .emulated = ATA_SHT_EMULATED,
179 .use_clustering = ATA_SHT_USE_CLUSTERING,
180 .proc_name = DRV_NAME,
181 .dma_boundary = ATA_DMA_BOUNDARY,
182 .slave_configure = ata_scsi_slave_config,
Tejun Heoccf68c32006-05-31 18:28:09 +0900183 .slave_destroy = ata_scsi_slave_destroy,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700184 .bios_param = ata_std_bios_param,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700185};
186
Jeff Garzik057ace52005-10-22 14:27:05 -0400187static const struct ata_port_operations sil_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188 .port_disable = ata_port_disable,
189 .dev_config = sil_dev_config,
190 .tf_load = ata_tf_load,
191 .tf_read = ata_tf_read,
192 .check_status = ata_check_status,
193 .exec_command = ata_exec_command,
194 .dev_select = ata_std_dev_select,
Alan Cox9d2c7c72007-03-08 23:09:12 +0000195 .set_mode = sil_set_mode,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196 .bmdma_setup = ata_bmdma_setup,
197 .bmdma_start = ata_bmdma_start,
198 .bmdma_stop = ata_bmdma_stop,
199 .bmdma_status = ata_bmdma_status,
200 .qc_prep = ata_qc_prep,
201 .qc_issue = ata_qc_issue_prot,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900202 .data_xfer = ata_data_xfer,
Tejun Heof6aae272006-05-15 20:58:27 +0900203 .freeze = sil_freeze,
204 .thaw = sil_thaw,
205 .error_handler = ata_bmdma_error_handler,
206 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700207 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900208 .irq_on = ata_irq_on,
209 .irq_ack = ata_irq_ack,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700210 .scr_read = sil_scr_read,
211 .scr_write = sil_scr_write,
212 .port_start = ata_port_start,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700213};
214
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100215static const struct ata_port_info sil_port_info[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216 /* sil_3112 */
217 {
Jeff Garzikcca39742006-08-24 03:19:22 -0400218 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE,
Tejun Heoe4deec62005-08-23 07:27:25 +0900219 .pio_mask = 0x1f, /* pio0-4 */
220 .mwdma_mask = 0x07, /* mwdma0-2 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400221 .udma_mask = ATA_UDMA5,
Tejun Heoe4deec62005-08-23 07:27:25 +0900222 .port_ops = &sil_ops,
Tejun Heo0ee304d2006-02-25 13:52:30 +0900223 },
Tejun Heo201ce852006-06-26 21:23:52 +0900224 /* sil_3112_no_sata_irq */
225 {
Jeff Garzikcca39742006-08-24 03:19:22 -0400226 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE |
Tejun Heo201ce852006-06-26 21:23:52 +0900227 SIL_FLAG_NO_SATA_IRQ,
228 .pio_mask = 0x1f, /* pio0-4 */
229 .mwdma_mask = 0x07, /* mwdma0-2 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400230 .udma_mask = ATA_UDMA5,
Tejun Heo201ce852006-06-26 21:23:52 +0900231 .port_ops = &sil_ops,
232 },
Tejun Heo0ee304d2006-02-25 13:52:30 +0900233 /* sil_3512 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700234 {
Jeff Garzikcca39742006-08-24 03:19:22 -0400235 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
Tejun Heo0ee304d2006-02-25 13:52:30 +0900236 .pio_mask = 0x1f, /* pio0-4 */
237 .mwdma_mask = 0x07, /* mwdma0-2 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400238 .udma_mask = ATA_UDMA5,
Tejun Heo0ee304d2006-02-25 13:52:30 +0900239 .port_ops = &sil_ops,
240 },
241 /* sil_3114 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242 {
Jeff Garzikcca39742006-08-24 03:19:22 -0400243 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700244 .pio_mask = 0x1f, /* pio0-4 */
245 .mwdma_mask = 0x07, /* mwdma0-2 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400246 .udma_mask = ATA_UDMA5,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700247 .port_ops = &sil_ops,
248 },
249};
250
251/* per-port register offsets */
252/* TODO: we can probably calculate rather than use a table */
253static const struct {
254 unsigned long tf; /* ATA taskfile register block */
255 unsigned long ctl; /* ATA control/altstatus register block */
256 unsigned long bmdma; /* DMA register block */
Tejun Heo20888d82006-05-31 18:27:53 +0900257 unsigned long bmdma2; /* DMA register block #2 */
Tejun Heo48d4ef22006-03-05 16:03:52 +0900258 unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700259 unsigned long scr; /* SATA control register block */
260 unsigned long sien; /* SATA Interrupt Enable register */
261 unsigned long xfer_mode;/* data transfer mode register */
Tejun Heoe4e10e32006-02-25 13:52:30 +0900262 unsigned long sfis_cfg; /* SATA FIS reception config register */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700263} sil_port[] = {
264 /* port 0 ... */
Jeff Garzik5bcd7a002007-05-26 16:35:42 -0400265 /* tf ctl bmdma bmdma2 fifo scr sien mode sfis */
266 { 0x80, 0x8A, 0x0, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c },
267 { 0xC0, 0xCA, 0x8, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc },
Tejun Heo20888d82006-05-31 18:27:53 +0900268 { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c },
269 { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700270 /* ... port 3 */
271};
272
273MODULE_AUTHOR("Jeff Garzik");
274MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
275MODULE_LICENSE("GPL");
276MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
277MODULE_VERSION(DRV_VERSION);
278
Jeff Garzik51e9f2f2006-01-27 16:50:27 -0500279static int slow_down = 0;
280module_param(slow_down, int, 0444);
281MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
282
Jeff Garzik374b1872005-08-30 05:42:52 -0400283
Linus Torvalds1da177e2005-04-16 15:20:36 -0700284static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
285{
286 u8 cache_line = 0;
287 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
288 return cache_line;
289}
290
Alan Cox9d2c7c72007-03-08 23:09:12 +0000291/**
292 * sil_set_mode - wrap set_mode functions
293 * @ap: port to set up
294 * @r_failed: returned device when we fail
295 *
296 * Wrap the libata method for device setup as after the setup we need
297 * to inspect the results and do some configuration work
298 */
299
300static int sil_set_mode (struct ata_port *ap, struct ata_device **r_failed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700301{
Jeff Garzikcca39742006-08-24 03:19:22 -0400302 struct ata_host *host = ap->host;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303 struct ata_device *dev;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900304 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
305 void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700306 u32 tmp, dev_mode[2];
307 unsigned int i;
Alan Cox9d2c7c72007-03-08 23:09:12 +0000308 int rc;
Jeff Garzika617c092007-05-21 20:14:23 -0400309
Alan Cox9d2c7c72007-03-08 23:09:12 +0000310 rc = ata_do_set_mode(ap, r_failed);
311 if (rc)
312 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700313
314 for (i = 0; i < 2; i++) {
315 dev = &ap->device[i];
Tejun Heoe1211e32006-04-01 01:38:18 +0900316 if (!ata_dev_enabled(dev))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700317 dev_mode[i] = 0; /* PIO0/1/2 */
318 else if (dev->flags & ATA_DFLAG_PIO)
319 dev_mode[i] = 1; /* PIO3/4 */
320 else
321 dev_mode[i] = 3; /* UDMA */
322 /* value 2 indicates MDMA */
323 }
324
325 tmp = readl(addr);
326 tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
327 tmp |= dev_mode[0];
328 tmp |= (dev_mode[1] << 4);
329 writel(tmp, addr);
330 readl(addr); /* flush */
Alan Cox9d2c7c72007-03-08 23:09:12 +0000331 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700332}
333
Tejun Heo0d5ff562007-02-01 15:06:36 +0900334static inline void __iomem *sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700335{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900336 void __iomem *offset = ap->ioaddr.scr_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700337
338 switch (sc_reg) {
339 case SCR_STATUS:
340 return offset + 4;
341 case SCR_ERROR:
342 return offset + 8;
343 case SCR_CONTROL:
344 return offset;
345 default:
346 /* do nothing */
347 break;
348 }
349
Randy Dunlap8d9db2d2007-02-16 01:40:06 -0800350 return NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700351}
352
353static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
354{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900355 void __iomem *mmio = sil_scr_addr(ap, sc_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356 if (mmio)
357 return readl(mmio);
358 return 0xffffffffU;
359}
360
361static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
362{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900363 void __iomem *mmio = sil_scr_addr(ap, sc_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700364 if (mmio)
365 writel(val, mmio);
366}
367
Tejun Heocbe88fb2006-05-31 18:27:55 +0900368static void sil_host_intr(struct ata_port *ap, u32 bmdma2)
369{
Tejun Heoea547632006-11-17 12:06:21 +0900370 struct ata_eh_info *ehi = &ap->eh_info;
Tejun Heocbe88fb2006-05-31 18:27:55 +0900371 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
372 u8 status;
373
Tejun Heoe5738902006-05-31 18:28:16 +0900374 if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) {
Tejun Heod4c85322006-06-12 18:45:55 +0900375 u32 serror;
376
377 /* SIEN doesn't mask SATA IRQs on some 3112s. Those
378 * controllers continue to assert IRQ as long as
379 * SError bits are pending. Clear SError immediately.
380 */
381 serror = sil_scr_read(ap, SCR_ERROR);
382 sil_scr_write(ap, SCR_ERROR, serror);
383
384 /* Trigger hotplug and accumulate SError only if the
385 * port isn't already frozen. Otherwise, PHY events
386 * during hardreset makes controllers with broken SIEN
387 * repeat probing needlessly.
388 */
Tejun Heob51e9e52006-06-29 01:29:30 +0900389 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
Tejun Heod4c85322006-06-12 18:45:55 +0900390 ata_ehi_hotplugged(&ap->eh_info);
391 ap->eh_info.serror |= serror;
392 }
393
Tejun Heoe5738902006-05-31 18:28:16 +0900394 goto freeze;
395 }
396
Tejun Heoe2f8fb72007-02-24 22:30:36 +0900397 if (unlikely(!qc))
Tejun Heocbe88fb2006-05-31 18:27:55 +0900398 goto freeze;
399
Tejun Heoe2f8fb72007-02-24 22:30:36 +0900400 if (unlikely(qc->tf.flags & ATA_TFLAG_POLLING)) {
401 /* this sometimes happens, just clear IRQ */
402 ata_chk_status(ap);
403 return;
404 }
405
Tejun Heocbe88fb2006-05-31 18:27:55 +0900406 /* Check whether we are expecting interrupt in this state */
407 switch (ap->hsm_task_state) {
408 case HSM_ST_FIRST:
409 /* Some pre-ATAPI-4 devices assert INTRQ
410 * at this state when ready to receive CDB.
411 */
412
413 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
414 * The flag was turned on only for atapi devices.
415 * No need to check is_atapi_taskfile(&qc->tf) again.
416 */
417 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
418 goto err_hsm;
419 break;
420 case HSM_ST_LAST:
421 if (qc->tf.protocol == ATA_PROT_DMA ||
422 qc->tf.protocol == ATA_PROT_ATAPI_DMA) {
423 /* clear DMA-Start bit */
424 ap->ops->bmdma_stop(qc);
425
426 if (bmdma2 & SIL_DMA_ERROR) {
427 qc->err_mask |= AC_ERR_HOST_BUS;
428 ap->hsm_task_state = HSM_ST_ERR;
429 }
430 }
431 break;
432 case HSM_ST:
433 break;
434 default:
435 goto err_hsm;
436 }
437
438 /* check main status, clearing INTRQ */
439 status = ata_chk_status(ap);
440 if (unlikely(status & ATA_BUSY))
441 goto err_hsm;
442
443 /* ack bmdma irq events */
444 ata_bmdma_irq_clear(ap);
445
446 /* kick HSM in the ass */
447 ata_hsm_move(ap, qc, status, 0);
448
Tejun Heoea547632006-11-17 12:06:21 +0900449 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
450 qc->tf.protocol == ATA_PROT_ATAPI_DMA))
451 ata_ehi_push_desc(ehi, "BMDMA2 stat 0x%x", bmdma2);
452
Tejun Heocbe88fb2006-05-31 18:27:55 +0900453 return;
454
455 err_hsm:
456 qc->err_mask |= AC_ERR_HSM;
457 freeze:
458 ata_port_freeze(ap);
459}
460
David Howells7d12e782006-10-05 14:55:46 +0100461static irqreturn_t sil_interrupt(int irq, void *dev_instance)
Tejun Heocbe88fb2006-05-31 18:27:55 +0900462{
Jeff Garzikcca39742006-08-24 03:19:22 -0400463 struct ata_host *host = dev_instance;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900464 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
Tejun Heocbe88fb2006-05-31 18:27:55 +0900465 int handled = 0;
466 int i;
467
Jeff Garzikcca39742006-08-24 03:19:22 -0400468 spin_lock(&host->lock);
Tejun Heocbe88fb2006-05-31 18:27:55 +0900469
Jeff Garzikcca39742006-08-24 03:19:22 -0400470 for (i = 0; i < host->n_ports; i++) {
471 struct ata_port *ap = host->ports[i];
Tejun Heocbe88fb2006-05-31 18:27:55 +0900472 u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2);
473
474 if (unlikely(!ap || ap->flags & ATA_FLAG_DISABLED))
475 continue;
476
Tejun Heo201ce852006-06-26 21:23:52 +0900477 /* turn off SATA_IRQ if not supported */
478 if (ap->flags & SIL_FLAG_NO_SATA_IRQ)
479 bmdma2 &= ~SIL_DMA_SATA_IRQ;
480
Tejun Heo23fa9612006-06-12 14:18:51 +0900481 if (bmdma2 == 0xffffffff ||
482 !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ)))
Tejun Heocbe88fb2006-05-31 18:27:55 +0900483 continue;
484
485 sil_host_intr(ap, bmdma2);
486 handled = 1;
487 }
488
Jeff Garzikcca39742006-08-24 03:19:22 -0400489 spin_unlock(&host->lock);
Tejun Heocbe88fb2006-05-31 18:27:55 +0900490
491 return IRQ_RETVAL(handled);
492}
493
Tejun Heof6aae272006-05-15 20:58:27 +0900494static void sil_freeze(struct ata_port *ap)
495{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900496 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
Tejun Heof6aae272006-05-15 20:58:27 +0900497 u32 tmp;
498
Tejun Heoe5738902006-05-31 18:28:16 +0900499 /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */
500 writel(0, mmio_base + sil_port[ap->port_no].sien);
501
Tejun Heof6aae272006-05-15 20:58:27 +0900502 /* plug IRQ */
503 tmp = readl(mmio_base + SIL_SYSCFG);
504 tmp |= SIL_MASK_IDE0_INT << ap->port_no;
505 writel(tmp, mmio_base + SIL_SYSCFG);
506 readl(mmio_base + SIL_SYSCFG); /* flush */
507}
508
509static void sil_thaw(struct ata_port *ap)
510{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900511 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
Tejun Heof6aae272006-05-15 20:58:27 +0900512 u32 tmp;
513
514 /* clear IRQ */
515 ata_chk_status(ap);
516 ata_bmdma_irq_clear(ap);
517
Tejun Heo201ce852006-06-26 21:23:52 +0900518 /* turn on SATA IRQ if supported */
519 if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ))
520 writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien);
Tejun Heoe5738902006-05-31 18:28:16 +0900521
Tejun Heof6aae272006-05-15 20:58:27 +0900522 /* turn on IRQ */
523 tmp = readl(mmio_base + SIL_SYSCFG);
524 tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no);
525 writel(tmp, mmio_base + SIL_SYSCFG);
526}
527
Linus Torvalds1da177e2005-04-16 15:20:36 -0700528/**
529 * sil_dev_config - Apply device/host-specific errata fixups
Linus Torvalds1da177e2005-04-16 15:20:36 -0700530 * @dev: Device to be examined
531 *
532 * After the IDENTIFY [PACKET] DEVICE step is complete, and a
533 * device is known to be present, this function is called.
534 * We apply two errata fixups which are specific to Silicon Image,
535 * a Seagate and a Maxtor fixup.
536 *
537 * For certain Seagate devices, we must limit the maximum sectors
538 * to under 8K.
539 *
540 * For certain Maxtor devices, we must not program the drive
541 * beyond udma5.
542 *
543 * Both fixups are unfairly pessimistic. As soon as I get more
544 * information on these errata, I will create a more exhaustive
545 * list, and apply the fixups to only the specific
546 * devices/hosts/firmwares that need it.
547 *
548 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
549 * The Maxtor quirk is in the blacklist, but I'm keeping the original
550 * pessimistic fix for the following reasons...
551 * - There seems to be less info on it, only one device gleaned off the
552 * Windows driver, maybe only one is affected. More info would be greatly
553 * appreciated.
554 * - But then again UDMA5 is hardly anything to complain about
555 */
Alancd0d3bb2007-03-02 00:56:15 +0000556static void sil_dev_config(struct ata_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700557{
Alancd0d3bb2007-03-02 00:56:15 +0000558 struct ata_port *ap = dev->ap;
Tejun Heoefdaedc2006-11-01 18:38:52 +0900559 int print_info = ap->eh_context.i.flags & ATA_EHI_PRINTINFO;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700560 unsigned int n, quirks = 0;
Tejun Heoa0cf7332007-01-02 20:18:49 +0900561 unsigned char model_num[ATA_ID_PROD_LEN + 1];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700562
Tejun Heoa0cf7332007-01-02 20:18:49 +0900563 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700564
Jeff Garzik8a60a072005-07-31 13:13:24 -0400565 for (n = 0; sil_blacklist[n].product; n++)
Tejun Heo2e026712006-02-12 22:47:04 +0900566 if (!strcmp(sil_blacklist[n].product, model_num)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700567 quirks = sil_blacklist[n].quirk;
568 break;
569 }
Jeff Garzik8a60a072005-07-31 13:13:24 -0400570
Linus Torvalds1da177e2005-04-16 15:20:36 -0700571 /* limit requests to 15 sectors */
Jeff Garzik51e9f2f2006-01-27 16:50:27 -0500572 if (slow_down ||
573 ((ap->flags & SIL_FLAG_MOD15WRITE) &&
574 (quirks & SIL_QUIRK_MOD15WRITE))) {
Tejun Heoefdaedc2006-11-01 18:38:52 +0900575 if (print_info)
576 ata_dev_printk(dev, KERN_INFO, "applying Seagate "
577 "errata fix (mod15write workaround)\n");
Tejun Heob00eec12006-02-12 23:32:59 +0900578 dev->max_sectors = 15;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700579 return;
580 }
581
582 /* limit to udma5 */
583 if (quirks & SIL_QUIRK_UDMA5MAX) {
Tejun Heoefdaedc2006-11-01 18:38:52 +0900584 if (print_info)
585 ata_dev_printk(dev, KERN_INFO, "applying Maxtor "
586 "errata fix %s\n", model_num);
Tejun Heo5a529132006-03-24 14:07:50 +0900587 dev->udma_mask &= ATA_UDMA5;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700588 return;
589 }
590}
591
Tejun Heo4447d352007-04-17 23:44:08 +0900592static void sil_init_controller(struct ata_host *host)
Tejun Heo3d8ec912006-07-03 16:07:27 +0900593{
Tejun Heo4447d352007-04-17 23:44:08 +0900594 struct pci_dev *pdev = to_pci_dev(host->dev);
595 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
Tejun Heo3d8ec912006-07-03 16:07:27 +0900596 u8 cls;
597 u32 tmp;
598 int i;
599
600 /* Initialize FIFO PCI bus arbitration */
601 cls = sil_get_device_cache_line(pdev);
602 if (cls) {
603 cls >>= 3;
604 cls++; /* cls = (line_size/8)+1 */
Tejun Heo4447d352007-04-17 23:44:08 +0900605 for (i = 0; i < host->n_ports; i++)
Tejun Heo3d8ec912006-07-03 16:07:27 +0900606 writew(cls << 8 | cls,
607 mmio_base + sil_port[i].fifo_cfg);
608 } else
609 dev_printk(KERN_WARNING, &pdev->dev,
610 "cache line size not set. Driver may not function\n");
611
612 /* Apply R_ERR on DMA activate FIS errata workaround */
Tejun Heo4447d352007-04-17 23:44:08 +0900613 if (host->ports[0]->flags & SIL_FLAG_RERR_ON_DMA_ACT) {
Tejun Heo3d8ec912006-07-03 16:07:27 +0900614 int cnt;
615
Tejun Heo4447d352007-04-17 23:44:08 +0900616 for (i = 0, cnt = 0; i < host->n_ports; i++) {
Tejun Heo3d8ec912006-07-03 16:07:27 +0900617 tmp = readl(mmio_base + sil_port[i].sfis_cfg);
618 if ((tmp & 0x3) != 0x01)
619 continue;
620 if (!cnt)
621 dev_printk(KERN_INFO, &pdev->dev,
622 "Applying R_ERR on DMA activate "
623 "FIS errata fix\n");
624 writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);
625 cnt++;
626 }
627 }
628
Tejun Heo4447d352007-04-17 23:44:08 +0900629 if (host->n_ports == 4) {
Tejun Heo3d8ec912006-07-03 16:07:27 +0900630 /* flip the magic "make 4 ports work" bit */
631 tmp = readl(mmio_base + sil_port[2].bmdma);
632 if ((tmp & SIL_INTR_STEERING) == 0)
633 writel(tmp | SIL_INTR_STEERING,
634 mmio_base + sil_port[2].bmdma);
635 }
636}
637
Linus Torvalds1da177e2005-04-16 15:20:36 -0700638static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
639{
640 static int printed_version;
Tejun Heo4447d352007-04-17 23:44:08 +0900641 int board_id = ent->driver_data;
642 const struct ata_port_info *ppi[] = { &sil_port_info[board_id], NULL };
643 struct ata_host *host;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400644 void __iomem *mmio_base;
Tejun Heo4447d352007-04-17 23:44:08 +0900645 int n_ports, rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700646 unsigned int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700647
648 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -0500649 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700650
Tejun Heo4447d352007-04-17 23:44:08 +0900651 /* allocate host */
652 n_ports = 2;
653 if (board_id == sil_3114)
654 n_ports = 4;
655
656 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
657 if (!host)
658 return -ENOMEM;
659
660 /* acquire resources and fill host */
Tejun Heo24dc5f32007-01-20 16:00:28 +0900661 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700662 if (rc)
663 return rc;
664
Tejun Heo0d5ff562007-02-01 15:06:36 +0900665 rc = pcim_iomap_regions(pdev, 1 << SIL_MMIO_BAR, DRV_NAME);
666 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900667 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +0900668 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900669 return rc;
Tejun Heo4447d352007-04-17 23:44:08 +0900670 host->iomap = pcim_iomap_table(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700671
672 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
673 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900674 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700675 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
676 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900677 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700678
Tejun Heo4447d352007-04-17 23:44:08 +0900679 mmio_base = host->iomap[SIL_MMIO_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700680
Tejun Heo4447d352007-04-17 23:44:08 +0900681 for (i = 0; i < host->n_ports; i++) {
682 struct ata_ioports *ioaddr = &host->ports[i]->ioaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700683
Tejun Heo4447d352007-04-17 23:44:08 +0900684 ioaddr->cmd_addr = mmio_base + sil_port[i].tf;
685 ioaddr->altstatus_addr =
686 ioaddr->ctl_addr = mmio_base + sil_port[i].ctl;
687 ioaddr->bmdma_addr = mmio_base + sil_port[i].bmdma;
688 ioaddr->scr_addr = mmio_base + sil_port[i].scr;
689 ata_std_ports(ioaddr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700690 }
691
Tejun Heo4447d352007-04-17 23:44:08 +0900692 /* initialize and activate */
693 sil_init_controller(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700694
Linus Torvalds1da177e2005-04-16 15:20:36 -0700695 pci_set_master(pdev);
Tejun Heo4447d352007-04-17 23:44:08 +0900696 return ata_host_activate(host, pdev->irq, sil_interrupt, IRQF_SHARED,
697 &sil_sht);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700698}
699
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700700#ifdef CONFIG_PM
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900701static int sil_pci_device_resume(struct pci_dev *pdev)
702{
Jeff Garzikcca39742006-08-24 03:19:22 -0400703 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heo553c4aa2006-12-26 19:39:50 +0900704 int rc;
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900705
Tejun Heo553c4aa2006-12-26 19:39:50 +0900706 rc = ata_pci_device_do_resume(pdev);
707 if (rc)
708 return rc;
709
Tejun Heo4447d352007-04-17 23:44:08 +0900710 sil_init_controller(host);
Jeff Garzikcca39742006-08-24 03:19:22 -0400711 ata_host_resume(host);
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900712
713 return 0;
714}
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700715#endif
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900716
Linus Torvalds1da177e2005-04-16 15:20:36 -0700717static int __init sil_init(void)
718{
Pavel Roskinb7887192006-08-10 18:13:18 +0900719 return pci_register_driver(&sil_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700720}
721
722static void __exit sil_exit(void)
723{
724 pci_unregister_driver(&sil_pci_driver);
725}
726
727
728module_init(sil_init);
729module_exit(sil_exit);