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Chris Leechc13c8262006-05-23 17:18:44 -07001#
2# DMA engine configuration
3#
4
Shannon Nelson2ed6dc32007-10-16 01:27:42 -07005menuconfig DMADEVICES
Haavard Skinnemoen6d4f5872007-11-28 16:21:43 -08006 bool "DMA Engine support"
Dan Williams04ce9ab2009-06-03 14:22:28 -07007 depends on HAS_DMA
Shannon Nelson2ed6dc32007-10-16 01:27:42 -07008 help
Haavard Skinnemoen6d4f5872007-11-28 16:21:43 -08009 DMA engines can do asynchronous data transfers without
10 involving the host CPU. Currently, this framework can be
11 used to offload memory copies in the network stack and
Dan Williams9c402f42008-06-27 01:21:11 -070012 RAID operations in the MD driver. This menu only presents
13 DMA Device drivers supported by the configured arch, it may
14 be empty in some cases.
Chris Leechc13c8262006-05-23 17:18:44 -070015
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070016if DMADEVICES
Chris Leechdb217332006-06-17 21:24:58 -070017
Chris Leech0bbd5f42006-05-23 17:35:34 -070018comment "DMA Devices"
19
Dan Williams138f4c32009-09-08 17:42:51 -070020config ASYNC_TX_DISABLE_CHANNEL_SWITCH
21 bool
22
Chris Leech0bbd5f42006-05-23 17:35:34 -070023config INTEL_IOATDMA
24 tristate "Intel I/OAT DMA support"
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070025 depends on PCI && X86
26 select DMA_ENGINE
27 select DCA
Dan Williams138f4c32009-09-08 17:42:51 -070028 select ASYNC_TX_DISABLE_CHANNEL_SWITCH
Dan Williams7b3cc2b2009-11-19 17:10:37 -070029 select ASYNC_TX_DISABLE_PQ_VAL_DMA
30 select ASYNC_TX_DISABLE_XOR_VAL_DMA
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070031 help
32 Enable support for the Intel(R) I/OAT DMA engine present
33 in recent Intel Xeon chipsets.
34
35 Say Y here if you have such a chipset.
36
37 If unsure, say N.
Dan Williamsc2110922007-01-02 13:52:26 -070038
39config INTEL_IOP_ADMA
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070040 tristate "Intel IOP ADMA support"
41 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070042 select DMA_ENGINE
43 help
44 Enable support for the Intel(R) IOP Series RAID engines.
Dan Williamsc2110922007-01-02 13:52:26 -070045
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070046config DW_DMAC
47 tristate "Synopsys DesignWare AHB DMA support"
48 depends on AVR32
49 select DMA_ENGINE
50 default y if CPU_AT32AP7000
51 help
52 Support the Synopsys DesignWare AHB DMA controller. This
53 can be integrated in chips such as the Atmel AT32ap7000.
54
Nicolas Ferredc78baa2009-07-03 19:24:33 +020055config AT_HDMAC
56 tristate "Atmel AHB DMA support"
Yegor Yefremovcd3abf92009-10-23 11:27:59 +010057 depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
Nicolas Ferredc78baa2009-07-03 19:24:33 +020058 select DMA_ENGINE
59 help
60 Support the Atmel AHB DMA controller. This can be integrated in
61 chips such as the Atmel AT91SAM9RL.
62
Zhang Wei173acc72008-03-01 07:42:48 -070063config FSL_DMA
Timur Tabi77cd62e2008-09-26 17:00:11 -070064 tristate "Freescale Elo and Elo Plus DMA support"
65 depends on FSL_SOC
Zhang Wei173acc72008-03-01 07:42:48 -070066 select DMA_ENGINE
67 ---help---
Timur Tabi77cd62e2008-09-26 17:00:11 -070068 Enable support for the Freescale Elo and Elo Plus DMA controllers.
69 The Elo is the DMA controller on some 82xx and 83xx parts, and the
70 Elo Plus is the DMA controller on 85xx and 86xx parts.
Zhang Wei173acc72008-03-01 07:42:48 -070071
Saeed Bisharaff7b0472008-07-08 11:58:36 -070072config MV_XOR
73 bool "Marvell XOR engine support"
74 depends on PLAT_ORION
Saeed Bisharaff7b0472008-07-08 11:58:36 -070075 select DMA_ENGINE
76 ---help---
77 Enable support for the Marvell XOR engine.
78
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -070079config MX3_IPU
80 bool "MX3x Image Processing Unit support"
81 depends on ARCH_MX3
82 select DMA_ENGINE
83 default y
84 help
85 If you plan to use the Image Processing unit in the i.MX3x, say
86 Y here. If unsure, select Y.
87
88config MX3_IPU_IRQS
89 int "Number of dynamically mapped interrupts for IPU"
90 depends on MX3_IPU
91 range 2 137
92 default 4
93 help
94 Out of 137 interrupt sources on i.MX31 IPU only very few are used.
95 To avoid bloating the irq_desc[] array we allocate a sufficient
96 number of IRQ slots and map them dynamically to specific sources.
97
Atsushi Nemotoea76f0b2009-04-23 00:40:30 +090098config TXX9_DMAC
99 tristate "Toshiba TXx9 SoC DMA support"
100 depends on MACH_TX49XX || MACH_TX39XX
101 select DMA_ENGINE
102 help
103 Support the TXx9 SoC internal DMA controller. This can be
104 integrated in chips such as the Toshiba TX4927/38/39.
105
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000106config SH_DMAE
107 tristate "Renesas SuperH DMAC support"
108 depends on SUPERH && SH_DMA
109 depends on !SH_DMA_API
110 select DMA_ENGINE
111 help
112 Enable support for the Renesas SuperH DMA controllers.
113
Shannon Nelson2ed6dc32007-10-16 01:27:42 -0700114config DMA_ENGINE
115 bool
116
117comment "DMA Clients"
118 depends on DMA_ENGINE
119
120config NET_DMA
121 bool "Network: TCP receive copy offload"
122 depends on DMA_ENGINE && NET
Dan Williams9c402f42008-06-27 01:21:11 -0700123 default (INTEL_IOATDMA || FSL_DMA)
Shannon Nelson2ed6dc32007-10-16 01:27:42 -0700124 help
125 This enables the use of DMA engines in the network stack to
126 offload receive copy-to-user operations, freeing CPU cycles.
Dan Williams9c402f42008-06-27 01:21:11 -0700127
128 Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
129 say N.
Shannon Nelson2ed6dc32007-10-16 01:27:42 -0700130
Dan Williams729b5d12009-03-25 09:13:25 -0700131config ASYNC_TX_DMA
132 bool "Async_tx: Offload support for the async_tx api"
Dan Williams9a8de632009-09-08 15:06:10 -0700133 depends on DMA_ENGINE
Dan Williams729b5d12009-03-25 09:13:25 -0700134 help
135 This allows the async_tx api to take advantage of offload engines for
136 memcpy, memset, xor, and raid6 p+q operations. If your platform has
137 a dma engine that can perform raid operations and you have enabled
138 MD_RAID456 say Y.
139
140 If unsure, say N.
141
Haavard Skinnemoen4a776f02008-07-08 11:58:45 -0700142config DMATEST
143 tristate "DMA Test client"
144 depends on DMA_ENGINE
145 help
146 Simple DMA test client. Say N unless you're debugging a
147 DMA Device driver.
148
Shannon Nelson2ed6dc32007-10-16 01:27:42 -0700149endif