Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 1 | /* |
Paul Walmsley | 96609ef | 2009-01-28 12:27:34 -0700 | [diff] [blame] | 2 | * linux/arch/arm/mach-omap2/sdrc2xxx.c |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 3 | * |
Paul Walmsley | 96609ef | 2009-01-28 12:27:34 -0700 | [diff] [blame] | 4 | * SDRAM timing related functions for OMAP2xxx |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 5 | * |
Paul Walmsley | f2ab997 | 2009-01-28 12:27:37 -0700 | [diff] [blame] | 6 | * Copyright (C) 2005, 2008 Texas Instruments Inc. |
| 7 | * Copyright (C) 2005, 2008 Nokia Corporation |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 8 | * |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 9 | * Tony Lindgren <tony@atomide.com> |
Paul Walmsley | f2ab997 | 2009-01-28 12:27:37 -0700 | [diff] [blame] | 10 | * Paul Walmsley |
| 11 | * Richard Woodruff <r-woodruff2@ti.com> |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 12 | * |
| 13 | * This program is free software; you can redistribute it and/or modify |
| 14 | * it under the terms of the GNU General Public License version 2 as |
| 15 | * published by the Free Software Foundation. |
| 16 | */ |
| 17 | |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 18 | #include <linux/module.h> |
| 19 | #include <linux/kernel.h> |
| 20 | #include <linux/device.h> |
| 21 | #include <linux/list.h> |
| 22 | #include <linux/errno.h> |
| 23 | #include <linux/delay.h> |
| 24 | #include <linux/clk.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 25 | #include <linux/io.h> |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 26 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 27 | #include <mach/common.h> |
| 28 | #include <mach/clock.h> |
| 29 | #include <mach/sram.h> |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 30 | |
Paul Walmsley | 4459598 | 2008-03-18 10:04:51 +0200 | [diff] [blame] | 31 | #include "prm.h" |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 32 | |
Paul Walmsley | f8de9b2 | 2009-01-28 12:27:31 -0700 | [diff] [blame] | 33 | #include <mach/sdrc.h> |
Paul Walmsley | 4459598 | 2008-03-18 10:04:51 +0200 | [diff] [blame] | 34 | #include "sdrc.h" |
| 35 | |
Paul Walmsley | f8de9b2 | 2009-01-28 12:27:31 -0700 | [diff] [blame] | 36 | /* Memory timing, DLL mode flags */ |
| 37 | #define M_DDR 1 |
| 38 | #define M_LOCK_CTRL (1 << 2) |
| 39 | #define M_UNLOCK 0 |
| 40 | #define M_LOCK 1 |
| 41 | |
| 42 | |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 43 | static struct memory_timings mem_timings; |
Paul Walmsley | 4459598 | 2008-03-18 10:04:51 +0200 | [diff] [blame] | 44 | static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2; |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 45 | |
Paul Walmsley | f2ab997 | 2009-01-28 12:27:37 -0700 | [diff] [blame] | 46 | static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void) |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 47 | { |
| 48 | return mem_timings.slow_dll_ctrl; |
| 49 | } |
| 50 | |
Paul Walmsley | f2ab997 | 2009-01-28 12:27:37 -0700 | [diff] [blame] | 51 | static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void) |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 52 | { |
| 53 | return mem_timings.fast_dll_ctrl; |
| 54 | } |
| 55 | |
Paul Walmsley | f2ab997 | 2009-01-28 12:27:37 -0700 | [diff] [blame] | 56 | static u32 omap2xxx_sdrc_get_type(void) |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 57 | { |
| 58 | return mem_timings.m_type; |
| 59 | } |
| 60 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 61 | /* |
| 62 | * Check the DLL lock state, and return tue if running in unlock mode. |
| 63 | * This is needed to compensate for the shifted DLL value in unlock mode. |
| 64 | */ |
Paul Walmsley | f2ab997 | 2009-01-28 12:27:37 -0700 | [diff] [blame] | 65 | u32 omap2xxx_sdrc_dll_is_unlocked(void) |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 66 | { |
| 67 | /* dlla and dllb are a set */ |
| 68 | u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL); |
| 69 | |
| 70 | if ((dll_state & (1 << 2)) == (1 << 2)) |
| 71 | return 1; |
| 72 | else |
| 73 | return 0; |
| 74 | } |
| 75 | |
| 76 | /* |
| 77 | * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC. |
| 78 | * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or |
| 79 | * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2) |
Paul Walmsley | f2ab997 | 2009-01-28 12:27:37 -0700 | [diff] [blame] | 80 | * |
| 81 | * Used by the clock framework during CORE DPLL changes |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 82 | */ |
Paul Walmsley | f2ab997 | 2009-01-28 12:27:37 -0700 | [diff] [blame] | 83 | u32 omap2xxx_sdrc_reprogram(u32 level, u32 force) |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 84 | { |
| 85 | u32 dll_ctrl, m_type; |
| 86 | u32 prev = curr_perf_level; |
| 87 | unsigned long flags; |
| 88 | |
| 89 | if ((curr_perf_level == level) && !force) |
| 90 | return prev; |
| 91 | |
Paul Walmsley | 96609ef | 2009-01-28 12:27:34 -0700 | [diff] [blame] | 92 | if (level == CORE_CLK_SRC_DPLL) |
Paul Walmsley | f2ab997 | 2009-01-28 12:27:37 -0700 | [diff] [blame] | 93 | dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl(); |
Paul Walmsley | 96609ef | 2009-01-28 12:27:34 -0700 | [diff] [blame] | 94 | else if (level == CORE_CLK_SRC_DPLL_X2) |
Paul Walmsley | f2ab997 | 2009-01-28 12:27:37 -0700 | [diff] [blame] | 95 | dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl(); |
Paul Walmsley | 96609ef | 2009-01-28 12:27:34 -0700 | [diff] [blame] | 96 | else |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 97 | return prev; |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 98 | |
Paul Walmsley | f2ab997 | 2009-01-28 12:27:37 -0700 | [diff] [blame] | 99 | m_type = omap2xxx_sdrc_get_type(); |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 100 | |
| 101 | local_irq_save(flags); |
| 102 | __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP); |
| 103 | omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type); |
| 104 | curr_perf_level = level; |
| 105 | local_irq_restore(flags); |
| 106 | |
| 107 | return prev; |
| 108 | } |
| 109 | |
Paul Walmsley | f2ab997 | 2009-01-28 12:27:37 -0700 | [diff] [blame] | 110 | /* Used by the clock framework during CORE DPLL changes */ |
| 111 | void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode) |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 112 | { |
| 113 | unsigned long dll_cnt; |
| 114 | u32 fast_dll = 0; |
| 115 | |
Paul Walmsley | 96609ef | 2009-01-28 12:27:34 -0700 | [diff] [blame] | 116 | /* DDR = 1, SDR = 0 */ |
| 117 | mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 118 | |
| 119 | /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others. |
| 120 | * In the case of 2422, its ok to use CS1 instead of CS0. |
| 121 | */ |
| 122 | if (cpu_is_omap2422()) |
| 123 | mem_timings.base_cs = 1; |
| 124 | else |
| 125 | mem_timings.base_cs = 0; |
| 126 | |
| 127 | if (mem_timings.m_type != M_DDR) |
| 128 | return; |
| 129 | |
| 130 | /* With DDR we need to determine the low frequency DLL value */ |
| 131 | if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL)) |
| 132 | mem_timings.dll_mode = M_UNLOCK; |
| 133 | else |
| 134 | mem_timings.dll_mode = M_LOCK; |
| 135 | |
| 136 | if (mem_timings.base_cs == 0) { |
Paul Walmsley | 4459598 | 2008-03-18 10:04:51 +0200 | [diff] [blame] | 137 | fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL); |
| 138 | dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00; |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 139 | } else { |
Paul Walmsley | 4459598 | 2008-03-18 10:04:51 +0200 | [diff] [blame] | 140 | fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL); |
| 141 | dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00; |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 142 | } |
| 143 | if (force_lock_to_unlock_mode) { |
| 144 | fast_dll &= ~0xff00; |
| 145 | fast_dll |= dll_cnt; /* Current lock mode */ |
| 146 | } |
| 147 | /* set fast timings with DLL filter disabled */ |
| 148 | mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8)); |
| 149 | |
| 150 | /* No disruptions, DDR will be offline & C-ABI not followed */ |
| 151 | omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl, |
| 152 | mem_timings.fast_dll_ctrl, |
| 153 | mem_timings.base_cs, |
| 154 | force_lock_to_unlock_mode); |
| 155 | mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */ |
| 156 | |
| 157 | /* Turn status into unlock ctrl */ |
| 158 | mem_timings.slow_dll_ctrl |= |
| 159 | ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2)); |
| 160 | |
| 161 | /* 90 degree phase for anything below 133Mhz + disable DLL filter */ |
| 162 | mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8)); |
| 163 | } |