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Hauke Mehrtensd27509f2014-02-04 00:01:45 +01001/*
2 * Broadcom BCM470X / BCM5301X ARM platform code.
3 * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
4 * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
5 *
6 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
Jon Masoncdc36b22015-11-20 10:17:18 -050011#include <dt-bindings/clock/bcm-nsp.h>
Rafał Miłeckifb026d32014-10-01 15:45:28 +020012#include <dt-bindings/gpio/gpio.h>
Rafał Miłeckif6f82342014-11-30 18:28:29 +010013#include <dt-bindings/input/input.h>
Hauke Mehrtensd27509f2014-02-04 00:01:45 +010014#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16#include "skeleton.dtsi"
17
18/ {
19 interrupt-parent = <&gic>;
20
Rafał Miłecki5a6516f2016-04-06 18:49:55 +020021 chosen {
22 stdout-path = &uart0;
23 };
24
Hauke Mehrtensd27509f2014-02-04 00:01:45 +010025 chipcommonA {
26 compatible = "simple-bus";
27 ranges = <0x00000000 0x18000000 0x00001000>;
28 #address-cells = <1>;
29 #size-cells = <1>;
30
31 uart0: serial@0300 {
32 compatible = "ns16550";
33 reg = <0x0300 0x100>;
34 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
Jon Masoncdc36b22015-11-20 10:17:18 -050035 clocks = <&iprocslow>;
Hauke Mehrtensd27509f2014-02-04 00:01:45 +010036 status = "disabled";
37 };
38
39 uart1: serial@0400 {
40 compatible = "ns16550";
41 reg = <0x0400 0x100>;
42 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
Jon Masoncdc36b22015-11-20 10:17:18 -050043 clocks = <&iprocslow>;
Hauke Mehrtensd27509f2014-02-04 00:01:45 +010044 status = "disabled";
45 };
46 };
47
48 mpcore {
49 compatible = "simple-bus";
Jon Masoncdc36b22015-11-20 10:17:18 -050050 ranges = <0x00000000 0x19000000 0x00023000>;
Hauke Mehrtensd27509f2014-02-04 00:01:45 +010051 #address-cells = <1>;
52 #size-cells = <1>;
53
Jon Masoncdc36b22015-11-20 10:17:18 -050054 a9pll: arm_clk@00000 {
55 #clock-cells = <0>;
56 compatible = "brcm,nsp-armpll";
57 clocks = <&osc>;
58 reg = <0x00000 0x1000>;
59 };
60
61 scu@20000 {
Hauke Mehrtensd27509f2014-02-04 00:01:45 +010062 compatible = "arm,cortex-a9-scu";
Jon Masoncdc36b22015-11-20 10:17:18 -050063 reg = <0x20000 0x100>;
Hauke Mehrtensd27509f2014-02-04 00:01:45 +010064 };
65
Jon Masoncdc36b22015-11-20 10:17:18 -050066 timer@20200 {
Hauke Mehrtensd27509f2014-02-04 00:01:45 +010067 compatible = "arm,cortex-a9-global-timer";
Jon Masoncdc36b22015-11-20 10:17:18 -050068 reg = <0x20200 0x100>;
Hauke Mehrtensd27509f2014-02-04 00:01:45 +010069 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
Jon Masoncdc36b22015-11-20 10:17:18 -050070 clocks = <&periph_clk>;
Hauke Mehrtensd27509f2014-02-04 00:01:45 +010071 };
72
Jon Masoncdc36b22015-11-20 10:17:18 -050073 local-timer@20600 {
Hauke Mehrtensd27509f2014-02-04 00:01:45 +010074 compatible = "arm,cortex-a9-twd-timer";
Jon Masoncdc36b22015-11-20 10:17:18 -050075 reg = <0x20600 0x100>;
Hauke Mehrtensd27509f2014-02-04 00:01:45 +010076 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
Jon Masoncdc36b22015-11-20 10:17:18 -050077 clocks = <&periph_clk>;
Hauke Mehrtensd27509f2014-02-04 00:01:45 +010078 };
79
Jon Masoncdc36b22015-11-20 10:17:18 -050080 gic: interrupt-controller@21000 {
Hauke Mehrtensd27509f2014-02-04 00:01:45 +010081 compatible = "arm,cortex-a9-gic";
82 #interrupt-cells = <3>;
83 #address-cells = <0>;
84 interrupt-controller;
Jon Masoncdc36b22015-11-20 10:17:18 -050085 reg = <0x21000 0x1000>,
86 <0x20100 0x100>;
Hauke Mehrtensd27509f2014-02-04 00:01:45 +010087 };
88
Jon Masoncdc36b22015-11-20 10:17:18 -050089 L2: cache-controller@22000 {
Hauke Mehrtensd27509f2014-02-04 00:01:45 +010090 compatible = "arm,pl310-cache";
Jon Masoncdc36b22015-11-20 10:17:18 -050091 reg = <0x22000 0x1000>;
Hauke Mehrtensd27509f2014-02-04 00:01:45 +010092 cache-unified;
Hauke Mehrtensdb44f132015-07-29 23:50:59 +020093 arm,shared-override;
94 prefetch-data = <1>;
95 prefetch-instr = <1>;
Hauke Mehrtensd27509f2014-02-04 00:01:45 +010096 cache-level = <2>;
97 };
98 };
99
Felix Fietkau1ff80362015-07-29 23:51:00 +0200100 pmu {
101 compatible = "arm,cortex-a9-pmu";
102 interrupts =
103 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
105 };
106
Hauke Mehrtensd27509f2014-02-04 00:01:45 +0100107 clocks {
108 #address-cells = <1>;
Jon Masoncdc36b22015-11-20 10:17:18 -0500109 #size-cells = <1>;
110 ranges;
Hauke Mehrtensd27509f2014-02-04 00:01:45 +0100111
Jon Masoncdc36b22015-11-20 10:17:18 -0500112 osc: oscillator {
Hauke Mehrtensd27509f2014-02-04 00:01:45 +0100113 #clock-cells = <0>;
Jon Masoncdc36b22015-11-20 10:17:18 -0500114 compatible = "fixed-clock";
115 clock-frequency = <25000000>;
116 };
117
118 iprocmed: iprocmed {
119 #clock-cells = <0>;
120 compatible = "fixed-factor-clock";
121 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
122 clock-div = <2>;
123 clock-mult = <1>;
124 };
125
126 iprocslow: iprocslow {
127 #clock-cells = <0>;
128 compatible = "fixed-factor-clock";
129 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
130 clock-div = <4>;
131 clock-mult = <1>;
132 };
133
134 periph_clk: periph_clk {
135 #clock-cells = <0>;
136 compatible = "fixed-factor-clock";
137 clocks = <&a9pll>;
138 clock-div = <2>;
139 clock-mult = <1>;
Hauke Mehrtensd27509f2014-02-04 00:01:45 +0100140 };
141 };
Rafał Miłeckifb026d32014-10-01 15:45:28 +0200142
Rafał Miłecki2709d392016-06-01 22:07:07 +0200143 usb2_phy: usb2-phy {
144 compatible = "brcm,ns-usb2-phy";
145 reg = <0x1800c000 0x1000>;
146 reg-names = "dmu";
147 #phy-cells = <0>;
148 clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
149 clock-names = "phy-ref-clk";
150 };
151
Rafał Miłeckifb026d32014-10-01 15:45:28 +0200152 axi@18000000 {
153 compatible = "brcm,bus-axi";
154 reg = <0x18000000 0x1000>;
155 ranges = <0x00000000 0x18000000 0x00100000>;
156 #address-cells = <1>;
157 #size-cells = <1>;
158
Hauke Mehrtensdec37882014-09-24 23:50:07 +0200159 #interrupt-cells = <1>;
160 interrupt-map-mask = <0x000fffff 0xffff>;
161 interrupt-map =
162 /* ChipCommon */
163 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
164
Florian Fainelli2cd0c022016-05-24 11:41:58 -0700165 /* Switch Register Access Block */
166 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
167 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
168 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
169 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
170 <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
171 <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
172 <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
173 <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
174 <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
175 <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
176 <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
177 <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
178 <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
179
Hauke Mehrtens1f80de62015-05-24 21:08:14 +0200180 /* PCIe Controller 0 */
181 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
182 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
183 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
184 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
185 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
186 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
187
188 /* PCIe Controller 1 */
189 <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
190 <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
191 <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
192 <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
193 <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
194 <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
195
196 /* PCIe Controller 2 */
197 <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
198 <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
199 <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
200 <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
201 <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
202 <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
203
Hauke Mehrtensdec37882014-09-24 23:50:07 +0200204 /* USB 2.0 Controller */
205 <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
206
207 /* USB 3.0 Controller */
208 <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
209
210 /* Ethernet Controller 0 */
211 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
212
213 /* Ethernet Controller 1 */
214 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
215
216 /* Ethernet Controller 2 */
217 <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
218
219 /* Ethernet Controller 3 */
220 <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
221
222 /* NAND Controller */
223 <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
224 <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
225 <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
226 <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
227 <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
228 <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
229 <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
230 <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
231
Rafał Miłeckifb026d32014-10-01 15:45:28 +0200232 chipcommon: chipcommon@0 {
233 reg = <0x00000000 0x1000>;
234
235 gpio-controller;
236 #gpio-cells = <2>;
237 };
Rafał Miłeckidd70ccf2016-03-23 16:52:47 +0100238
239 usb2: usb2@21000 {
240 reg = <0x00021000 0x1000>;
241
242 #address-cells = <1>;
243 #size-cells = <1>;
Rafał Miłecki2709d392016-06-01 22:07:07 +0200244
245 phys = <&usb2_phy>;
Rafał Miłeckidd70ccf2016-03-23 16:52:47 +0100246 };
247
248 usb3: usb3@23000 {
249 reg = <0x00023000 0x1000>;
250
251 #address-cells = <1>;
252 #size-cells = <1>;
253 };
Rafał Miłecki1b47b982016-04-19 08:56:46 +0200254
255 spi@29000 {
256 reg = <0x00029000 0x1000>;
257 #address-cells = <1>;
258 #size-cells = <0>;
259
260 spi_nor: spi-nor@0 {
261 compatible = "jedec,spi-nor";
262 reg = <0>;
263 spi-max-frequency = <20000000>;
264 linux,part-probe = "ofpart", "bcm47xxpart";
265 status = "disabled";
266 };
267 };
Florian Fainelli59f0ce12016-05-23 16:38:00 -0700268
269 gmac0: ethernet@24000 {
270 reg = <0x24000 0x800>;
271 };
272
273 gmac1: ethernet@25000 {
274 reg = <0x25000 0x800>;
275 };
276
277 gmac2: ethernet@26000 {
278 reg = <0x26000 0x800>;
279 };
280
281 gmac3: ethernet@27000 {
282 reg = <0x27000 0x800>;
283 };
Rafał Miłeckifb026d32014-10-01 15:45:28 +0200284 };
Hauke Mehrtens9faa5962015-05-29 23:39:47 +0200285
Jon Masoncdc36b22015-11-20 10:17:18 -0500286 lcpll0: lcpll0@1800c100 {
287 #clock-cells = <1>;
288 compatible = "brcm,nsp-lcpll0";
289 reg = <0x1800c100 0x14>;
290 clocks = <&osc>;
291 clock-output-names = "lcpll0", "pcie_phy", "sdio",
292 "ddr_phy";
293 };
294
295 genpll: genpll@1800c140 {
296 #clock-cells = <1>;
297 compatible = "brcm,nsp-genpll";
298 reg = <0x1800c140 0x24>;
299 clocks = <&osc>;
300 clock-output-names = "genpll", "phy", "ethernetclk",
301 "usbclk", "iprocfast", "sata1",
302 "sata2";
303 };
304
Florian Fainelli59f0ce12016-05-23 16:38:00 -0700305 srab: srab@18007000 {
306 compatible = "brcm,bcm5301x-srab";
307 reg = <0x18007000 0x1000>;
308 #address-cells = <1>;
309 #size-cells = <0>;
310
311 status = "disabled";
312
313 /* ports are defined in board DTS */
314 };
315
Florian Fainelli36e55662016-06-22 17:27:03 -0700316 rng: rng@18004000 {
317 compatible = "brcm,bcm5301x-rng";
318 reg = <0x18004000 0x14>;
319 };
320
Hauke Mehrtens9faa5962015-05-29 23:39:47 +0200321 nand: nand@18028000 {
322 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
323 reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
324 reg-names = "nand", "iproc-idm", "iproc-ext";
325 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
326
327 #address-cells = <1>;
328 #size-cells = <0>;
329
330 brcm,nand-has-wp;
331 };
Hauke Mehrtensd27509f2014-02-04 00:01:45 +0100332};