Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Altera <www.altera.com> |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 16 | */ |
| 17 | |
Steffen Trumtrar | 7da9b43 | 2014-04-02 21:31:31 -0500 | [diff] [blame] | 18 | #include "skeleton.dtsi" |
Steffen Trumtrar | 16fb4f8 | 2014-04-15 17:27:07 -0500 | [diff] [blame] | 19 | #include <dt-bindings/reset/altr,rst-mgr.h> |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 20 | |
| 21 | / { |
| 22 | #address-cells = <1>; |
| 23 | #size-cells = <1>; |
| 24 | |
| 25 | aliases { |
| 26 | ethernet0 = &gmac0; |
Dinh Nguyen | 3d954cf | 2013-06-05 10:02:53 -0500 | [diff] [blame] | 27 | ethernet1 = &gmac1; |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 28 | serial0 = &uart0; |
| 29 | serial1 = &uart1; |
Dinh Nguyen | c2ad284 | 2013-02-11 17:30:30 -0600 | [diff] [blame] | 30 | timer0 = &timer0; |
| 31 | timer1 = &timer1; |
| 32 | timer2 = &timer2; |
| 33 | timer3 = &timer3; |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 34 | }; |
| 35 | |
| 36 | cpus { |
| 37 | #address-cells = <1>; |
| 38 | #size-cells = <0>; |
| 39 | |
| 40 | cpu@0 { |
| 41 | compatible = "arm,cortex-a9"; |
| 42 | device_type = "cpu"; |
| 43 | reg = <0>; |
| 44 | next-level-cache = <&L2>; |
| 45 | }; |
| 46 | cpu@1 { |
| 47 | compatible = "arm,cortex-a9"; |
| 48 | device_type = "cpu"; |
| 49 | reg = <1>; |
| 50 | next-level-cache = <&L2>; |
| 51 | }; |
| 52 | }; |
| 53 | |
| 54 | intc: intc@fffed000 { |
| 55 | compatible = "arm,cortex-a9-gic"; |
| 56 | #interrupt-cells = <3>; |
| 57 | interrupt-controller; |
| 58 | reg = <0xfffed000 0x1000>, |
| 59 | <0xfffec100 0x100>; |
| 60 | }; |
| 61 | |
| 62 | soc { |
| 63 | #address-cells = <1>; |
| 64 | #size-cells = <1>; |
| 65 | compatible = "simple-bus"; |
| 66 | device_type = "soc"; |
| 67 | interrupt-parent = <&intc>; |
| 68 | ranges; |
| 69 | |
| 70 | amba { |
| 71 | compatible = "arm,amba-bus"; |
| 72 | #address-cells = <1>; |
| 73 | #size-cells = <1>; |
| 74 | ranges; |
| 75 | |
| 76 | pdma: pdma@ffe01000 { |
| 77 | compatible = "arm,pl330", "arm,primecell"; |
| 78 | reg = <0xffe01000 0x1000>; |
Steffen Trumtrar | 18d5619 | 2014-04-02 10:40:30 -0500 | [diff] [blame] | 79 | interrupts = <0 104 4>, |
| 80 | <0 105 4>, |
| 81 | <0 106 4>, |
| 82 | <0 107 4>, |
| 83 | <0 108 4>, |
| 84 | <0 109 4>, |
| 85 | <0 110 4>, |
| 86 | <0 111 4>; |
Padmavathi Venna | 0d8abbf | 2013-03-04 11:04:28 +0530 | [diff] [blame] | 87 | #dma-cells = <1>; |
| 88 | #dma-channels = <8>; |
| 89 | #dma-requests = <32>; |
Steffen Trumtrar | 672ef90 | 2014-01-08 12:01:26 -0600 | [diff] [blame] | 90 | clocks = <&l4_main_clk>; |
| 91 | clock-names = "apb_pclk"; |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 92 | }; |
| 93 | }; |
| 94 | |
Steffen Trumtrar | 36fe3f5 | 2014-04-02 11:11:26 -0500 | [diff] [blame] | 95 | can0: can@ffc00000 { |
| 96 | compatible = "bosch,d_can"; |
| 97 | reg = <0xffc00000 0x1000>; |
| 98 | interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; |
| 99 | clocks = <&can0_clk>; |
| 100 | status = "disabled"; |
| 101 | }; |
| 102 | |
| 103 | can1: can@ffc01000 { |
| 104 | compatible = "bosch,d_can"; |
| 105 | reg = <0xffc01000 0x1000>; |
| 106 | interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; |
| 107 | clocks = <&can1_clk>; |
| 108 | status = "disabled"; |
| 109 | }; |
| 110 | |
Dinh Nguyen | 042000b | 2013-04-11 10:55:25 -0500 | [diff] [blame] | 111 | clkmgr@ffd04000 { |
| 112 | compatible = "altr,clk-mgr"; |
| 113 | reg = <0xffd04000 0x1000>; |
| 114 | |
| 115 | clocks { |
| 116 | #address-cells = <1>; |
| 117 | #size-cells = <0>; |
| 118 | |
Dinh Nguyen | f1ce1a9 | 2014-02-19 14:56:38 -0600 | [diff] [blame] | 119 | osc1: osc1 { |
| 120 | #clock-cells = <0>; |
| 121 | compatible = "fixed-clock"; |
| 122 | }; |
| 123 | |
| 124 | osc2: osc2 { |
Dinh Nguyen | 042000b | 2013-04-11 10:55:25 -0500 | [diff] [blame] | 125 | #clock-cells = <0>; |
| 126 | compatible = "fixed-clock"; |
| 127 | }; |
| 128 | |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 129 | f2s_periph_ref_clk: f2s_periph_ref_clk { |
| 130 | #clock-cells = <0>; |
| 131 | compatible = "fixed-clock"; |
Dinh Nguyen | f1ce1a9 | 2014-02-19 14:56:38 -0600 | [diff] [blame] | 132 | }; |
| 133 | |
| 134 | f2s_sdram_ref_clk: f2s_sdram_ref_clk { |
| 135 | #clock-cells = <0>; |
| 136 | compatible = "fixed-clock"; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 137 | }; |
| 138 | |
Dinh Nguyen | 042000b | 2013-04-11 10:55:25 -0500 | [diff] [blame] | 139 | main_pll: main_pll { |
| 140 | #address-cells = <1>; |
| 141 | #size-cells = <0>; |
| 142 | #clock-cells = <0>; |
| 143 | compatible = "altr,socfpga-pll-clock"; |
Dinh Nguyen | f1ce1a9 | 2014-02-19 14:56:38 -0600 | [diff] [blame] | 144 | clocks = <&osc1>; |
Dinh Nguyen | 042000b | 2013-04-11 10:55:25 -0500 | [diff] [blame] | 145 | reg = <0x40>; |
| 146 | |
| 147 | mpuclk: mpuclk { |
| 148 | #clock-cells = <0>; |
| 149 | compatible = "altr,socfpga-perip-clk"; |
| 150 | clocks = <&main_pll>; |
Dinh Nguyen | 8cb289e | 2014-04-16 15:05:15 -0500 | [diff] [blame] | 151 | div-reg = <0xe0 0 9>; |
Dinh Nguyen | 042000b | 2013-04-11 10:55:25 -0500 | [diff] [blame] | 152 | reg = <0x48>; |
| 153 | }; |
| 154 | |
| 155 | mainclk: mainclk { |
| 156 | #clock-cells = <0>; |
| 157 | compatible = "altr,socfpga-perip-clk"; |
| 158 | clocks = <&main_pll>; |
Dinh Nguyen | 8cb289e | 2014-04-16 15:05:15 -0500 | [diff] [blame] | 159 | div-reg = <0xe4 0 9>; |
Dinh Nguyen | 042000b | 2013-04-11 10:55:25 -0500 | [diff] [blame] | 160 | reg = <0x4C>; |
| 161 | }; |
| 162 | |
| 163 | dbg_base_clk: dbg_base_clk { |
| 164 | #clock-cells = <0>; |
| 165 | compatible = "altr,socfpga-perip-clk"; |
| 166 | clocks = <&main_pll>; |
Dinh Nguyen | 8cb289e | 2014-04-16 15:05:15 -0500 | [diff] [blame] | 167 | div-reg = <0xe8 0 9>; |
Dinh Nguyen | 042000b | 2013-04-11 10:55:25 -0500 | [diff] [blame] | 168 | reg = <0x50>; |
| 169 | }; |
| 170 | |
| 171 | main_qspi_clk: main_qspi_clk { |
| 172 | #clock-cells = <0>; |
| 173 | compatible = "altr,socfpga-perip-clk"; |
| 174 | clocks = <&main_pll>; |
| 175 | reg = <0x54>; |
| 176 | }; |
| 177 | |
| 178 | main_nand_sdmmc_clk: main_nand_sdmmc_clk { |
| 179 | #clock-cells = <0>; |
| 180 | compatible = "altr,socfpga-perip-clk"; |
| 181 | clocks = <&main_pll>; |
| 182 | reg = <0x58>; |
| 183 | }; |
| 184 | |
Steffen Trumtrar | 01ed80b | 2013-10-07 11:11:38 -0500 | [diff] [blame] | 185 | cfg_h2f_usr0_clk: cfg_h2f_usr0_clk { |
Dinh Nguyen | 042000b | 2013-04-11 10:55:25 -0500 | [diff] [blame] | 186 | #clock-cells = <0>; |
| 187 | compatible = "altr,socfpga-perip-clk"; |
| 188 | clocks = <&main_pll>; |
| 189 | reg = <0x5C>; |
| 190 | }; |
| 191 | }; |
| 192 | |
| 193 | periph_pll: periph_pll { |
| 194 | #address-cells = <1>; |
| 195 | #size-cells = <0>; |
| 196 | #clock-cells = <0>; |
| 197 | compatible = "altr,socfpga-pll-clock"; |
Dinh Nguyen | f1ce1a9 | 2014-02-19 14:56:38 -0600 | [diff] [blame] | 198 | clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; |
Dinh Nguyen | 042000b | 2013-04-11 10:55:25 -0500 | [diff] [blame] | 199 | reg = <0x80>; |
| 200 | |
| 201 | emac0_clk: emac0_clk { |
| 202 | #clock-cells = <0>; |
| 203 | compatible = "altr,socfpga-perip-clk"; |
| 204 | clocks = <&periph_pll>; |
| 205 | reg = <0x88>; |
| 206 | }; |
| 207 | |
| 208 | emac1_clk: emac1_clk { |
| 209 | #clock-cells = <0>; |
| 210 | compatible = "altr,socfpga-perip-clk"; |
| 211 | clocks = <&periph_pll>; |
| 212 | reg = <0x8C>; |
| 213 | }; |
| 214 | |
| 215 | per_qspi_clk: per_qsi_clk { |
| 216 | #clock-cells = <0>; |
| 217 | compatible = "altr,socfpga-perip-clk"; |
| 218 | clocks = <&periph_pll>; |
| 219 | reg = <0x90>; |
| 220 | }; |
| 221 | |
| 222 | per_nand_mmc_clk: per_nand_mmc_clk { |
| 223 | #clock-cells = <0>; |
| 224 | compatible = "altr,socfpga-perip-clk"; |
| 225 | clocks = <&periph_pll>; |
| 226 | reg = <0x94>; |
| 227 | }; |
| 228 | |
| 229 | per_base_clk: per_base_clk { |
| 230 | #clock-cells = <0>; |
| 231 | compatible = "altr,socfpga-perip-clk"; |
| 232 | clocks = <&periph_pll>; |
| 233 | reg = <0x98>; |
| 234 | }; |
| 235 | |
Steffen Trumtrar | 01ed80b | 2013-10-07 11:11:38 -0500 | [diff] [blame] | 236 | h2f_usr1_clk: h2f_usr1_clk { |
Dinh Nguyen | 042000b | 2013-04-11 10:55:25 -0500 | [diff] [blame] | 237 | #clock-cells = <0>; |
| 238 | compatible = "altr,socfpga-perip-clk"; |
| 239 | clocks = <&periph_pll>; |
| 240 | reg = <0x9C>; |
| 241 | }; |
| 242 | }; |
| 243 | |
| 244 | sdram_pll: sdram_pll { |
| 245 | #address-cells = <1>; |
| 246 | #size-cells = <0>; |
| 247 | #clock-cells = <0>; |
| 248 | compatible = "altr,socfpga-pll-clock"; |
Dinh Nguyen | f1ce1a9 | 2014-02-19 14:56:38 -0600 | [diff] [blame] | 249 | clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; |
Dinh Nguyen | 042000b | 2013-04-11 10:55:25 -0500 | [diff] [blame] | 250 | reg = <0xC0>; |
| 251 | |
| 252 | ddr_dqs_clk: ddr_dqs_clk { |
| 253 | #clock-cells = <0>; |
| 254 | compatible = "altr,socfpga-perip-clk"; |
| 255 | clocks = <&sdram_pll>; |
| 256 | reg = <0xC8>; |
| 257 | }; |
| 258 | |
| 259 | ddr_2x_dqs_clk: ddr_2x_dqs_clk { |
| 260 | #clock-cells = <0>; |
| 261 | compatible = "altr,socfpga-perip-clk"; |
| 262 | clocks = <&sdram_pll>; |
| 263 | reg = <0xCC>; |
| 264 | }; |
| 265 | |
| 266 | ddr_dq_clk: ddr_dq_clk { |
| 267 | #clock-cells = <0>; |
| 268 | compatible = "altr,socfpga-perip-clk"; |
| 269 | clocks = <&sdram_pll>; |
| 270 | reg = <0xD0>; |
| 271 | }; |
| 272 | |
Steffen Trumtrar | 01ed80b | 2013-10-07 11:11:38 -0500 | [diff] [blame] | 273 | h2f_usr2_clk: h2f_usr2_clk { |
Dinh Nguyen | 042000b | 2013-04-11 10:55:25 -0500 | [diff] [blame] | 274 | #clock-cells = <0>; |
| 275 | compatible = "altr,socfpga-perip-clk"; |
| 276 | clocks = <&sdram_pll>; |
| 277 | reg = <0xD4>; |
| 278 | }; |
| 279 | }; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 280 | |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 281 | mpu_periph_clk: mpu_periph_clk { |
| 282 | #clock-cells = <0>; |
Dinh Nguyen | a5c6e87 | 2013-12-03 14:32:10 -0600 | [diff] [blame] | 283 | compatible = "altr,socfpga-perip-clk"; |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 284 | clocks = <&mpuclk>; |
| 285 | fixed-divider = <4>; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 286 | }; |
| 287 | |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 288 | mpu_l2_ram_clk: mpu_l2_ram_clk { |
| 289 | #clock-cells = <0>; |
Dinh Nguyen | a5c6e87 | 2013-12-03 14:32:10 -0600 | [diff] [blame] | 290 | compatible = "altr,socfpga-perip-clk"; |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 291 | clocks = <&mpuclk>; |
| 292 | fixed-divider = <2>; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 293 | }; |
| 294 | |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 295 | l4_main_clk: l4_main_clk { |
| 296 | #clock-cells = <0>; |
| 297 | compatible = "altr,socfpga-gate-clk"; |
| 298 | clocks = <&mainclk>; |
| 299 | clk-gate = <0x60 0>; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 300 | }; |
| 301 | |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 302 | l3_main_clk: l3_main_clk { |
| 303 | #clock-cells = <0>; |
Dinh Nguyen | a5c6e87 | 2013-12-03 14:32:10 -0600 | [diff] [blame] | 304 | compatible = "altr,socfpga-perip-clk"; |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 305 | clocks = <&mainclk>; |
Dinh Nguyen | a5c6e87 | 2013-12-03 14:32:10 -0600 | [diff] [blame] | 306 | fixed-divider = <1>; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 307 | }; |
| 308 | |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 309 | l3_mp_clk: l3_mp_clk { |
| 310 | #clock-cells = <0>; |
| 311 | compatible = "altr,socfpga-gate-clk"; |
| 312 | clocks = <&mainclk>; |
| 313 | div-reg = <0x64 0 2>; |
| 314 | clk-gate = <0x60 1>; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 315 | }; |
| 316 | |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 317 | l3_sp_clk: l3_sp_clk { |
| 318 | #clock-cells = <0>; |
| 319 | compatible = "altr,socfpga-gate-clk"; |
| 320 | clocks = <&mainclk>; |
| 321 | div-reg = <0x64 2 2>; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 322 | }; |
| 323 | |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 324 | l4_mp_clk: l4_mp_clk { |
| 325 | #clock-cells = <0>; |
| 326 | compatible = "altr,socfpga-gate-clk"; |
| 327 | clocks = <&mainclk>, <&per_base_clk>; |
| 328 | div-reg = <0x64 4 3>; |
| 329 | clk-gate = <0x60 2>; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 330 | }; |
| 331 | |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 332 | l4_sp_clk: l4_sp_clk { |
| 333 | #clock-cells = <0>; |
| 334 | compatible = "altr,socfpga-gate-clk"; |
| 335 | clocks = <&mainclk>, <&per_base_clk>; |
| 336 | div-reg = <0x64 7 3>; |
| 337 | clk-gate = <0x60 3>; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 338 | }; |
| 339 | |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 340 | dbg_at_clk: dbg_at_clk { |
| 341 | #clock-cells = <0>; |
| 342 | compatible = "altr,socfpga-gate-clk"; |
| 343 | clocks = <&dbg_base_clk>; |
| 344 | div-reg = <0x68 0 2>; |
| 345 | clk-gate = <0x60 4>; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 346 | }; |
| 347 | |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 348 | dbg_clk: dbg_clk { |
| 349 | #clock-cells = <0>; |
| 350 | compatible = "altr,socfpga-gate-clk"; |
| 351 | clocks = <&dbg_base_clk>; |
| 352 | div-reg = <0x68 2 2>; |
| 353 | clk-gate = <0x60 5>; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 354 | }; |
| 355 | |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 356 | dbg_trace_clk: dbg_trace_clk { |
| 357 | #clock-cells = <0>; |
| 358 | compatible = "altr,socfpga-gate-clk"; |
| 359 | clocks = <&dbg_base_clk>; |
| 360 | div-reg = <0x6C 0 3>; |
| 361 | clk-gate = <0x60 6>; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 362 | }; |
| 363 | |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 364 | dbg_timer_clk: dbg_timer_clk { |
| 365 | #clock-cells = <0>; |
| 366 | compatible = "altr,socfpga-gate-clk"; |
| 367 | clocks = <&dbg_base_clk>; |
| 368 | clk-gate = <0x60 7>; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 369 | }; |
| 370 | |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 371 | cfg_clk: cfg_clk { |
| 372 | #clock-cells = <0>; |
| 373 | compatible = "altr,socfpga-gate-clk"; |
Steffen Trumtrar | 01ed80b | 2013-10-07 11:11:38 -0500 | [diff] [blame] | 374 | clocks = <&cfg_h2f_usr0_clk>; |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 375 | clk-gate = <0x60 8>; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 376 | }; |
| 377 | |
Steffen Trumtrar | 01ed80b | 2013-10-07 11:11:38 -0500 | [diff] [blame] | 378 | h2f_user0_clk: h2f_user0_clk { |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 379 | #clock-cells = <0>; |
| 380 | compatible = "altr,socfpga-gate-clk"; |
Steffen Trumtrar | 01ed80b | 2013-10-07 11:11:38 -0500 | [diff] [blame] | 381 | clocks = <&cfg_h2f_usr0_clk>; |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 382 | clk-gate = <0x60 9>; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 383 | }; |
| 384 | |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 385 | emac_0_clk: emac_0_clk { |
| 386 | #clock-cells = <0>; |
| 387 | compatible = "altr,socfpga-gate-clk"; |
| 388 | clocks = <&emac0_clk>; |
| 389 | clk-gate = <0xa0 0>; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 390 | }; |
| 391 | |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 392 | emac_1_clk: emac_1_clk { |
| 393 | #clock-cells = <0>; |
| 394 | compatible = "altr,socfpga-gate-clk"; |
| 395 | clocks = <&emac1_clk>; |
| 396 | clk-gate = <0xa0 1>; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 397 | }; |
| 398 | |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 399 | usb_mp_clk: usb_mp_clk { |
| 400 | #clock-cells = <0>; |
| 401 | compatible = "altr,socfpga-gate-clk"; |
| 402 | clocks = <&per_base_clk>; |
| 403 | clk-gate = <0xa0 2>; |
| 404 | div-reg = <0xa4 0 3>; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 405 | }; |
| 406 | |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 407 | spi_m_clk: spi_m_clk { |
| 408 | #clock-cells = <0>; |
| 409 | compatible = "altr,socfpga-gate-clk"; |
| 410 | clocks = <&per_base_clk>; |
| 411 | clk-gate = <0xa0 3>; |
| 412 | div-reg = <0xa4 3 3>; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 413 | }; |
| 414 | |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 415 | can0_clk: can0_clk { |
| 416 | #clock-cells = <0>; |
| 417 | compatible = "altr,socfpga-gate-clk"; |
| 418 | clocks = <&per_base_clk>; |
| 419 | clk-gate = <0xa0 4>; |
| 420 | div-reg = <0xa4 6 3>; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 421 | }; |
| 422 | |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 423 | can1_clk: can1_clk { |
| 424 | #clock-cells = <0>; |
| 425 | compatible = "altr,socfpga-gate-clk"; |
| 426 | clocks = <&per_base_clk>; |
| 427 | clk-gate = <0xa0 5>; |
| 428 | div-reg = <0xa4 9 3>; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 429 | }; |
| 430 | |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 431 | gpio_db_clk: gpio_db_clk { |
| 432 | #clock-cells = <0>; |
| 433 | compatible = "altr,socfpga-gate-clk"; |
| 434 | clocks = <&per_base_clk>; |
| 435 | clk-gate = <0xa0 6>; |
| 436 | div-reg = <0xa8 0 24>; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 437 | }; |
| 438 | |
Steffen Trumtrar | 01ed80b | 2013-10-07 11:11:38 -0500 | [diff] [blame] | 439 | h2f_user1_clk: h2f_user1_clk { |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 440 | #clock-cells = <0>; |
| 441 | compatible = "altr,socfpga-gate-clk"; |
Steffen Trumtrar | 01ed80b | 2013-10-07 11:11:38 -0500 | [diff] [blame] | 442 | clocks = <&h2f_usr1_clk>; |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 443 | clk-gate = <0xa0 7>; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 444 | }; |
| 445 | |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 446 | sdmmc_clk: sdmmc_clk { |
| 447 | #clock-cells = <0>; |
| 448 | compatible = "altr,socfpga-gate-clk"; |
| 449 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; |
| 450 | clk-gate = <0xa0 8>; |
Dinh Nguyen | 044abbd | 2014-01-06 12:17:24 -0600 | [diff] [blame] | 451 | clk-phase = <0 135>; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 452 | }; |
| 453 | |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 454 | nand_x_clk: nand_x_clk { |
| 455 | #clock-cells = <0>; |
| 456 | compatible = "altr,socfpga-gate-clk"; |
| 457 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; |
| 458 | clk-gate = <0xa0 9>; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 459 | }; |
| 460 | |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 461 | nand_clk: nand_clk { |
| 462 | #clock-cells = <0>; |
| 463 | compatible = "altr,socfpga-gate-clk"; |
| 464 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; |
| 465 | clk-gate = <0xa0 10>; |
| 466 | fixed-divider = <4>; |
| 467 | }; |
| 468 | |
| 469 | qspi_clk: qspi_clk { |
| 470 | #clock-cells = <0>; |
| 471 | compatible = "altr,socfpga-gate-clk"; |
| 472 | clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; |
| 473 | clk-gate = <0xa0 11>; |
Dinh Nguyen | a92b83a | 2013-06-05 10:02:54 -0500 | [diff] [blame] | 474 | }; |
Dinh Nguyen | 042000b | 2013-04-11 10:55:25 -0500 | [diff] [blame] | 475 | }; |
| 476 | }; |
| 477 | |
Dinh Nguyen | 3d954cf | 2013-06-05 10:02:53 -0500 | [diff] [blame] | 478 | gmac0: ethernet@ff700000 { |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 479 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; |
Dinh Nguyen | 2755e18 | 2014-03-26 22:45:11 -0500 | [diff] [blame] | 480 | altr,sysmgr-syscon = <&sysmgr 0x60 0>; |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 481 | reg = <0xff700000 0x2000>; |
| 482 | interrupts = <0 115 4>; |
| 483 | interrupt-names = "macirq"; |
| 484 | mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ |
Dinh Nguyen | 3d954cf | 2013-06-05 10:02:53 -0500 | [diff] [blame] | 485 | clocks = <&emac0_clk>; |
| 486 | clock-names = "stmmaceth"; |
Steffen Trumtrar | 16fb4f8 | 2014-04-15 17:27:07 -0500 | [diff] [blame] | 487 | resets = <&rst EMAC0_RESET>; |
| 488 | reset-names = "stmmaceth"; |
Vince Bridgers | ea6856e | 2014-07-31 15:49:16 -0500 | [diff] [blame] | 489 | snps,multicast-filter-bins = <256>; |
| 490 | snps,perfect-filter-entries = <128>; |
Dinh Nguyen | 3d954cf | 2013-06-05 10:02:53 -0500 | [diff] [blame] | 491 | status = "disabled"; |
| 492 | }; |
| 493 | |
| 494 | gmac1: ethernet@ff702000 { |
| 495 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; |
Dinh Nguyen | 2755e18 | 2014-03-26 22:45:11 -0500 | [diff] [blame] | 496 | altr,sysmgr-syscon = <&sysmgr 0x60 2>; |
Dinh Nguyen | 3d954cf | 2013-06-05 10:02:53 -0500 | [diff] [blame] | 497 | reg = <0xff702000 0x2000>; |
| 498 | interrupts = <0 120 4>; |
| 499 | interrupt-names = "macirq"; |
| 500 | mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ |
| 501 | clocks = <&emac1_clk>; |
| 502 | clock-names = "stmmaceth"; |
Steffen Trumtrar | 16fb4f8 | 2014-04-15 17:27:07 -0500 | [diff] [blame] | 503 | resets = <&rst EMAC1_RESET>; |
| 504 | reset-names = "stmmaceth"; |
Vince Bridgers | ea6856e | 2014-07-31 15:49:16 -0500 | [diff] [blame] | 505 | snps,multicast-filter-bins = <256>; |
| 506 | snps,perfect-filter-entries = <128>; |
Dinh Nguyen | 3d954cf | 2013-06-05 10:02:53 -0500 | [diff] [blame] | 507 | status = "disabled"; |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 508 | }; |
| 509 | |
Steffen Trumtrar | fdeda15 | 2014-04-02 11:05:31 -0500 | [diff] [blame] | 510 | i2c0: i2c@ffc04000 { |
| 511 | #address-cells = <1>; |
| 512 | #size-cells = <0>; |
| 513 | compatible = "snps,designware-i2c"; |
| 514 | reg = <0xffc04000 0x1000>; |
| 515 | clocks = <&l4_sp_clk>; |
| 516 | interrupts = <0 158 0x4>; |
| 517 | status = "disabled"; |
| 518 | }; |
| 519 | |
| 520 | i2c1: i2c@ffc05000 { |
| 521 | #address-cells = <1>; |
| 522 | #size-cells = <0>; |
| 523 | compatible = "snps,designware-i2c"; |
| 524 | reg = <0xffc05000 0x1000>; |
| 525 | clocks = <&l4_sp_clk>; |
| 526 | interrupts = <0 159 0x4>; |
| 527 | status = "disabled"; |
| 528 | }; |
| 529 | |
| 530 | i2c2: i2c@ffc06000 { |
| 531 | #address-cells = <1>; |
| 532 | #size-cells = <0>; |
| 533 | compatible = "snps,designware-i2c"; |
| 534 | reg = <0xffc06000 0x1000>; |
| 535 | clocks = <&l4_sp_clk>; |
| 536 | interrupts = <0 160 0x4>; |
| 537 | status = "disabled"; |
| 538 | }; |
| 539 | |
| 540 | i2c3: i2c@ffc07000 { |
| 541 | #address-cells = <1>; |
| 542 | #size-cells = <0>; |
| 543 | compatible = "snps,designware-i2c"; |
| 544 | reg = <0xffc07000 0x1000>; |
| 545 | clocks = <&l4_sp_clk>; |
| 546 | interrupts = <0 161 0x4>; |
| 547 | status = "disabled"; |
| 548 | }; |
| 549 | |
Dinh Nguyen | d11ac1d | 2014-10-22 13:00:42 -0500 | [diff] [blame] | 550 | gpio0: gpio@ff708000 { |
Sebastian Andrzej Siewior | 6ec08c7 | 2014-03-20 18:21:55 -0500 | [diff] [blame] | 551 | #address-cells = <1>; |
| 552 | #size-cells = <0>; |
| 553 | compatible = "snps,dw-apb-gpio"; |
| 554 | reg = <0xff708000 0x1000>; |
| 555 | clocks = <&per_base_clk>; |
| 556 | status = "disabled"; |
| 557 | |
Dinh Nguyen | d11ac1d | 2014-10-22 13:00:42 -0500 | [diff] [blame] | 558 | porta: gpio-controller@0 { |
Sebastian Andrzej Siewior | 6ec08c7 | 2014-03-20 18:21:55 -0500 | [diff] [blame] | 559 | compatible = "snps,dw-apb-gpio-port"; |
| 560 | gpio-controller; |
| 561 | #gpio-cells = <2>; |
| 562 | snps,nr-gpios = <29>; |
| 563 | reg = <0>; |
| 564 | interrupt-controller; |
| 565 | #interrupt-cells = <2>; |
| 566 | interrupts = <0 164 4>; |
| 567 | }; |
| 568 | }; |
| 569 | |
Dinh Nguyen | d11ac1d | 2014-10-22 13:00:42 -0500 | [diff] [blame] | 570 | gpio1: gpio@ff709000 { |
Sebastian Andrzej Siewior | 6ec08c7 | 2014-03-20 18:21:55 -0500 | [diff] [blame] | 571 | #address-cells = <1>; |
| 572 | #size-cells = <0>; |
| 573 | compatible = "snps,dw-apb-gpio"; |
| 574 | reg = <0xff709000 0x1000>; |
| 575 | clocks = <&per_base_clk>; |
| 576 | status = "disabled"; |
| 577 | |
Dinh Nguyen | d11ac1d | 2014-10-22 13:00:42 -0500 | [diff] [blame] | 578 | portb: gpio-controller@0 { |
Sebastian Andrzej Siewior | 6ec08c7 | 2014-03-20 18:21:55 -0500 | [diff] [blame] | 579 | compatible = "snps,dw-apb-gpio-port"; |
| 580 | gpio-controller; |
| 581 | #gpio-cells = <2>; |
| 582 | snps,nr-gpios = <29>; |
| 583 | reg = <0>; |
| 584 | interrupt-controller; |
| 585 | #interrupt-cells = <2>; |
| 586 | interrupts = <0 165 4>; |
| 587 | }; |
| 588 | }; |
| 589 | |
Dinh Nguyen | d11ac1d | 2014-10-22 13:00:42 -0500 | [diff] [blame] | 590 | gpio2: gpio@ff70a000 { |
Sebastian Andrzej Siewior | 6ec08c7 | 2014-03-20 18:21:55 -0500 | [diff] [blame] | 591 | #address-cells = <1>; |
| 592 | #size-cells = <0>; |
| 593 | compatible = "snps,dw-apb-gpio"; |
| 594 | reg = <0xff70a000 0x1000>; |
| 595 | clocks = <&per_base_clk>; |
| 596 | status = "disabled"; |
| 597 | |
Dinh Nguyen | d11ac1d | 2014-10-22 13:00:42 -0500 | [diff] [blame] | 598 | portc: gpio-controller@0 { |
Sebastian Andrzej Siewior | 6ec08c7 | 2014-03-20 18:21:55 -0500 | [diff] [blame] | 599 | compatible = "snps,dw-apb-gpio-port"; |
| 600 | gpio-controller; |
| 601 | #gpio-cells = <2>; |
| 602 | snps,nr-gpios = <27>; |
| 603 | reg = <0>; |
| 604 | interrupt-controller; |
| 605 | #interrupt-cells = <2>; |
| 606 | interrupts = <0 166 4>; |
| 607 | }; |
| 608 | }; |
| 609 | |
Thor Thayer | 75a4182 | 2014-08-26 16:09:32 -0500 | [diff] [blame] | 610 | sdr: sdr@ffc25000 { |
| 611 | compatible = "syscon"; |
| 612 | reg = <0xffc25000 0x1000>; |
| 613 | }; |
| 614 | |
| 615 | sdramedac { |
| 616 | compatible = "altr,sdram-edac"; |
| 617 | altr,sdr-syscon = <&sdr>; |
| 618 | interrupts = <0 39 4>; |
| 619 | }; |
| 620 | |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 621 | L2: l2-cache@fffef000 { |
| 622 | compatible = "arm,pl310-cache"; |
| 623 | reg = <0xfffef000 0x1000>; |
| 624 | interrupts = <0 38 0x04>; |
| 625 | cache-unified; |
| 626 | cache-level = <2>; |
Dinh Nguyen | 9a21e55 | 2014-01-06 20:54:43 -0600 | [diff] [blame] | 627 | arm,tag-latency = <1 1 1>; |
| 628 | arm,data-latency = <2 1 1>; |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 629 | }; |
| 630 | |
Dinh Nguyen | 9b93136 | 2014-02-17 20:31:02 -0600 | [diff] [blame] | 631 | mmc: dwmmc0@ff704000 { |
| 632 | compatible = "altr,socfpga-dw-mshc"; |
| 633 | reg = <0xff704000 0x1000>; |
| 634 | interrupts = <0 139 4>; |
| 635 | fifo-depth = <0x400>; |
| 636 | #address-cells = <1>; |
| 637 | #size-cells = <0>; |
| 638 | clocks = <&l4_mp_clk>, <&sdmmc_clk>; |
| 639 | clock-names = "biu", "ciu"; |
| 640 | }; |
| 641 | |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 642 | /* Local timer */ |
| 643 | timer@fffec600 { |
| 644 | compatible = "arm,cortex-a9-twd-timer"; |
| 645 | reg = <0xfffec600 0x100>; |
| 646 | interrupts = <1 13 0xf04>; |
Dinh Nguyen | 159c7f8 | 2013-10-01 14:42:27 -0500 | [diff] [blame] | 647 | clocks = <&mpu_periph_clk>; |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 648 | }; |
| 649 | |
Dinh Nguyen | c2ad284 | 2013-02-11 17:30:30 -0600 | [diff] [blame] | 650 | timer0: timer0@ffc08000 { |
Dinh Nguyen | 620f5e1 | 2013-08-21 15:28:49 -0500 | [diff] [blame] | 651 | compatible = "snps,dw-apb-timer"; |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 652 | interrupts = <0 167 4>; |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 653 | reg = <0xffc08000 0x1000>; |
Dinh Nguyen | bd785ef | 2014-04-02 21:14:57 -0500 | [diff] [blame] | 654 | clocks = <&l4_sp_clk>; |
| 655 | clock-names = "timer"; |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 656 | }; |
| 657 | |
Dinh Nguyen | c2ad284 | 2013-02-11 17:30:30 -0600 | [diff] [blame] | 658 | timer1: timer1@ffc09000 { |
Dinh Nguyen | 620f5e1 | 2013-08-21 15:28:49 -0500 | [diff] [blame] | 659 | compatible = "snps,dw-apb-timer"; |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 660 | interrupts = <0 168 4>; |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 661 | reg = <0xffc09000 0x1000>; |
Dinh Nguyen | bd785ef | 2014-04-02 21:14:57 -0500 | [diff] [blame] | 662 | clocks = <&l4_sp_clk>; |
| 663 | clock-names = "timer"; |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 664 | }; |
| 665 | |
Dinh Nguyen | c2ad284 | 2013-02-11 17:30:30 -0600 | [diff] [blame] | 666 | timer2: timer2@ffd00000 { |
Dinh Nguyen | 620f5e1 | 2013-08-21 15:28:49 -0500 | [diff] [blame] | 667 | compatible = "snps,dw-apb-timer"; |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 668 | interrupts = <0 169 4>; |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 669 | reg = <0xffd00000 0x1000>; |
Dinh Nguyen | bd785ef | 2014-04-02 21:14:57 -0500 | [diff] [blame] | 670 | clocks = <&osc1>; |
| 671 | clock-names = "timer"; |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 672 | }; |
| 673 | |
Dinh Nguyen | c2ad284 | 2013-02-11 17:30:30 -0600 | [diff] [blame] | 674 | timer3: timer3@ffd01000 { |
Dinh Nguyen | 620f5e1 | 2013-08-21 15:28:49 -0500 | [diff] [blame] | 675 | compatible = "snps,dw-apb-timer"; |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 676 | interrupts = <0 170 4>; |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 677 | reg = <0xffd01000 0x1000>; |
Dinh Nguyen | bd785ef | 2014-04-02 21:14:57 -0500 | [diff] [blame] | 678 | clocks = <&osc1>; |
| 679 | clock-names = "timer"; |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 680 | }; |
| 681 | |
Dinh Nguyen | c2ad284 | 2013-02-11 17:30:30 -0600 | [diff] [blame] | 682 | uart0: serial0@ffc02000 { |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 683 | compatible = "snps,dw-apb-uart"; |
| 684 | reg = <0xffc02000 0x1000>; |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 685 | interrupts = <0 162 4>; |
| 686 | reg-shift = <2>; |
| 687 | reg-io-width = <4>; |
Dinh Nguyen | bd785ef | 2014-04-02 21:14:57 -0500 | [diff] [blame] | 688 | clocks = <&l4_sp_clk>; |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 689 | }; |
| 690 | |
Dinh Nguyen | c2ad284 | 2013-02-11 17:30:30 -0600 | [diff] [blame] | 691 | uart1: serial1@ffc03000 { |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 692 | compatible = "snps,dw-apb-uart"; |
| 693 | reg = <0xffc03000 0x1000>; |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 694 | interrupts = <0 163 4>; |
| 695 | reg-shift = <2>; |
| 696 | reg-io-width = <4>; |
Dinh Nguyen | bd785ef | 2014-04-02 21:14:57 -0500 | [diff] [blame] | 697 | clocks = <&l4_sp_clk>; |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 698 | }; |
Dinh Nguyen | 9c4566a | 2012-10-25 10:41:39 -0600 | [diff] [blame] | 699 | |
Steffen Trumtrar | 16fb4f8 | 2014-04-15 17:27:07 -0500 | [diff] [blame] | 700 | rst: rstmgr@ffd05000 { |
Vince Bridgers | dc8fbed | 2014-06-23 13:32:11 -0500 | [diff] [blame] | 701 | #reset-cells = <1>; |
Steffen Trumtrar | 7857d56 | 2013-10-07 10:44:07 -0500 | [diff] [blame] | 702 | compatible = "altr,rst-mgr"; |
| 703 | reg = <0xffd05000 0x1000>; |
| 704 | }; |
Dinh Nguyen | 9c4566a | 2012-10-25 10:41:39 -0600 | [diff] [blame] | 705 | |
Dinh Nguyen | 1403250 | 2013-10-28 09:48:32 -0500 | [diff] [blame] | 706 | usbphy0: usbphy@0 { |
| 707 | #phy-cells = <0>; |
| 708 | compatible = "usb-nop-xceiv"; |
| 709 | status = "okay"; |
| 710 | }; |
| 711 | |
| 712 | usb0: usb@ffb00000 { |
| 713 | compatible = "snps,dwc2"; |
| 714 | reg = <0xffb00000 0xffff>; |
| 715 | interrupts = <0 125 4>; |
| 716 | clocks = <&usb_mp_clk>; |
| 717 | clock-names = "otg"; |
| 718 | phys = <&usbphy0>; |
| 719 | phy-names = "usb2-phy"; |
| 720 | status = "disabled"; |
| 721 | }; |
| 722 | |
| 723 | usb1: usb@ffb40000 { |
| 724 | compatible = "snps,dwc2"; |
| 725 | reg = <0xffb40000 0xffff>; |
| 726 | interrupts = <0 128 4>; |
| 727 | clocks = <&usb_mp_clk>; |
| 728 | clock-names = "otg"; |
| 729 | phys = <&usbphy0>; |
| 730 | phy-names = "usb2-phy"; |
| 731 | status = "disabled"; |
| 732 | }; |
| 733 | |
Steffen Trumtrar | a98b605 | 2014-05-22 16:37:17 -0500 | [diff] [blame] | 734 | watchdog0: watchdog@ffd02000 { |
| 735 | compatible = "snps,dw-wdt"; |
| 736 | reg = <0xffd02000 0x1000>; |
| 737 | interrupts = <0 171 4>; |
| 738 | clocks = <&osc1>; |
| 739 | status = "disabled"; |
| 740 | }; |
| 741 | |
| 742 | watchdog1: watchdog@ffd03000 { |
| 743 | compatible = "snps,dw-wdt"; |
| 744 | reg = <0xffd03000 0x1000>; |
| 745 | interrupts = <0 172 4>; |
| 746 | clocks = <&osc1>; |
| 747 | status = "disabled"; |
| 748 | }; |
| 749 | |
Dinh Nguyen | a5d6ac2 | 2014-03-09 23:12:14 -0500 | [diff] [blame] | 750 | sysmgr: sysmgr@ffd08000 { |
Dinh Nguyen | 9b93136 | 2014-02-17 20:31:02 -0600 | [diff] [blame] | 751 | compatible = "altr,sys-mgr", "syscon"; |
| 752 | reg = <0xffd08000 0x4000>; |
| 753 | }; |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 754 | }; |
| 755 | }; |