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Chris Leechc13c8262006-05-23 17:18:44 -07001#
2# DMA engine configuration
3#
4
Shannon Nelson2ed6dc32007-10-16 01:27:42 -07005menuconfig DMADEVICES
Haavard Skinnemoen6d4f5872007-11-28 16:21:43 -08006 bool "DMA Engine support"
Dan Williams04ce9ab2009-06-03 14:22:28 -07007 depends on HAS_DMA
Shannon Nelson2ed6dc32007-10-16 01:27:42 -07008 help
Haavard Skinnemoen6d4f5872007-11-28 16:21:43 -08009 DMA engines can do asynchronous data transfers without
10 involving the host CPU. Currently, this framework can be
11 used to offload memory copies in the network stack and
Dan Williams9c402f42008-06-27 01:21:11 -070012 RAID operations in the MD driver. This menu only presents
13 DMA Device drivers supported by the configured arch, it may
14 be empty in some cases.
Chris Leechc13c8262006-05-23 17:18:44 -070015
Linus Walleij6c664a82010-02-09 22:34:54 +010016config DMADEVICES_DEBUG
17 bool "DMA Engine debugging"
18 depends on DMADEVICES != n
19 help
20 This is an option for use by developers; most people should
21 say N here. This enables DMA engine core and driver debugging.
22
23config DMADEVICES_VDEBUG
24 bool "DMA Engine verbose debugging"
25 depends on DMADEVICES_DEBUG != n
26 help
27 This is an option for use by developers; most people should
28 say N here. This enables deeper (more verbose) debugging of
29 the DMA engine core and drivers.
30
31
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070032if DMADEVICES
Chris Leechdb217332006-06-17 21:24:58 -070033
Chris Leech0bbd5f42006-05-23 17:35:34 -070034comment "DMA Devices"
35
Dan Williams138f4c32009-09-08 17:42:51 -070036config ASYNC_TX_DISABLE_CHANNEL_SWITCH
37 bool
38
Chris Leech0bbd5f42006-05-23 17:35:34 -070039config INTEL_IOATDMA
40 tristate "Intel I/OAT DMA support"
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070041 depends on PCI && X86
42 select DMA_ENGINE
43 select DCA
Dan Williams138f4c32009-09-08 17:42:51 -070044 select ASYNC_TX_DISABLE_CHANNEL_SWITCH
Dan Williams7b3cc2b2009-11-19 17:10:37 -070045 select ASYNC_TX_DISABLE_PQ_VAL_DMA
46 select ASYNC_TX_DISABLE_XOR_VAL_DMA
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070047 help
48 Enable support for the Intel(R) I/OAT DMA engine present
49 in recent Intel Xeon chipsets.
50
51 Say Y here if you have such a chipset.
52
53 If unsure, say N.
Dan Williamsc2110922007-01-02 13:52:26 -070054
55config INTEL_IOP_ADMA
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070056 tristate "Intel IOP ADMA support"
57 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070058 select DMA_ENGINE
59 help
60 Enable support for the Intel(R) IOP Series RAID engines.
Dan Williamsc2110922007-01-02 13:52:26 -070061
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070062config DW_DMAC
63 tristate "Synopsys DesignWare AHB DMA support"
64 depends on AVR32
65 select DMA_ENGINE
66 default y if CPU_AT32AP7000
67 help
68 Support the Synopsys DesignWare AHB DMA controller. This
69 can be integrated in chips such as the Atmel AT32ap7000.
70
Nicolas Ferredc78baa2009-07-03 19:24:33 +020071config AT_HDMAC
72 tristate "Atmel AHB DMA support"
Yegor Yefremovcd3abf92009-10-23 11:27:59 +010073 depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
Nicolas Ferredc78baa2009-07-03 19:24:33 +020074 select DMA_ENGINE
75 help
76 Support the Atmel AHB DMA controller. This can be integrated in
77 chips such as the Atmel AT91SAM9RL.
78
Zhang Wei173acc72008-03-01 07:42:48 -070079config FSL_DMA
Timur Tabi77cd62e2008-09-26 17:00:11 -070080 tristate "Freescale Elo and Elo Plus DMA support"
81 depends on FSL_SOC
Zhang Wei173acc72008-03-01 07:42:48 -070082 select DMA_ENGINE
83 ---help---
Timur Tabi77cd62e2008-09-26 17:00:11 -070084 Enable support for the Freescale Elo and Elo Plus DMA controllers.
85 The Elo is the DMA controller on some 82xx and 83xx parts, and the
86 Elo Plus is the DMA controller on 85xx and 86xx parts.
Zhang Wei173acc72008-03-01 07:42:48 -070087
Piotr Ziecik0fb6f732010-02-05 03:42:52 +000088config MPC512X_DMA
89 tristate "Freescale MPC512x built-in DMA engine support"
90 depends on PPC_MPC512x
91 select DMA_ENGINE
92 ---help---
93 Enable support for the Freescale MPC512x built-in DMA engine.
94
Saeed Bisharaff7b0472008-07-08 11:58:36 -070095config MV_XOR
96 bool "Marvell XOR engine support"
97 depends on PLAT_ORION
Saeed Bisharaff7b0472008-07-08 11:58:36 -070098 select DMA_ENGINE
99 ---help---
100 Enable support for the Marvell XOR engine.
101
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700102config MX3_IPU
103 bool "MX3x Image Processing Unit support"
104 depends on ARCH_MX3
105 select DMA_ENGINE
106 default y
107 help
108 If you plan to use the Image Processing unit in the i.MX3x, say
109 Y here. If unsure, select Y.
110
111config MX3_IPU_IRQS
112 int "Number of dynamically mapped interrupts for IPU"
113 depends on MX3_IPU
114 range 2 137
115 default 4
116 help
117 Out of 137 interrupt sources on i.MX31 IPU only very few are used.
118 To avoid bloating the irq_desc[] array we allocate a sufficient
119 number of IRQ slots and map them dynamically to specific sources.
120
Atsushi Nemotoea76f0b2009-04-23 00:40:30 +0900121config TXX9_DMAC
122 tristate "Toshiba TXx9 SoC DMA support"
123 depends on MACH_TX49XX || MACH_TX39XX
124 select DMA_ENGINE
125 help
126 Support the TXx9 SoC internal DMA controller. This can be
127 integrated in chips such as the Toshiba TX4927/38/39.
128
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000129config SH_DMAE
130 tristate "Renesas SuperH DMAC support"
131 depends on SUPERH && SH_DMA
132 depends on !SH_DMA_API
133 select DMA_ENGINE
134 help
135 Enable support for the Renesas SuperH DMA controllers.
136
Linus Walleij61f135b2009-11-19 19:49:17 +0100137config COH901318
138 bool "ST-Ericsson COH901318 DMA support"
139 select DMA_ENGINE
140 depends on ARCH_U300
141 help
142 Enable support for ST-Ericsson COH 901 318 DMA.
143
Anatolij Gustschin12458ea2009-12-11 21:24:44 -0700144config AMCC_PPC440SPE_ADMA
145 tristate "AMCC PPC440SPe ADMA support"
146 depends on 440SPe || 440SP
147 select DMA_ENGINE
148 select ARCH_HAS_ASYNC_TX_FIND_CHANNEL
149 help
150 Enable support for the AMCC PPC440SPe RAID engines.
151
152config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
153 bool
154
Shannon Nelson2ed6dc32007-10-16 01:27:42 -0700155config DMA_ENGINE
156 bool
157
158comment "DMA Clients"
159 depends on DMA_ENGINE
160
161config NET_DMA
162 bool "Network: TCP receive copy offload"
163 depends on DMA_ENGINE && NET
Dan Williams9c402f42008-06-27 01:21:11 -0700164 default (INTEL_IOATDMA || FSL_DMA)
Shannon Nelson2ed6dc32007-10-16 01:27:42 -0700165 help
166 This enables the use of DMA engines in the network stack to
167 offload receive copy-to-user operations, freeing CPU cycles.
Dan Williams9c402f42008-06-27 01:21:11 -0700168
169 Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
170 say N.
Shannon Nelson2ed6dc32007-10-16 01:27:42 -0700171
Dan Williams729b5d12009-03-25 09:13:25 -0700172config ASYNC_TX_DMA
173 bool "Async_tx: Offload support for the async_tx api"
Dan Williams9a8de632009-09-08 15:06:10 -0700174 depends on DMA_ENGINE
Dan Williams729b5d12009-03-25 09:13:25 -0700175 help
176 This allows the async_tx api to take advantage of offload engines for
177 memcpy, memset, xor, and raid6 p+q operations. If your platform has
178 a dma engine that can perform raid operations and you have enabled
179 MD_RAID456 say Y.
180
181 If unsure, say N.
182
Haavard Skinnemoen4a776f02008-07-08 11:58:45 -0700183config DMATEST
184 tristate "DMA Test client"
185 depends on DMA_ENGINE
186 help
187 Simple DMA test client. Say N unless you're debugging a
188 DMA Device driver.
189
Shannon Nelson2ed6dc32007-10-16 01:27:42 -0700190endif