Grant Likely | ca632f5 | 2011-06-06 01:16:30 -0600 | [diff] [blame] | 1 | /* |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 2 | * Copyright (C) 2009 Samsung Electronics Ltd. |
| 3 | * Jaswinder Singh <jassi.brar@samsung.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; either version 2 of the License, or |
| 8 | * (at your option) any later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 18 | */ |
| 19 | |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/module.h> |
| 22 | #include <linux/workqueue.h> |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 23 | #include <linux/interrupt.h> |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 24 | #include <linux/delay.h> |
| 25 | #include <linux/clk.h> |
| 26 | #include <linux/dma-mapping.h> |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 27 | #include <linux/dmaengine.h> |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 28 | #include <linux/platform_device.h> |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 29 | #include <linux/pm_runtime.h> |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 30 | #include <linux/spi/spi.h> |
Thomas Abraham | 1c20c20 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 31 | #include <linux/gpio.h> |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 32 | #include <linux/of.h> |
| 33 | #include <linux/of_gpio.h> |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 34 | |
Arnd Bergmann | 436d42c | 2012-08-24 15:22:12 +0200 | [diff] [blame] | 35 | #include <linux/platform_data/spi-s3c64xx.h> |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 36 | |
Mark Brown | 563b444 | 2013-04-18 18:06:05 +0100 | [diff] [blame] | 37 | #ifdef CONFIG_S3C_DMA |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 38 | #include <mach/dma.h> |
| 39 | #endif |
| 40 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 41 | #define MAX_SPI_PORTS 3 |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 42 | #define S3C64XX_SPI_QUIRK_POLL (1 << 0) |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 43 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 44 | /* Registers and bit-fields */ |
| 45 | |
| 46 | #define S3C64XX_SPI_CH_CFG 0x00 |
| 47 | #define S3C64XX_SPI_CLK_CFG 0x04 |
| 48 | #define S3C64XX_SPI_MODE_CFG 0x08 |
| 49 | #define S3C64XX_SPI_SLAVE_SEL 0x0C |
| 50 | #define S3C64XX_SPI_INT_EN 0x10 |
| 51 | #define S3C64XX_SPI_STATUS 0x14 |
| 52 | #define S3C64XX_SPI_TX_DATA 0x18 |
| 53 | #define S3C64XX_SPI_RX_DATA 0x1C |
| 54 | #define S3C64XX_SPI_PACKET_CNT 0x20 |
| 55 | #define S3C64XX_SPI_PENDING_CLR 0x24 |
| 56 | #define S3C64XX_SPI_SWAP_CFG 0x28 |
| 57 | #define S3C64XX_SPI_FB_CLK 0x2C |
| 58 | |
| 59 | #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */ |
| 60 | #define S3C64XX_SPI_CH_SW_RST (1<<5) |
| 61 | #define S3C64XX_SPI_CH_SLAVE (1<<4) |
| 62 | #define S3C64XX_SPI_CPOL_L (1<<3) |
| 63 | #define S3C64XX_SPI_CPHA_B (1<<2) |
| 64 | #define S3C64XX_SPI_CH_RXCH_ON (1<<1) |
| 65 | #define S3C64XX_SPI_CH_TXCH_ON (1<<0) |
| 66 | |
| 67 | #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) |
| 68 | #define S3C64XX_SPI_CLKSEL_SRCSHFT 9 |
| 69 | #define S3C64XX_SPI_ENCLK_ENABLE (1<<8) |
Jingoo Han | 75bf336 | 2013-01-31 15:25:01 +0900 | [diff] [blame] | 70 | #define S3C64XX_SPI_PSR_MASK 0xff |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 71 | |
| 72 | #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) |
| 73 | #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) |
| 74 | #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29) |
| 75 | #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29) |
| 76 | #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17) |
| 77 | #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) |
| 78 | #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) |
| 79 | #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) |
| 80 | #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) |
| 81 | #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) |
| 82 | #define S3C64XX_SPI_MODE_4BURST (1<<0) |
| 83 | |
| 84 | #define S3C64XX_SPI_SLAVE_AUTO (1<<1) |
| 85 | #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0) |
| 86 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 87 | #define S3C64XX_SPI_INT_TRAILING_EN (1<<6) |
| 88 | #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) |
| 89 | #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) |
| 90 | #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3) |
| 91 | #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2) |
| 92 | #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) |
| 93 | #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) |
| 94 | |
| 95 | #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) |
| 96 | #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) |
| 97 | #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) |
| 98 | #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2) |
| 99 | #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1) |
| 100 | #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) |
| 101 | |
| 102 | #define S3C64XX_SPI_PACKET_CNT_EN (1<<16) |
| 103 | |
| 104 | #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) |
| 105 | #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) |
| 106 | #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2) |
| 107 | #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1) |
| 108 | #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0) |
| 109 | |
| 110 | #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7) |
| 111 | #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6) |
| 112 | #define S3C64XX_SPI_SWAP_RX_BIT (1<<5) |
| 113 | #define S3C64XX_SPI_SWAP_RX_EN (1<<4) |
| 114 | #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3) |
| 115 | #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2) |
| 116 | #define S3C64XX_SPI_SWAP_TX_BIT (1<<1) |
| 117 | #define S3C64XX_SPI_SWAP_TX_EN (1<<0) |
| 118 | |
| 119 | #define S3C64XX_SPI_FBCLK_MSK (3<<0) |
| 120 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 121 | #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) |
| 122 | #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ |
| 123 | (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) |
| 124 | #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) |
| 125 | #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ |
| 126 | FIFO_LVL_MASK(i)) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 127 | |
| 128 | #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff |
| 129 | #define S3C64XX_SPI_TRAILCNT_OFF 19 |
| 130 | |
| 131 | #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT |
| 132 | |
| 133 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 134 | #define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 135 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 136 | #define RXBUSY (1<<2) |
| 137 | #define TXBUSY (1<<3) |
| 138 | |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 139 | struct s3c64xx_spi_dma_data { |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 140 | struct dma_chan *ch; |
Arnd Bergmann | c10356b | 2012-04-30 16:31:27 +0000 | [diff] [blame] | 141 | enum dma_transfer_direction direction; |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 142 | unsigned int dmach; |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 143 | }; |
| 144 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 145 | /** |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 146 | * struct s3c64xx_spi_info - SPI Controller hardware info |
| 147 | * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. |
| 148 | * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. |
| 149 | * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. |
| 150 | * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. |
| 151 | * @clk_from_cmu: True, if the controller does not include a clock mux and |
| 152 | * prescaler unit. |
| 153 | * |
| 154 | * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but |
| 155 | * differ in some aspects such as the size of the fifo and spi bus clock |
| 156 | * setup. Such differences are specified to the driver using this structure |
| 157 | * which is provided as driver data to the driver. |
| 158 | */ |
| 159 | struct s3c64xx_spi_port_config { |
| 160 | int fifo_lvl_mask[MAX_SPI_PORTS]; |
| 161 | int rx_lvl_offset; |
| 162 | int tx_st_done; |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 163 | int quirks; |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 164 | bool high_speed; |
| 165 | bool clk_from_cmu; |
| 166 | }; |
| 167 | |
| 168 | /** |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 169 | * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver. |
| 170 | * @clk: Pointer to the spi clock. |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 171 | * @src_clk: Pointer to the clock used to generate SPI signals. |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 172 | * @master: Pointer to the SPI Protocol master. |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 173 | * @cntrlr_info: Platform specific data for the controller this driver manages. |
| 174 | * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint. |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 175 | * @lock: Controller specific lock. |
| 176 | * @state: Set of FLAGS to indicate status. |
| 177 | * @rx_dmach: Controller's DMA channel for Rx. |
| 178 | * @tx_dmach: Controller's DMA channel for Tx. |
| 179 | * @sfr_start: BUS address of SPI controller regs. |
| 180 | * @regs: Pointer to ioremap'ed controller registers. |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 181 | * @irq: interrupt |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 182 | * @xfer_completion: To indicate completion of xfer task. |
| 183 | * @cur_mode: Stores the active configuration of the controller. |
| 184 | * @cur_bpw: Stores the active bits per word settings. |
| 185 | * @cur_speed: Stores the active xfer clock speed. |
| 186 | */ |
| 187 | struct s3c64xx_spi_driver_data { |
| 188 | void __iomem *regs; |
| 189 | struct clk *clk; |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 190 | struct clk *src_clk; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 191 | struct platform_device *pdev; |
| 192 | struct spi_master *master; |
Jassi Brar | ad7de72 | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 193 | struct s3c64xx_spi_info *cntrlr_info; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 194 | struct spi_device *tgl_spi; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 195 | spinlock_t lock; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 196 | unsigned long sfr_start; |
| 197 | struct completion xfer_completion; |
| 198 | unsigned state; |
| 199 | unsigned cur_mode, cur_bpw; |
| 200 | unsigned cur_speed; |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 201 | struct s3c64xx_spi_dma_data rx_dma; |
| 202 | struct s3c64xx_spi_dma_data tx_dma; |
Mark Brown | 563b444 | 2013-04-18 18:06:05 +0100 | [diff] [blame] | 203 | #ifdef CONFIG_S3C_DMA |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 204 | struct samsung_dma_ops *ops; |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 205 | #endif |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 206 | struct s3c64xx_spi_port_config *port_conf; |
| 207 | unsigned int port_id; |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 208 | unsigned long gpios[4]; |
Girish K S | 3146bee | 2013-06-21 11:26:12 +0530 | [diff] [blame] | 209 | bool cs_gpio; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 210 | }; |
| 211 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 212 | static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) |
| 213 | { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 214 | void __iomem *regs = sdd->regs; |
| 215 | unsigned long loops; |
| 216 | u32 val; |
| 217 | |
| 218 | writel(0, regs + S3C64XX_SPI_PACKET_CNT); |
| 219 | |
| 220 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
Kyoungil Kim | 7d859ff | 2012-05-23 21:29:51 +0900 | [diff] [blame] | 221 | val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); |
| 222 | writel(val, regs + S3C64XX_SPI_CH_CFG); |
| 223 | |
| 224 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 225 | val |= S3C64XX_SPI_CH_SW_RST; |
| 226 | val &= ~S3C64XX_SPI_CH_HS_EN; |
| 227 | writel(val, regs + S3C64XX_SPI_CH_CFG); |
| 228 | |
| 229 | /* Flush TxFIFO*/ |
| 230 | loops = msecs_to_loops(1); |
| 231 | do { |
| 232 | val = readl(regs + S3C64XX_SPI_STATUS); |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 233 | } while (TX_FIFO_LVL(val, sdd) && loops--); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 234 | |
Mark Brown | be7852a | 2010-08-23 17:40:56 +0100 | [diff] [blame] | 235 | if (loops == 0) |
| 236 | dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); |
| 237 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 238 | /* Flush RxFIFO*/ |
| 239 | loops = msecs_to_loops(1); |
| 240 | do { |
| 241 | val = readl(regs + S3C64XX_SPI_STATUS); |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 242 | if (RX_FIFO_LVL(val, sdd)) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 243 | readl(regs + S3C64XX_SPI_RX_DATA); |
| 244 | else |
| 245 | break; |
| 246 | } while (loops--); |
| 247 | |
Mark Brown | be7852a | 2010-08-23 17:40:56 +0100 | [diff] [blame] | 248 | if (loops == 0) |
| 249 | dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); |
| 250 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 251 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
| 252 | val &= ~S3C64XX_SPI_CH_SW_RST; |
| 253 | writel(val, regs + S3C64XX_SPI_CH_CFG); |
| 254 | |
| 255 | val = readl(regs + S3C64XX_SPI_MODE_CFG); |
| 256 | val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); |
| 257 | writel(val, regs + S3C64XX_SPI_MODE_CFG); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 258 | } |
| 259 | |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 260 | static void s3c64xx_spi_dmacb(void *data) |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 261 | { |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 262 | struct s3c64xx_spi_driver_data *sdd; |
| 263 | struct s3c64xx_spi_dma_data *dma = data; |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 264 | unsigned long flags; |
| 265 | |
Kyoungil Kim | 054ebcc | 2012-03-10 09:48:46 +0900 | [diff] [blame] | 266 | if (dma->direction == DMA_DEV_TO_MEM) |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 267 | sdd = container_of(data, |
| 268 | struct s3c64xx_spi_driver_data, rx_dma); |
| 269 | else |
| 270 | sdd = container_of(data, |
| 271 | struct s3c64xx_spi_driver_data, tx_dma); |
| 272 | |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 273 | spin_lock_irqsave(&sdd->lock, flags); |
| 274 | |
Kyoungil Kim | 054ebcc | 2012-03-10 09:48:46 +0900 | [diff] [blame] | 275 | if (dma->direction == DMA_DEV_TO_MEM) { |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 276 | sdd->state &= ~RXBUSY; |
| 277 | if (!(sdd->state & TXBUSY)) |
| 278 | complete(&sdd->xfer_completion); |
| 279 | } else { |
| 280 | sdd->state &= ~TXBUSY; |
| 281 | if (!(sdd->state & RXBUSY)) |
| 282 | complete(&sdd->xfer_completion); |
| 283 | } |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 284 | |
| 285 | spin_unlock_irqrestore(&sdd->lock, flags); |
| 286 | } |
| 287 | |
Mark Brown | 563b444 | 2013-04-18 18:06:05 +0100 | [diff] [blame] | 288 | #ifdef CONFIG_S3C_DMA |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 289 | /* FIXME: remove this section once arch/arm/mach-s3c64xx uses dmaengine */ |
| 290 | |
| 291 | static struct s3c2410_dma_client s3c64xx_spi_dma_client = { |
| 292 | .name = "samsung-spi-dma", |
| 293 | }; |
| 294 | |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 295 | static void prepare_dma(struct s3c64xx_spi_dma_data *dma, |
| 296 | unsigned len, dma_addr_t buf) |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 297 | { |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 298 | struct s3c64xx_spi_driver_data *sdd; |
Boojin Kim | 4969c32 | 2012-06-19 13:27:03 +0900 | [diff] [blame] | 299 | struct samsung_dma_prep info; |
| 300 | struct samsung_dma_config config; |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 301 | |
Boojin Kim | 4969c32 | 2012-06-19 13:27:03 +0900 | [diff] [blame] | 302 | if (dma->direction == DMA_DEV_TO_MEM) { |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 303 | sdd = container_of((void *)dma, |
| 304 | struct s3c64xx_spi_driver_data, rx_dma); |
Boojin Kim | 4969c32 | 2012-06-19 13:27:03 +0900 | [diff] [blame] | 305 | config.direction = sdd->rx_dma.direction; |
| 306 | config.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA; |
| 307 | config.width = sdd->cur_bpw / 8; |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 308 | sdd->ops->config((enum dma_ch)sdd->rx_dma.ch, &config); |
Boojin Kim | 4969c32 | 2012-06-19 13:27:03 +0900 | [diff] [blame] | 309 | } else { |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 310 | sdd = container_of((void *)dma, |
| 311 | struct s3c64xx_spi_driver_data, tx_dma); |
Boojin Kim | 4969c32 | 2012-06-19 13:27:03 +0900 | [diff] [blame] | 312 | config.direction = sdd->tx_dma.direction; |
| 313 | config.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA; |
| 314 | config.width = sdd->cur_bpw / 8; |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 315 | sdd->ops->config((enum dma_ch)sdd->tx_dma.ch, &config); |
Boojin Kim | 4969c32 | 2012-06-19 13:27:03 +0900 | [diff] [blame] | 316 | } |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 317 | |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 318 | info.cap = DMA_SLAVE; |
| 319 | info.len = len; |
| 320 | info.fp = s3c64xx_spi_dmacb; |
| 321 | info.fp_param = dma; |
| 322 | info.direction = dma->direction; |
| 323 | info.buf = buf; |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 324 | |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 325 | sdd->ops->prepare((enum dma_ch)dma->ch, &info); |
| 326 | sdd->ops->trigger((enum dma_ch)dma->ch); |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 327 | } |
| 328 | |
| 329 | static int acquire_dma(struct s3c64xx_spi_driver_data *sdd) |
| 330 | { |
Boojin Kim | 4969c32 | 2012-06-19 13:27:03 +0900 | [diff] [blame] | 331 | struct samsung_dma_req req; |
Padmavathi Venna | b5be04d | 2013-01-18 17:17:03 +0530 | [diff] [blame] | 332 | struct device *dev = &sdd->pdev->dev; |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 333 | |
| 334 | sdd->ops = samsung_dma_get_ops(); |
| 335 | |
Boojin Kim | 4969c32 | 2012-06-19 13:27:03 +0900 | [diff] [blame] | 336 | req.cap = DMA_SLAVE; |
| 337 | req.client = &s3c64xx_spi_dma_client; |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 338 | |
Jingoo Han | b998aca8 | 2013-07-17 17:54:11 +0900 | [diff] [blame] | 339 | sdd->rx_dma.ch = (struct dma_chan *)(unsigned long)sdd->ops->request( |
| 340 | sdd->rx_dma.dmach, &req, dev, "rx"); |
| 341 | sdd->tx_dma.ch = (struct dma_chan *)(unsigned long)sdd->ops->request( |
| 342 | sdd->tx_dma.dmach, &req, dev, "tx"); |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 343 | |
| 344 | return 1; |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 345 | } |
| 346 | |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 347 | static int s3c64xx_spi_prepare_transfer(struct spi_master *spi) |
| 348 | { |
| 349 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); |
| 350 | |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 351 | /* |
| 352 | * If DMA resource was not available during |
| 353 | * probe, no need to continue with dma requests |
| 354 | * else Acquire DMA channels |
| 355 | */ |
| 356 | while (!is_polling(sdd) && !acquire_dma(sdd)) |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 357 | usleep_range(10000, 11000); |
| 358 | |
| 359 | pm_runtime_get_sync(&sdd->pdev->dev); |
| 360 | |
| 361 | return 0; |
| 362 | } |
| 363 | |
| 364 | static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi) |
| 365 | { |
| 366 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); |
| 367 | |
| 368 | /* Free DMA channels */ |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 369 | if (!is_polling(sdd)) { |
| 370 | sdd->ops->release((enum dma_ch)sdd->rx_dma.ch, |
| 371 | &s3c64xx_spi_dma_client); |
| 372 | sdd->ops->release((enum dma_ch)sdd->tx_dma.ch, |
| 373 | &s3c64xx_spi_dma_client); |
| 374 | } |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 375 | pm_runtime_put(&sdd->pdev->dev); |
| 376 | |
| 377 | return 0; |
| 378 | } |
| 379 | |
| 380 | static void s3c64xx_spi_dma_stop(struct s3c64xx_spi_driver_data *sdd, |
| 381 | struct s3c64xx_spi_dma_data *dma) |
| 382 | { |
| 383 | sdd->ops->stop((enum dma_ch)dma->ch); |
| 384 | } |
| 385 | #else |
| 386 | |
| 387 | static void prepare_dma(struct s3c64xx_spi_dma_data *dma, |
| 388 | unsigned len, dma_addr_t buf) |
| 389 | { |
| 390 | struct s3c64xx_spi_driver_data *sdd; |
| 391 | struct dma_slave_config config; |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 392 | struct dma_async_tx_descriptor *desc; |
| 393 | |
Tomasz Figa | b1a8e78 | 2013-08-11 02:33:28 +0200 | [diff] [blame] | 394 | memset(&config, 0, sizeof(config)); |
| 395 | |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 396 | if (dma->direction == DMA_DEV_TO_MEM) { |
| 397 | sdd = container_of((void *)dma, |
| 398 | struct s3c64xx_spi_driver_data, rx_dma); |
| 399 | config.direction = dma->direction; |
| 400 | config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA; |
| 401 | config.src_addr_width = sdd->cur_bpw / 8; |
| 402 | config.src_maxburst = 1; |
| 403 | dmaengine_slave_config(dma->ch, &config); |
| 404 | } else { |
| 405 | sdd = container_of((void *)dma, |
| 406 | struct s3c64xx_spi_driver_data, tx_dma); |
| 407 | config.direction = dma->direction; |
| 408 | config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA; |
| 409 | config.dst_addr_width = sdd->cur_bpw / 8; |
| 410 | config.dst_maxburst = 1; |
| 411 | dmaengine_slave_config(dma->ch, &config); |
| 412 | } |
| 413 | |
Tomasz Figa | 90438c4 | 2013-08-11 02:33:30 +0200 | [diff] [blame] | 414 | desc = dmaengine_prep_slave_single(dma->ch, buf, len, |
| 415 | dma->direction, DMA_PREP_INTERRUPT); |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 416 | |
| 417 | desc->callback = s3c64xx_spi_dmacb; |
| 418 | desc->callback_param = dma; |
| 419 | |
| 420 | dmaengine_submit(desc); |
| 421 | dma_async_issue_pending(dma->ch); |
| 422 | } |
| 423 | |
| 424 | static int s3c64xx_spi_prepare_transfer(struct spi_master *spi) |
| 425 | { |
| 426 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); |
| 427 | dma_filter_fn filter = sdd->cntrlr_info->filter; |
| 428 | struct device *dev = &sdd->pdev->dev; |
| 429 | dma_cap_mask_t mask; |
Mark Brown | fb9d044 | 2013-04-18 18:12:00 +0100 | [diff] [blame] | 430 | int ret; |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 431 | |
Girish K S | 9f4b323 | 2013-06-27 12:26:53 +0530 | [diff] [blame] | 432 | if (is_polling(sdd)) |
| 433 | return 0; |
| 434 | |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 435 | dma_cap_zero(mask); |
| 436 | dma_cap_set(DMA_SLAVE, mask); |
| 437 | |
| 438 | /* Acquire DMA channels */ |
| 439 | sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter, |
Jingoo Han | db0606e | 2013-07-15 15:11:57 +0900 | [diff] [blame] | 440 | (void *)sdd->rx_dma.dmach, dev, "rx"); |
Mark Brown | fb9d044 | 2013-04-18 18:12:00 +0100 | [diff] [blame] | 441 | if (!sdd->rx_dma.ch) { |
| 442 | dev_err(dev, "Failed to get RX DMA channel\n"); |
| 443 | ret = -EBUSY; |
| 444 | goto out; |
| 445 | } |
| 446 | |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 447 | sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter, |
Jingoo Han | db0606e | 2013-07-15 15:11:57 +0900 | [diff] [blame] | 448 | (void *)sdd->tx_dma.dmach, dev, "tx"); |
Mark Brown | fb9d044 | 2013-04-18 18:12:00 +0100 | [diff] [blame] | 449 | if (!sdd->tx_dma.ch) { |
| 450 | dev_err(dev, "Failed to get TX DMA channel\n"); |
| 451 | ret = -EBUSY; |
| 452 | goto out_rx; |
| 453 | } |
| 454 | |
| 455 | ret = pm_runtime_get_sync(&sdd->pdev->dev); |
Sylwester Nawrocki | 6c6cf64 | 2013-06-10 18:22:26 +0200 | [diff] [blame] | 456 | if (ret < 0) { |
Mark Brown | fb9d044 | 2013-04-18 18:12:00 +0100 | [diff] [blame] | 457 | dev_err(dev, "Failed to enable device: %d\n", ret); |
| 458 | goto out_tx; |
| 459 | } |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 460 | |
| 461 | return 0; |
Mark Brown | fb9d044 | 2013-04-18 18:12:00 +0100 | [diff] [blame] | 462 | |
| 463 | out_tx: |
| 464 | dma_release_channel(sdd->tx_dma.ch); |
| 465 | out_rx: |
| 466 | dma_release_channel(sdd->rx_dma.ch); |
| 467 | out: |
| 468 | return ret; |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 469 | } |
| 470 | |
| 471 | static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi) |
| 472 | { |
| 473 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); |
| 474 | |
| 475 | /* Free DMA channels */ |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 476 | if (!is_polling(sdd)) { |
| 477 | dma_release_channel(sdd->rx_dma.ch); |
| 478 | dma_release_channel(sdd->tx_dma.ch); |
| 479 | } |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 480 | |
| 481 | pm_runtime_put(&sdd->pdev->dev); |
| 482 | return 0; |
| 483 | } |
| 484 | |
| 485 | static void s3c64xx_spi_dma_stop(struct s3c64xx_spi_driver_data *sdd, |
| 486 | struct s3c64xx_spi_dma_data *dma) |
| 487 | { |
| 488 | dmaengine_terminate_all(dma->ch); |
| 489 | } |
| 490 | #endif |
| 491 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 492 | static void enable_datapath(struct s3c64xx_spi_driver_data *sdd, |
| 493 | struct spi_device *spi, |
| 494 | struct spi_transfer *xfer, int dma_mode) |
| 495 | { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 496 | void __iomem *regs = sdd->regs; |
| 497 | u32 modecfg, chcfg; |
| 498 | |
| 499 | modecfg = readl(regs + S3C64XX_SPI_MODE_CFG); |
| 500 | modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); |
| 501 | |
| 502 | chcfg = readl(regs + S3C64XX_SPI_CH_CFG); |
| 503 | chcfg &= ~S3C64XX_SPI_CH_TXCH_ON; |
| 504 | |
| 505 | if (dma_mode) { |
| 506 | chcfg &= ~S3C64XX_SPI_CH_RXCH_ON; |
| 507 | } else { |
| 508 | /* Always shift in data in FIFO, even if xfer is Tx only, |
| 509 | * this helps setting PCKT_CNT value for generating clocks |
| 510 | * as exactly needed. |
| 511 | */ |
| 512 | chcfg |= S3C64XX_SPI_CH_RXCH_ON; |
| 513 | writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) |
| 514 | | S3C64XX_SPI_PACKET_CNT_EN, |
| 515 | regs + S3C64XX_SPI_PACKET_CNT); |
| 516 | } |
| 517 | |
| 518 | if (xfer->tx_buf != NULL) { |
| 519 | sdd->state |= TXBUSY; |
| 520 | chcfg |= S3C64XX_SPI_CH_TXCH_ON; |
| 521 | if (dma_mode) { |
| 522 | modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 523 | prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 524 | } else { |
Jassi Brar | 0c92ecf | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 525 | switch (sdd->cur_bpw) { |
| 526 | case 32: |
| 527 | iowrite32_rep(regs + S3C64XX_SPI_TX_DATA, |
| 528 | xfer->tx_buf, xfer->len / 4); |
| 529 | break; |
| 530 | case 16: |
| 531 | iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, |
| 532 | xfer->tx_buf, xfer->len / 2); |
| 533 | break; |
| 534 | default: |
| 535 | iowrite8_rep(regs + S3C64XX_SPI_TX_DATA, |
| 536 | xfer->tx_buf, xfer->len); |
| 537 | break; |
| 538 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 539 | } |
| 540 | } |
| 541 | |
| 542 | if (xfer->rx_buf != NULL) { |
| 543 | sdd->state |= RXBUSY; |
| 544 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 545 | if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 546 | && !(sdd->cur_mode & SPI_CPHA)) |
| 547 | chcfg |= S3C64XX_SPI_CH_HS_EN; |
| 548 | |
| 549 | if (dma_mode) { |
| 550 | modecfg |= S3C64XX_SPI_MODE_RXDMA_ON; |
| 551 | chcfg |= S3C64XX_SPI_CH_RXCH_ON; |
| 552 | writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) |
| 553 | | S3C64XX_SPI_PACKET_CNT_EN, |
| 554 | regs + S3C64XX_SPI_PACKET_CNT); |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 555 | prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 556 | } |
| 557 | } |
| 558 | |
| 559 | writel(modecfg, regs + S3C64XX_SPI_MODE_CFG); |
| 560 | writel(chcfg, regs + S3C64XX_SPI_CH_CFG); |
| 561 | } |
| 562 | |
| 563 | static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd, |
| 564 | struct spi_device *spi) |
| 565 | { |
| 566 | struct s3c64xx_spi_csinfo *cs; |
| 567 | |
| 568 | if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */ |
| 569 | if (sdd->tgl_spi != spi) { /* if last mssg on diff device */ |
| 570 | /* Deselect the last toggled device */ |
| 571 | cs = sdd->tgl_spi->controller_data; |
Girish K S | 3146bee | 2013-06-21 11:26:12 +0530 | [diff] [blame] | 572 | if (sdd->cs_gpio) |
| 573 | gpio_set_value(cs->line, |
| 574 | spi->mode & SPI_CS_HIGH ? 0 : 1); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 575 | } |
| 576 | sdd->tgl_spi = NULL; |
| 577 | } |
| 578 | |
| 579 | cs = spi->controller_data; |
Girish K S | 3146bee | 2013-06-21 11:26:12 +0530 | [diff] [blame] | 580 | if (sdd->cs_gpio) |
| 581 | gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0); |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 582 | |
| 583 | /* Start the signals */ |
| 584 | writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL); |
| 585 | } |
| 586 | |
Mark Brown | 7961707 | 2013-06-19 19:12:39 +0100 | [diff] [blame] | 587 | static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 588 | int timeout_ms) |
| 589 | { |
| 590 | void __iomem *regs = sdd->regs; |
| 591 | unsigned long val = 1; |
| 592 | u32 status; |
| 593 | |
| 594 | /* max fifo depth available */ |
| 595 | u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1; |
| 596 | |
| 597 | if (timeout_ms) |
| 598 | val = msecs_to_loops(timeout_ms); |
| 599 | |
| 600 | do { |
| 601 | status = readl(regs + S3C64XX_SPI_STATUS); |
| 602 | } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); |
| 603 | |
| 604 | /* return the actual received data length */ |
| 605 | return RX_FIFO_LVL(status, sdd); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 606 | } |
| 607 | |
| 608 | static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd, |
| 609 | struct spi_transfer *xfer, int dma_mode) |
| 610 | { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 611 | void __iomem *regs = sdd->regs; |
| 612 | unsigned long val; |
| 613 | int ms; |
| 614 | |
| 615 | /* millisecs to xfer 'len' bytes @ 'cur_speed' */ |
| 616 | ms = xfer->len * 8 * 1000 / sdd->cur_speed; |
Mark Brown | 9d8f86b | 2010-09-07 16:37:52 +0100 | [diff] [blame] | 617 | ms += 10; /* some tolerance */ |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 618 | |
| 619 | if (dma_mode) { |
| 620 | val = msecs_to_jiffies(ms) + 10; |
| 621 | val = wait_for_completion_timeout(&sdd->xfer_completion, val); |
| 622 | } else { |
Jassi Brar | c3f139b | 2010-09-03 10:36:46 +0900 | [diff] [blame] | 623 | u32 status; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 624 | val = msecs_to_loops(ms); |
| 625 | do { |
Jassi Brar | c3f139b | 2010-09-03 10:36:46 +0900 | [diff] [blame] | 626 | status = readl(regs + S3C64XX_SPI_STATUS); |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 627 | } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 628 | } |
| 629 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 630 | if (dma_mode) { |
| 631 | u32 status; |
| 632 | |
| 633 | /* |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 634 | * If the previous xfer was completed within timeout, then |
| 635 | * proceed further else return -EIO. |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 636 | * DmaTx returns after simply writing data in the FIFO, |
| 637 | * w/o waiting for real transmission on the bus to finish. |
| 638 | * DmaRx returns only after Dma read data from FIFO which |
| 639 | * needs bus transmission to finish, so we don't worry if |
| 640 | * Xfer involved Rx(with or without Tx). |
| 641 | */ |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 642 | if (val && !xfer->rx_buf) { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 643 | val = msecs_to_loops(10); |
| 644 | status = readl(regs + S3C64XX_SPI_STATUS); |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 645 | while ((TX_FIFO_LVL(status, sdd) |
| 646 | || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 647 | && --val) { |
| 648 | cpu_relax(); |
| 649 | status = readl(regs + S3C64XX_SPI_STATUS); |
| 650 | } |
| 651 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 652 | } |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 653 | |
| 654 | /* If timed out while checking rx/tx status return error */ |
| 655 | if (!val) |
| 656 | return -EIO; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 657 | } else { |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 658 | int loops; |
| 659 | u32 cpy_len; |
| 660 | u8 *buf; |
| 661 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 662 | /* If it was only Tx */ |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 663 | if (!xfer->rx_buf) { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 664 | sdd->state &= ~TXBUSY; |
| 665 | return 0; |
| 666 | } |
| 667 | |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 668 | /* |
| 669 | * If the receive length is bigger than the controller fifo |
| 670 | * size, calculate the loops and read the fifo as many times. |
| 671 | * loops = length / max fifo size (calculated by using the |
| 672 | * fifo mask). |
| 673 | * For any size less than the fifo size the below code is |
| 674 | * executed atleast once. |
| 675 | */ |
| 676 | loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1); |
| 677 | buf = xfer->rx_buf; |
| 678 | do { |
| 679 | /* wait for data to be received in the fifo */ |
Mark Brown | 7961707 | 2013-06-19 19:12:39 +0100 | [diff] [blame] | 680 | cpy_len = s3c64xx_spi_wait_for_timeout(sdd, |
| 681 | (loops ? ms : 0)); |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 682 | |
| 683 | switch (sdd->cur_bpw) { |
| 684 | case 32: |
| 685 | ioread32_rep(regs + S3C64XX_SPI_RX_DATA, |
| 686 | buf, cpy_len / 4); |
| 687 | break; |
| 688 | case 16: |
| 689 | ioread16_rep(regs + S3C64XX_SPI_RX_DATA, |
| 690 | buf, cpy_len / 2); |
| 691 | break; |
| 692 | default: |
| 693 | ioread8_rep(regs + S3C64XX_SPI_RX_DATA, |
| 694 | buf, cpy_len); |
| 695 | break; |
| 696 | } |
| 697 | |
| 698 | buf = buf + cpy_len; |
| 699 | } while (loops--); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 700 | sdd->state &= ~RXBUSY; |
| 701 | } |
| 702 | |
| 703 | return 0; |
| 704 | } |
| 705 | |
| 706 | static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd, |
| 707 | struct spi_device *spi) |
| 708 | { |
| 709 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; |
| 710 | |
| 711 | if (sdd->tgl_spi == spi) |
| 712 | sdd->tgl_spi = NULL; |
| 713 | |
Girish K S | 3146bee | 2013-06-21 11:26:12 +0530 | [diff] [blame] | 714 | if (sdd->cs_gpio) |
| 715 | gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1); |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 716 | |
| 717 | /* Quiese the signals */ |
| 718 | writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 719 | } |
| 720 | |
| 721 | static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) |
| 722 | { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 723 | void __iomem *regs = sdd->regs; |
| 724 | u32 val; |
| 725 | |
| 726 | /* Disable Clock */ |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 727 | if (sdd->port_conf->clk_from_cmu) { |
Thomas Abraham | 9f667bf | 2012-10-03 08:30:12 +0900 | [diff] [blame] | 728 | clk_disable_unprepare(sdd->src_clk); |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 729 | } else { |
| 730 | val = readl(regs + S3C64XX_SPI_CLK_CFG); |
| 731 | val &= ~S3C64XX_SPI_ENCLK_ENABLE; |
| 732 | writel(val, regs + S3C64XX_SPI_CLK_CFG); |
| 733 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 734 | |
| 735 | /* Set Polarity and Phase */ |
| 736 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
| 737 | val &= ~(S3C64XX_SPI_CH_SLAVE | |
| 738 | S3C64XX_SPI_CPOL_L | |
| 739 | S3C64XX_SPI_CPHA_B); |
| 740 | |
| 741 | if (sdd->cur_mode & SPI_CPOL) |
| 742 | val |= S3C64XX_SPI_CPOL_L; |
| 743 | |
| 744 | if (sdd->cur_mode & SPI_CPHA) |
| 745 | val |= S3C64XX_SPI_CPHA_B; |
| 746 | |
| 747 | writel(val, regs + S3C64XX_SPI_CH_CFG); |
| 748 | |
| 749 | /* Set Channel & DMA Mode */ |
| 750 | val = readl(regs + S3C64XX_SPI_MODE_CFG); |
| 751 | val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK |
| 752 | | S3C64XX_SPI_MODE_CH_TSZ_MASK); |
| 753 | |
| 754 | switch (sdd->cur_bpw) { |
| 755 | case 32: |
| 756 | val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD; |
Jassi Brar | 0c92ecf | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 757 | val |= S3C64XX_SPI_MODE_CH_TSZ_WORD; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 758 | break; |
| 759 | case 16: |
| 760 | val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; |
Jassi Brar | 0c92ecf | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 761 | val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 762 | break; |
| 763 | default: |
| 764 | val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE; |
Jassi Brar | 0c92ecf | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 765 | val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 766 | break; |
| 767 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 768 | |
| 769 | writel(val, regs + S3C64XX_SPI_MODE_CFG); |
| 770 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 771 | if (sdd->port_conf->clk_from_cmu) { |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 772 | /* Configure Clock */ |
| 773 | /* There is half-multiplier before the SPI */ |
| 774 | clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); |
| 775 | /* Enable Clock */ |
Thomas Abraham | 9f667bf | 2012-10-03 08:30:12 +0900 | [diff] [blame] | 776 | clk_prepare_enable(sdd->src_clk); |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 777 | } else { |
| 778 | /* Configure Clock */ |
| 779 | val = readl(regs + S3C64XX_SPI_CLK_CFG); |
| 780 | val &= ~S3C64XX_SPI_PSR_MASK; |
| 781 | val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) |
| 782 | & S3C64XX_SPI_PSR_MASK); |
| 783 | writel(val, regs + S3C64XX_SPI_CLK_CFG); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 784 | |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 785 | /* Enable Clock */ |
| 786 | val = readl(regs + S3C64XX_SPI_CLK_CFG); |
| 787 | val |= S3C64XX_SPI_ENCLK_ENABLE; |
| 788 | writel(val, regs + S3C64XX_SPI_CLK_CFG); |
| 789 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 790 | } |
| 791 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 792 | #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32) |
| 793 | |
| 794 | static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd, |
| 795 | struct spi_message *msg) |
| 796 | { |
| 797 | struct device *dev = &sdd->pdev->dev; |
| 798 | struct spi_transfer *xfer; |
| 799 | |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 800 | if (is_polling(sdd) || msg->is_dma_mapped) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 801 | return 0; |
| 802 | |
| 803 | /* First mark all xfer unmapped */ |
| 804 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
| 805 | xfer->rx_dma = XFER_DMAADDR_INVALID; |
| 806 | xfer->tx_dma = XFER_DMAADDR_INVALID; |
| 807 | } |
| 808 | |
| 809 | /* Map until end or first fail */ |
| 810 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
| 811 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 812 | if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1)) |
Jassi Brar | e02ddd4 | 2010-09-29 17:31:31 +0900 | [diff] [blame] | 813 | continue; |
| 814 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 815 | if (xfer->tx_buf != NULL) { |
Jassi Brar | 251ee47 | 2010-09-03 10:36:26 +0900 | [diff] [blame] | 816 | xfer->tx_dma = dma_map_single(dev, |
| 817 | (void *)xfer->tx_buf, xfer->len, |
| 818 | DMA_TO_DEVICE); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 819 | if (dma_mapping_error(dev, xfer->tx_dma)) { |
| 820 | dev_err(dev, "dma_map_single Tx failed\n"); |
| 821 | xfer->tx_dma = XFER_DMAADDR_INVALID; |
| 822 | return -ENOMEM; |
| 823 | } |
| 824 | } |
| 825 | |
| 826 | if (xfer->rx_buf != NULL) { |
| 827 | xfer->rx_dma = dma_map_single(dev, xfer->rx_buf, |
| 828 | xfer->len, DMA_FROM_DEVICE); |
| 829 | if (dma_mapping_error(dev, xfer->rx_dma)) { |
| 830 | dev_err(dev, "dma_map_single Rx failed\n"); |
| 831 | dma_unmap_single(dev, xfer->tx_dma, |
| 832 | xfer->len, DMA_TO_DEVICE); |
| 833 | xfer->tx_dma = XFER_DMAADDR_INVALID; |
| 834 | xfer->rx_dma = XFER_DMAADDR_INVALID; |
| 835 | return -ENOMEM; |
| 836 | } |
| 837 | } |
| 838 | } |
| 839 | |
| 840 | return 0; |
| 841 | } |
| 842 | |
| 843 | static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd, |
| 844 | struct spi_message *msg) |
| 845 | { |
| 846 | struct device *dev = &sdd->pdev->dev; |
| 847 | struct spi_transfer *xfer; |
| 848 | |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 849 | if (is_polling(sdd) || msg->is_dma_mapped) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 850 | return; |
| 851 | |
| 852 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
| 853 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 854 | if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1)) |
Jassi Brar | e02ddd4 | 2010-09-29 17:31:31 +0900 | [diff] [blame] | 855 | continue; |
| 856 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 857 | if (xfer->rx_buf != NULL |
| 858 | && xfer->rx_dma != XFER_DMAADDR_INVALID) |
| 859 | dma_unmap_single(dev, xfer->rx_dma, |
| 860 | xfer->len, DMA_FROM_DEVICE); |
| 861 | |
| 862 | if (xfer->tx_buf != NULL |
| 863 | && xfer->tx_dma != XFER_DMAADDR_INVALID) |
| 864 | dma_unmap_single(dev, xfer->tx_dma, |
| 865 | xfer->len, DMA_TO_DEVICE); |
| 866 | } |
| 867 | } |
| 868 | |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 869 | static int s3c64xx_spi_transfer_one_message(struct spi_master *master, |
| 870 | struct spi_message *msg) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 871 | { |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 872 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 873 | struct spi_device *spi = msg->spi; |
| 874 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; |
| 875 | struct spi_transfer *xfer; |
| 876 | int status = 0, cs_toggle = 0; |
| 877 | u32 speed; |
| 878 | u8 bpw; |
| 879 | |
| 880 | /* If Master's(controller) state differs from that needed by Slave */ |
| 881 | if (sdd->cur_speed != spi->max_speed_hz |
| 882 | || sdd->cur_mode != spi->mode |
| 883 | || sdd->cur_bpw != spi->bits_per_word) { |
| 884 | sdd->cur_bpw = spi->bits_per_word; |
| 885 | sdd->cur_speed = spi->max_speed_hz; |
| 886 | sdd->cur_mode = spi->mode; |
| 887 | s3c64xx_spi_config(sdd); |
| 888 | } |
| 889 | |
| 890 | /* Map all the transfers if needed */ |
| 891 | if (s3c64xx_spi_map_mssg(sdd, msg)) { |
| 892 | dev_err(&spi->dev, |
| 893 | "Xfer: Unable to map message buffers!\n"); |
| 894 | status = -ENOMEM; |
| 895 | goto out; |
| 896 | } |
| 897 | |
| 898 | /* Configure feedback delay */ |
| 899 | writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); |
| 900 | |
| 901 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
| 902 | |
| 903 | unsigned long flags; |
| 904 | int use_dma; |
| 905 | |
| 906 | INIT_COMPLETION(sdd->xfer_completion); |
| 907 | |
| 908 | /* Only BPW and Speed may change across transfers */ |
Laxman Dewangan | 766ed70 | 2012-12-18 14:25:43 +0530 | [diff] [blame] | 909 | bpw = xfer->bits_per_word; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 910 | speed = xfer->speed_hz ? : spi->max_speed_hz; |
| 911 | |
Jassi Brar | 0c92ecf | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 912 | if (xfer->len % (bpw / 8)) { |
| 913 | dev_err(&spi->dev, |
| 914 | "Xfer length(%u) not a multiple of word size(%u)\n", |
| 915 | xfer->len, bpw / 8); |
| 916 | status = -EIO; |
| 917 | goto out; |
| 918 | } |
| 919 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 920 | if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { |
| 921 | sdd->cur_bpw = bpw; |
| 922 | sdd->cur_speed = speed; |
| 923 | s3c64xx_spi_config(sdd); |
| 924 | } |
| 925 | |
| 926 | /* Polling method for xfers not bigger than FIFO capacity */ |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 927 | use_dma = 0; |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 928 | if (!is_polling(sdd) && |
| 929 | (sdd->rx_dma.ch && sdd->tx_dma.ch && |
| 930 | (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1)))) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 931 | use_dma = 1; |
| 932 | |
| 933 | spin_lock_irqsave(&sdd->lock, flags); |
| 934 | |
| 935 | /* Pending only which is to be done */ |
| 936 | sdd->state &= ~RXBUSY; |
| 937 | sdd->state &= ~TXBUSY; |
| 938 | |
| 939 | enable_datapath(sdd, spi, xfer, use_dma); |
| 940 | |
| 941 | /* Slave Select */ |
| 942 | enable_cs(sdd, spi); |
| 943 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 944 | spin_unlock_irqrestore(&sdd->lock, flags); |
| 945 | |
| 946 | status = wait_for_xfer(sdd, xfer, use_dma); |
| 947 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 948 | if (status) { |
Jingoo Han | 75bf336 | 2013-01-31 15:25:01 +0900 | [diff] [blame] | 949 | dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n", |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 950 | xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, |
| 951 | (sdd->state & RXBUSY) ? 'f' : 'p', |
| 952 | (sdd->state & TXBUSY) ? 'f' : 'p', |
| 953 | xfer->len); |
| 954 | |
| 955 | if (use_dma) { |
| 956 | if (xfer->tx_buf != NULL |
| 957 | && (sdd->state & TXBUSY)) |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 958 | s3c64xx_spi_dma_stop(sdd, &sdd->tx_dma); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 959 | if (xfer->rx_buf != NULL |
| 960 | && (sdd->state & RXBUSY)) |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 961 | s3c64xx_spi_dma_stop(sdd, &sdd->rx_dma); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 962 | } |
| 963 | |
| 964 | goto out; |
| 965 | } |
| 966 | |
| 967 | if (xfer->delay_usecs) |
| 968 | udelay(xfer->delay_usecs); |
| 969 | |
| 970 | if (xfer->cs_change) { |
| 971 | /* Hint that the next mssg is gonna be |
| 972 | for the same device */ |
| 973 | if (list_is_last(&xfer->transfer_list, |
| 974 | &msg->transfers)) |
| 975 | cs_toggle = 1; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 976 | } |
| 977 | |
| 978 | msg->actual_length += xfer->len; |
| 979 | |
| 980 | flush_fifo(sdd); |
| 981 | } |
| 982 | |
| 983 | out: |
| 984 | if (!cs_toggle || status) |
| 985 | disable_cs(sdd, spi); |
| 986 | else |
| 987 | sdd->tgl_spi = spi; |
| 988 | |
| 989 | s3c64xx_spi_unmap_mssg(sdd, msg); |
| 990 | |
| 991 | msg->status = status; |
| 992 | |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 993 | spi_finalize_current_message(master); |
| 994 | |
| 995 | return 0; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 996 | } |
| 997 | |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 998 | static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata( |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 999 | struct spi_device *spi) |
| 1000 | { |
| 1001 | struct s3c64xx_spi_csinfo *cs; |
Arnd Bergmann | 4732cc6 | 2012-08-04 11:18:20 +0000 | [diff] [blame] | 1002 | struct device_node *slave_np, *data_np = NULL; |
Girish K S | 3146bee | 2013-06-21 11:26:12 +0530 | [diff] [blame] | 1003 | struct s3c64xx_spi_driver_data *sdd; |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1004 | u32 fb_delay = 0; |
| 1005 | |
Girish K S | 3146bee | 2013-06-21 11:26:12 +0530 | [diff] [blame] | 1006 | sdd = spi_master_get_devdata(spi->master); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1007 | slave_np = spi->dev.of_node; |
| 1008 | if (!slave_np) { |
| 1009 | dev_err(&spi->dev, "device node not found\n"); |
| 1010 | return ERR_PTR(-EINVAL); |
| 1011 | } |
| 1012 | |
Srinivas Kandagatla | 06455bb | 2012-09-18 08:10:49 +0100 | [diff] [blame] | 1013 | data_np = of_get_child_by_name(slave_np, "controller-data"); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1014 | if (!data_np) { |
| 1015 | dev_err(&spi->dev, "child node 'controller-data' not found\n"); |
| 1016 | return ERR_PTR(-EINVAL); |
| 1017 | } |
| 1018 | |
| 1019 | cs = kzalloc(sizeof(*cs), GFP_KERNEL); |
| 1020 | if (!cs) { |
Jingoo Han | 75bf336 | 2013-01-31 15:25:01 +0900 | [diff] [blame] | 1021 | dev_err(&spi->dev, "could not allocate memory for controller data\n"); |
Srinivas Kandagatla | 06455bb | 2012-09-18 08:10:49 +0100 | [diff] [blame] | 1022 | of_node_put(data_np); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1023 | return ERR_PTR(-ENOMEM); |
| 1024 | } |
| 1025 | |
Girish K S | 3146bee | 2013-06-21 11:26:12 +0530 | [diff] [blame] | 1026 | /* The CS line is asserted/deasserted by the gpio pin */ |
| 1027 | if (sdd->cs_gpio) |
| 1028 | cs->line = of_get_named_gpio(data_np, "cs-gpio", 0); |
| 1029 | |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1030 | if (!gpio_is_valid(cs->line)) { |
Jingoo Han | 75bf336 | 2013-01-31 15:25:01 +0900 | [diff] [blame] | 1031 | dev_err(&spi->dev, "chip select gpio is not specified or invalid\n"); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1032 | kfree(cs); |
Srinivas Kandagatla | 06455bb | 2012-09-18 08:10:49 +0100 | [diff] [blame] | 1033 | of_node_put(data_np); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1034 | return ERR_PTR(-EINVAL); |
| 1035 | } |
| 1036 | |
| 1037 | of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay); |
| 1038 | cs->fb_delay = fb_delay; |
Srinivas Kandagatla | 06455bb | 2012-09-18 08:10:49 +0100 | [diff] [blame] | 1039 | of_node_put(data_np); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1040 | return cs; |
| 1041 | } |
| 1042 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1043 | /* |
| 1044 | * Here we only check the validity of requested configuration |
| 1045 | * and save the configuration in a local data-structure. |
| 1046 | * The controller is actually configured only just before we |
| 1047 | * get a message to transfer. |
| 1048 | */ |
| 1049 | static int s3c64xx_spi_setup(struct spi_device *spi) |
| 1050 | { |
| 1051 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; |
| 1052 | struct s3c64xx_spi_driver_data *sdd; |
Jassi Brar | ad7de72 | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1053 | struct s3c64xx_spi_info *sci; |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1054 | int err; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1055 | |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1056 | sdd = spi_master_get_devdata(spi->master); |
| 1057 | if (!cs && spi->dev.of_node) { |
Matthias Brugger | 5c725b3 | 2013-03-26 10:27:35 +0100 | [diff] [blame] | 1058 | cs = s3c64xx_get_slave_ctrldata(spi); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1059 | spi->controller_data = cs; |
| 1060 | } |
| 1061 | |
| 1062 | if (IS_ERR_OR_NULL(cs)) { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1063 | dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); |
| 1064 | return -ENODEV; |
| 1065 | } |
| 1066 | |
Tomasz Figa | 0149871 | 2013-08-11 02:33:29 +0200 | [diff] [blame] | 1067 | if (!spi_get_ctldata(spi)) { |
| 1068 | /* Request gpio only if cs line is asserted by gpio pins */ |
| 1069 | if (sdd->cs_gpio) { |
| 1070 | err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH, |
| 1071 | dev_name(&spi->dev)); |
| 1072 | if (err) { |
| 1073 | dev_err(&spi->dev, |
| 1074 | "Failed to get /CS gpio [%d]: %d\n", |
| 1075 | cs->line, err); |
| 1076 | goto err_gpio_req; |
| 1077 | } |
Thomas Abraham | 1c20c20 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1078 | } |
Thomas Abraham | 1c20c20 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1079 | |
Girish K S | 3146bee | 2013-06-21 11:26:12 +0530 | [diff] [blame] | 1080 | spi_set_ctldata(spi, cs); |
Tomasz Figa | 0149871 | 2013-08-11 02:33:29 +0200 | [diff] [blame] | 1081 | } |
Girish K S | 3146bee | 2013-06-21 11:26:12 +0530 | [diff] [blame] | 1082 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1083 | sci = sdd->cntrlr_info; |
| 1084 | |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1085 | pm_runtime_get_sync(&sdd->pdev->dev); |
| 1086 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1087 | /* Check if we can provide the requested rate */ |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1088 | if (!sdd->port_conf->clk_from_cmu) { |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 1089 | u32 psr, speed; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1090 | |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 1091 | /* Max possible */ |
| 1092 | speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1093 | |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 1094 | if (spi->max_speed_hz > speed) |
| 1095 | spi->max_speed_hz = speed; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1096 | |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 1097 | psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; |
| 1098 | psr &= S3C64XX_SPI_PSR_MASK; |
| 1099 | if (psr == S3C64XX_SPI_PSR_MASK) |
| 1100 | psr--; |
| 1101 | |
| 1102 | speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); |
| 1103 | if (spi->max_speed_hz < speed) { |
| 1104 | if (psr+1 < S3C64XX_SPI_PSR_MASK) { |
| 1105 | psr++; |
| 1106 | } else { |
| 1107 | err = -EINVAL; |
| 1108 | goto setup_exit; |
| 1109 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1110 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1111 | |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 1112 | speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1113 | if (spi->max_speed_hz >= speed) { |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 1114 | spi->max_speed_hz = speed; |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1115 | } else { |
Mark Brown | e1b0f0d | 2012-12-20 18:27:31 +0000 | [diff] [blame] | 1116 | dev_err(&spi->dev, "Can't set %dHz transfer speed\n", |
| 1117 | spi->max_speed_hz); |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 1118 | err = -EINVAL; |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1119 | goto setup_exit; |
| 1120 | } |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 1121 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1122 | |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1123 | pm_runtime_put(&sdd->pdev->dev); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1124 | disable_cs(sdd, spi); |
| 1125 | return 0; |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1126 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1127 | setup_exit: |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1128 | /* setup() returns with device de-selected */ |
| 1129 | disable_cs(sdd, spi); |
| 1130 | |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1131 | gpio_free(cs->line); |
| 1132 | spi_set_ctldata(spi, NULL); |
| 1133 | |
| 1134 | err_gpio_req: |
Sylwester Nawrocki | 5bee3b9 | 2012-09-13 16:31:30 +0200 | [diff] [blame] | 1135 | if (spi->dev.of_node) |
| 1136 | kfree(cs); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1137 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1138 | return err; |
| 1139 | } |
| 1140 | |
Thomas Abraham | 1c20c20 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1141 | static void s3c64xx_spi_cleanup(struct spi_device *spi) |
| 1142 | { |
| 1143 | struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); |
Girish K S | 3146bee | 2013-06-21 11:26:12 +0530 | [diff] [blame] | 1144 | struct s3c64xx_spi_driver_data *sdd; |
Thomas Abraham | 1c20c20 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1145 | |
Girish K S | 3146bee | 2013-06-21 11:26:12 +0530 | [diff] [blame] | 1146 | sdd = spi_master_get_devdata(spi->master); |
| 1147 | if (cs && sdd->cs_gpio) { |
Thomas Abraham | 1c20c20 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1148 | gpio_free(cs->line); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1149 | if (spi->dev.of_node) |
| 1150 | kfree(cs); |
| 1151 | } |
Thomas Abraham | 1c20c20 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1152 | spi_set_ctldata(spi, NULL); |
| 1153 | } |
| 1154 | |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1155 | static irqreturn_t s3c64xx_spi_irq(int irq, void *data) |
| 1156 | { |
| 1157 | struct s3c64xx_spi_driver_data *sdd = data; |
| 1158 | struct spi_master *spi = sdd->master; |
Girish K S | 375981f | 2013-03-13 12:13:30 +0530 | [diff] [blame] | 1159 | unsigned int val, clr = 0; |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1160 | |
Girish K S | 375981f | 2013-03-13 12:13:30 +0530 | [diff] [blame] | 1161 | val = readl(sdd->regs + S3C64XX_SPI_STATUS); |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1162 | |
Girish K S | 375981f | 2013-03-13 12:13:30 +0530 | [diff] [blame] | 1163 | if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) { |
| 1164 | clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR; |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1165 | dev_err(&spi->dev, "RX overrun\n"); |
Girish K S | 375981f | 2013-03-13 12:13:30 +0530 | [diff] [blame] | 1166 | } |
| 1167 | if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) { |
| 1168 | clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR; |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1169 | dev_err(&spi->dev, "RX underrun\n"); |
Girish K S | 375981f | 2013-03-13 12:13:30 +0530 | [diff] [blame] | 1170 | } |
| 1171 | if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) { |
| 1172 | clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR; |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1173 | dev_err(&spi->dev, "TX overrun\n"); |
Girish K S | 375981f | 2013-03-13 12:13:30 +0530 | [diff] [blame] | 1174 | } |
| 1175 | if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) { |
| 1176 | clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR; |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1177 | dev_err(&spi->dev, "TX underrun\n"); |
Girish K S | 375981f | 2013-03-13 12:13:30 +0530 | [diff] [blame] | 1178 | } |
| 1179 | |
| 1180 | /* Clear the pending irq by setting and then clearing it */ |
| 1181 | writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR); |
| 1182 | writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR); |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1183 | |
| 1184 | return IRQ_HANDLED; |
| 1185 | } |
| 1186 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1187 | static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) |
| 1188 | { |
Jassi Brar | ad7de72 | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1189 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1190 | void __iomem *regs = sdd->regs; |
| 1191 | unsigned int val; |
| 1192 | |
| 1193 | sdd->cur_speed = 0; |
| 1194 | |
Mark Brown | 5fc3e83 | 2012-07-19 14:36:23 +0900 | [diff] [blame] | 1195 | writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1196 | |
| 1197 | /* Disable Interrupts - we use Polling if not DMA mode */ |
| 1198 | writel(0, regs + S3C64XX_SPI_INT_EN); |
| 1199 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1200 | if (!sdd->port_conf->clk_from_cmu) |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 1201 | writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1202 | regs + S3C64XX_SPI_CLK_CFG); |
| 1203 | writel(0, regs + S3C64XX_SPI_MODE_CFG); |
| 1204 | writel(0, regs + S3C64XX_SPI_PACKET_CNT); |
| 1205 | |
Girish K S | 375981f | 2013-03-13 12:13:30 +0530 | [diff] [blame] | 1206 | /* Clear any irq pending bits, should set and clear the bits */ |
| 1207 | val = S3C64XX_SPI_PND_RX_OVERRUN_CLR | |
| 1208 | S3C64XX_SPI_PND_RX_UNDERRUN_CLR | |
| 1209 | S3C64XX_SPI_PND_TX_OVERRUN_CLR | |
| 1210 | S3C64XX_SPI_PND_TX_UNDERRUN_CLR; |
| 1211 | writel(val, regs + S3C64XX_SPI_PENDING_CLR); |
| 1212 | writel(0, regs + S3C64XX_SPI_PENDING_CLR); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1213 | |
| 1214 | writel(0, regs + S3C64XX_SPI_SWAP_CFG); |
| 1215 | |
| 1216 | val = readl(regs + S3C64XX_SPI_MODE_CFG); |
| 1217 | val &= ~S3C64XX_SPI_MODE_4BURST; |
| 1218 | val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); |
| 1219 | val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); |
| 1220 | writel(val, regs + S3C64XX_SPI_MODE_CFG); |
| 1221 | |
| 1222 | flush_fifo(sdd); |
| 1223 | } |
| 1224 | |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1225 | #ifdef CONFIG_OF |
Jingoo Han | 75bf336 | 2013-01-31 15:25:01 +0900 | [diff] [blame] | 1226 | static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1227 | { |
| 1228 | struct s3c64xx_spi_info *sci; |
| 1229 | u32 temp; |
| 1230 | |
| 1231 | sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL); |
| 1232 | if (!sci) { |
| 1233 | dev_err(dev, "memory allocation for spi_info failed\n"); |
| 1234 | return ERR_PTR(-ENOMEM); |
| 1235 | } |
| 1236 | |
| 1237 | if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { |
Jingoo Han | 75bf336 | 2013-01-31 15:25:01 +0900 | [diff] [blame] | 1238 | dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n"); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1239 | sci->src_clk_nr = 0; |
| 1240 | } else { |
| 1241 | sci->src_clk_nr = temp; |
| 1242 | } |
| 1243 | |
| 1244 | if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { |
Jingoo Han | 75bf336 | 2013-01-31 15:25:01 +0900 | [diff] [blame] | 1245 | dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n"); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1246 | sci->num_cs = 1; |
| 1247 | } else { |
| 1248 | sci->num_cs = temp; |
| 1249 | } |
| 1250 | |
| 1251 | return sci; |
| 1252 | } |
| 1253 | #else |
| 1254 | static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) |
| 1255 | { |
| 1256 | return dev->platform_data; |
| 1257 | } |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1258 | #endif |
| 1259 | |
| 1260 | static const struct of_device_id s3c64xx_spi_dt_match[]; |
| 1261 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1262 | static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( |
| 1263 | struct platform_device *pdev) |
| 1264 | { |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1265 | #ifdef CONFIG_OF |
| 1266 | if (pdev->dev.of_node) { |
| 1267 | const struct of_device_id *match; |
| 1268 | match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node); |
| 1269 | return (struct s3c64xx_spi_port_config *)match->data; |
| 1270 | } |
| 1271 | #endif |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1272 | return (struct s3c64xx_spi_port_config *) |
| 1273 | platform_get_device_id(pdev)->driver_data; |
| 1274 | } |
| 1275 | |
Grant Likely | 2deff8d | 2013-02-05 13:27:35 +0000 | [diff] [blame] | 1276 | static int s3c64xx_spi_probe(struct platform_device *pdev) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1277 | { |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1278 | struct resource *mem_res; |
Padmavathi Venna | b5be04d | 2013-01-18 17:17:03 +0530 | [diff] [blame] | 1279 | struct resource *res; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1280 | struct s3c64xx_spi_driver_data *sdd; |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1281 | struct s3c64xx_spi_info *sci = pdev->dev.platform_data; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1282 | struct spi_master *master; |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1283 | int ret, irq; |
Padmavathi Venna | a24d850 | 2011-11-02 20:04:19 +0900 | [diff] [blame] | 1284 | char clk_name[16]; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1285 | |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1286 | if (!sci && pdev->dev.of_node) { |
| 1287 | sci = s3c64xx_spi_parse_dt(&pdev->dev); |
| 1288 | if (IS_ERR(sci)) |
| 1289 | return PTR_ERR(sci); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1290 | } |
| 1291 | |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1292 | if (!sci) { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1293 | dev_err(&pdev->dev, "platform_data missing!\n"); |
| 1294 | return -ENODEV; |
| 1295 | } |
| 1296 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1297 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1298 | if (mem_res == NULL) { |
| 1299 | dev_err(&pdev->dev, "Unable to get SPI MEM resource\n"); |
| 1300 | return -ENXIO; |
| 1301 | } |
| 1302 | |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1303 | irq = platform_get_irq(pdev, 0); |
| 1304 | if (irq < 0) { |
| 1305 | dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq); |
| 1306 | return irq; |
| 1307 | } |
| 1308 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1309 | master = spi_alloc_master(&pdev->dev, |
| 1310 | sizeof(struct s3c64xx_spi_driver_data)); |
| 1311 | if (master == NULL) { |
| 1312 | dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); |
| 1313 | return -ENOMEM; |
| 1314 | } |
| 1315 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1316 | platform_set_drvdata(pdev, master); |
| 1317 | |
| 1318 | sdd = spi_master_get_devdata(master); |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1319 | sdd->port_conf = s3c64xx_spi_get_port_config(pdev); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1320 | sdd->master = master; |
| 1321 | sdd->cntrlr_info = sci; |
| 1322 | sdd->pdev = pdev; |
| 1323 | sdd->sfr_start = mem_res->start; |
Girish K S | 3146bee | 2013-06-21 11:26:12 +0530 | [diff] [blame] | 1324 | sdd->cs_gpio = true; |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1325 | if (pdev->dev.of_node) { |
Girish K S | 3146bee | 2013-06-21 11:26:12 +0530 | [diff] [blame] | 1326 | if (!of_find_property(pdev->dev.of_node, "cs-gpio", NULL)) |
| 1327 | sdd->cs_gpio = false; |
| 1328 | |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1329 | ret = of_alias_get_id(pdev->dev.of_node, "spi"); |
| 1330 | if (ret < 0) { |
Jingoo Han | 75bf336 | 2013-01-31 15:25:01 +0900 | [diff] [blame] | 1331 | dev_err(&pdev->dev, "failed to get alias id, errno %d\n", |
| 1332 | ret); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1333 | goto err0; |
| 1334 | } |
| 1335 | sdd->port_id = ret; |
| 1336 | } else { |
| 1337 | sdd->port_id = pdev->id; |
| 1338 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1339 | |
| 1340 | sdd->cur_bpw = 8; |
| 1341 | |
Padmavathi Venna | b5be04d | 2013-01-18 17:17:03 +0530 | [diff] [blame] | 1342 | if (!sdd->pdev->dev.of_node) { |
| 1343 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
| 1344 | if (!res) { |
Jingoo Han | db0606e | 2013-07-15 15:11:57 +0900 | [diff] [blame] | 1345 | dev_warn(&pdev->dev, "Unable to get SPI tx dma resource. Switching to poll mode\n"); |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 1346 | sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL; |
| 1347 | } else |
| 1348 | sdd->tx_dma.dmach = res->start; |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1349 | |
Padmavathi Venna | b5be04d | 2013-01-18 17:17:03 +0530 | [diff] [blame] | 1350 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); |
| 1351 | if (!res) { |
Jingoo Han | db0606e | 2013-07-15 15:11:57 +0900 | [diff] [blame] | 1352 | dev_warn(&pdev->dev, "Unable to get SPI rx dma resource. Switching to poll mode\n"); |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 1353 | sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL; |
| 1354 | } else |
| 1355 | sdd->rx_dma.dmach = res->start; |
Padmavathi Venna | b5be04d | 2013-01-18 17:17:03 +0530 | [diff] [blame] | 1356 | } |
| 1357 | |
| 1358 | sdd->tx_dma.direction = DMA_MEM_TO_DEV; |
| 1359 | sdd->rx_dma.direction = DMA_DEV_TO_MEM; |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1360 | |
| 1361 | master->dev.of_node = pdev->dev.of_node; |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1362 | master->bus_num = sdd->port_id; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1363 | master->setup = s3c64xx_spi_setup; |
Thomas Abraham | 1c20c20 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1364 | master->cleanup = s3c64xx_spi_cleanup; |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 1365 | master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; |
| 1366 | master->transfer_one_message = s3c64xx_spi_transfer_one_message; |
| 1367 | master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1368 | master->num_chipselect = sci->num_cs; |
| 1369 | master->dma_alignment = 8; |
Stephen Warren | 24778be | 2013-05-21 20:36:35 -0600 | [diff] [blame] | 1370 | master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | |
| 1371 | SPI_BPW_MASK(8); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1372 | /* the spi->mode bits understood by this driver: */ |
| 1373 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
| 1374 | |
Thierry Reding | b0ee560 | 2013-01-21 11:09:18 +0100 | [diff] [blame] | 1375 | sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res); |
| 1376 | if (IS_ERR(sdd->regs)) { |
| 1377 | ret = PTR_ERR(sdd->regs); |
Jingoo Han | 4eb7700 | 2013-01-10 11:04:21 +0900 | [diff] [blame] | 1378 | goto err0; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1379 | } |
| 1380 | |
Thomas Abraham | 00ab539 | 2013-04-15 20:42:57 -0700 | [diff] [blame] | 1381 | if (sci->cfg_gpio && sci->cfg_gpio()) { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1382 | dev_err(&pdev->dev, "Unable to config gpio\n"); |
| 1383 | ret = -EBUSY; |
Jingoo Han | 4eb7700 | 2013-01-10 11:04:21 +0900 | [diff] [blame] | 1384 | goto err0; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1385 | } |
| 1386 | |
| 1387 | /* Setup clocks */ |
Jingoo Han | 4eb7700 | 2013-01-10 11:04:21 +0900 | [diff] [blame] | 1388 | sdd->clk = devm_clk_get(&pdev->dev, "spi"); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1389 | if (IS_ERR(sdd->clk)) { |
| 1390 | dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n"); |
| 1391 | ret = PTR_ERR(sdd->clk); |
Thomas Abraham | 00ab539 | 2013-04-15 20:42:57 -0700 | [diff] [blame] | 1392 | goto err0; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1393 | } |
| 1394 | |
Thomas Abraham | 9f667bf | 2012-10-03 08:30:12 +0900 | [diff] [blame] | 1395 | if (clk_prepare_enable(sdd->clk)) { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1396 | dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); |
| 1397 | ret = -EBUSY; |
Thomas Abraham | 00ab539 | 2013-04-15 20:42:57 -0700 | [diff] [blame] | 1398 | goto err0; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1399 | } |
| 1400 | |
Padmavathi Venna | a24d850 | 2011-11-02 20:04:19 +0900 | [diff] [blame] | 1401 | sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); |
Jingoo Han | 4eb7700 | 2013-01-10 11:04:21 +0900 | [diff] [blame] | 1402 | sdd->src_clk = devm_clk_get(&pdev->dev, clk_name); |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1403 | if (IS_ERR(sdd->src_clk)) { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1404 | dev_err(&pdev->dev, |
Padmavathi Venna | a24d850 | 2011-11-02 20:04:19 +0900 | [diff] [blame] | 1405 | "Unable to acquire clock '%s'\n", clk_name); |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1406 | ret = PTR_ERR(sdd->src_clk); |
Jingoo Han | 4eb7700 | 2013-01-10 11:04:21 +0900 | [diff] [blame] | 1407 | goto err2; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1408 | } |
| 1409 | |
Thomas Abraham | 9f667bf | 2012-10-03 08:30:12 +0900 | [diff] [blame] | 1410 | if (clk_prepare_enable(sdd->src_clk)) { |
Padmavathi Venna | a24d850 | 2011-11-02 20:04:19 +0900 | [diff] [blame] | 1411 | dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1412 | ret = -EBUSY; |
Jingoo Han | 4eb7700 | 2013-01-10 11:04:21 +0900 | [diff] [blame] | 1413 | goto err2; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1414 | } |
| 1415 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1416 | /* Setup Deufult Mode */ |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1417 | s3c64xx_spi_hwinit(sdd, sdd->port_id); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1418 | |
| 1419 | spin_lock_init(&sdd->lock); |
| 1420 | init_completion(&sdd->xfer_completion); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1421 | |
Jingoo Han | 4eb7700 | 2013-01-10 11:04:21 +0900 | [diff] [blame] | 1422 | ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0, |
| 1423 | "spi-s3c64xx", sdd); |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1424 | if (ret != 0) { |
| 1425 | dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n", |
| 1426 | irq, ret); |
Jingoo Han | 4eb7700 | 2013-01-10 11:04:21 +0900 | [diff] [blame] | 1427 | goto err3; |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1428 | } |
| 1429 | |
| 1430 | writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | |
| 1431 | S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, |
| 1432 | sdd->regs + S3C64XX_SPI_INT_EN); |
| 1433 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1434 | if (spi_register_master(master)) { |
| 1435 | dev_err(&pdev->dev, "cannot register SPI master\n"); |
| 1436 | ret = -EBUSY; |
Jingoo Han | 4eb7700 | 2013-01-10 11:04:21 +0900 | [diff] [blame] | 1437 | goto err3; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1438 | } |
| 1439 | |
Jingoo Han | 75bf336 | 2013-01-31 15:25:01 +0900 | [diff] [blame] | 1440 | dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n", |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1441 | sdd->port_id, master->num_chipselect); |
Jingoo Han | c65bc4a | 2013-07-16 08:53:33 +0900 | [diff] [blame] | 1442 | dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tDMA=[Rx-%d, Tx-%d]\n", |
| 1443 | mem_res, |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 1444 | sdd->rx_dma.dmach, sdd->tx_dma.dmach); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1445 | |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1446 | pm_runtime_enable(&pdev->dev); |
| 1447 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1448 | return 0; |
| 1449 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1450 | err3: |
Jingoo Han | 4eb7700 | 2013-01-10 11:04:21 +0900 | [diff] [blame] | 1451 | clk_disable_unprepare(sdd->src_clk); |
| 1452 | err2: |
| 1453 | clk_disable_unprepare(sdd->clk); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1454 | err0: |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1455 | spi_master_put(master); |
| 1456 | |
| 1457 | return ret; |
| 1458 | } |
| 1459 | |
| 1460 | static int s3c64xx_spi_remove(struct platform_device *pdev) |
| 1461 | { |
| 1462 | struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); |
| 1463 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1464 | |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1465 | pm_runtime_disable(&pdev->dev); |
| 1466 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1467 | spi_unregister_master(master); |
| 1468 | |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1469 | writel(0, sdd->regs + S3C64XX_SPI_INT_EN); |
| 1470 | |
Thomas Abraham | 9f667bf | 2012-10-03 08:30:12 +0900 | [diff] [blame] | 1471 | clk_disable_unprepare(sdd->src_clk); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1472 | |
Thomas Abraham | 9f667bf | 2012-10-03 08:30:12 +0900 | [diff] [blame] | 1473 | clk_disable_unprepare(sdd->clk); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1474 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1475 | spi_master_put(master); |
| 1476 | |
| 1477 | return 0; |
| 1478 | } |
| 1479 | |
Jingoo Han | 997230d | 2013-03-22 02:09:08 +0000 | [diff] [blame] | 1480 | #ifdef CONFIG_PM_SLEEP |
Mark Brown | e25d0bf | 2011-12-04 00:36:18 +0000 | [diff] [blame] | 1481 | static int s3c64xx_spi_suspend(struct device *dev) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1482 | { |
Guenter Roeck | 9a2a524 | 2012-08-16 20:14:25 -0700 | [diff] [blame] | 1483 | struct spi_master *master = dev_get_drvdata(dev); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1484 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1485 | |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 1486 | spi_master_suspend(master); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1487 | |
| 1488 | /* Disable the clock */ |
Thomas Abraham | 9f667bf | 2012-10-03 08:30:12 +0900 | [diff] [blame] | 1489 | clk_disable_unprepare(sdd->src_clk); |
| 1490 | clk_disable_unprepare(sdd->clk); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1491 | |
| 1492 | sdd->cur_speed = 0; /* Output Clock is stopped */ |
| 1493 | |
| 1494 | return 0; |
| 1495 | } |
| 1496 | |
Mark Brown | e25d0bf | 2011-12-04 00:36:18 +0000 | [diff] [blame] | 1497 | static int s3c64xx_spi_resume(struct device *dev) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1498 | { |
Guenter Roeck | 9a2a524 | 2012-08-16 20:14:25 -0700 | [diff] [blame] | 1499 | struct spi_master *master = dev_get_drvdata(dev); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1500 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
Jassi Brar | ad7de72 | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1501 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1502 | |
Thomas Abraham | 00ab539 | 2013-04-15 20:42:57 -0700 | [diff] [blame] | 1503 | if (sci->cfg_gpio) |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1504 | sci->cfg_gpio(); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1505 | |
| 1506 | /* Enable the clock */ |
Thomas Abraham | 9f667bf | 2012-10-03 08:30:12 +0900 | [diff] [blame] | 1507 | clk_prepare_enable(sdd->src_clk); |
| 1508 | clk_prepare_enable(sdd->clk); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1509 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1510 | s3c64xx_spi_hwinit(sdd, sdd->port_id); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1511 | |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 1512 | spi_master_resume(master); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1513 | |
| 1514 | return 0; |
| 1515 | } |
Jingoo Han | 997230d | 2013-03-22 02:09:08 +0000 | [diff] [blame] | 1516 | #endif /* CONFIG_PM_SLEEP */ |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1517 | |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1518 | #ifdef CONFIG_PM_RUNTIME |
| 1519 | static int s3c64xx_spi_runtime_suspend(struct device *dev) |
| 1520 | { |
Guenter Roeck | 9a2a524 | 2012-08-16 20:14:25 -0700 | [diff] [blame] | 1521 | struct spi_master *master = dev_get_drvdata(dev); |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1522 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
| 1523 | |
Thomas Abraham | 9f667bf | 2012-10-03 08:30:12 +0900 | [diff] [blame] | 1524 | clk_disable_unprepare(sdd->clk); |
| 1525 | clk_disable_unprepare(sdd->src_clk); |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1526 | |
| 1527 | return 0; |
| 1528 | } |
| 1529 | |
| 1530 | static int s3c64xx_spi_runtime_resume(struct device *dev) |
| 1531 | { |
Guenter Roeck | 9a2a524 | 2012-08-16 20:14:25 -0700 | [diff] [blame] | 1532 | struct spi_master *master = dev_get_drvdata(dev); |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1533 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
| 1534 | |
Thomas Abraham | 9f667bf | 2012-10-03 08:30:12 +0900 | [diff] [blame] | 1535 | clk_prepare_enable(sdd->src_clk); |
| 1536 | clk_prepare_enable(sdd->clk); |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1537 | |
| 1538 | return 0; |
| 1539 | } |
| 1540 | #endif /* CONFIG_PM_RUNTIME */ |
| 1541 | |
Mark Brown | e25d0bf | 2011-12-04 00:36:18 +0000 | [diff] [blame] | 1542 | static const struct dev_pm_ops s3c64xx_spi_pm = { |
| 1543 | SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume) |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1544 | SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend, |
| 1545 | s3c64xx_spi_runtime_resume, NULL) |
Mark Brown | e25d0bf | 2011-12-04 00:36:18 +0000 | [diff] [blame] | 1546 | }; |
| 1547 | |
Sachin Kamat | 10ce047 | 2012-08-03 10:08:12 +0530 | [diff] [blame] | 1548 | static struct s3c64xx_spi_port_config s3c2443_spi_port_config = { |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1549 | .fifo_lvl_mask = { 0x7f }, |
| 1550 | .rx_lvl_offset = 13, |
| 1551 | .tx_st_done = 21, |
| 1552 | .high_speed = true, |
| 1553 | }; |
| 1554 | |
Sachin Kamat | 10ce047 | 2012-08-03 10:08:12 +0530 | [diff] [blame] | 1555 | static struct s3c64xx_spi_port_config s3c6410_spi_port_config = { |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1556 | .fifo_lvl_mask = { 0x7f, 0x7F }, |
| 1557 | .rx_lvl_offset = 13, |
| 1558 | .tx_st_done = 21, |
| 1559 | }; |
| 1560 | |
Sachin Kamat | 10ce047 | 2012-08-03 10:08:12 +0530 | [diff] [blame] | 1561 | static struct s3c64xx_spi_port_config s5p64x0_spi_port_config = { |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1562 | .fifo_lvl_mask = { 0x1ff, 0x7F }, |
| 1563 | .rx_lvl_offset = 15, |
| 1564 | .tx_st_done = 25, |
| 1565 | }; |
| 1566 | |
Sachin Kamat | 10ce047 | 2012-08-03 10:08:12 +0530 | [diff] [blame] | 1567 | static struct s3c64xx_spi_port_config s5pc100_spi_port_config = { |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1568 | .fifo_lvl_mask = { 0x7f, 0x7F }, |
| 1569 | .rx_lvl_offset = 13, |
| 1570 | .tx_st_done = 21, |
| 1571 | .high_speed = true, |
| 1572 | }; |
| 1573 | |
Sachin Kamat | 10ce047 | 2012-08-03 10:08:12 +0530 | [diff] [blame] | 1574 | static struct s3c64xx_spi_port_config s5pv210_spi_port_config = { |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1575 | .fifo_lvl_mask = { 0x1ff, 0x7F }, |
| 1576 | .rx_lvl_offset = 15, |
| 1577 | .tx_st_done = 25, |
| 1578 | .high_speed = true, |
| 1579 | }; |
| 1580 | |
Sachin Kamat | 10ce047 | 2012-08-03 10:08:12 +0530 | [diff] [blame] | 1581 | static struct s3c64xx_spi_port_config exynos4_spi_port_config = { |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1582 | .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, |
| 1583 | .rx_lvl_offset = 15, |
| 1584 | .tx_st_done = 25, |
| 1585 | .high_speed = true, |
| 1586 | .clk_from_cmu = true, |
| 1587 | }; |
| 1588 | |
Girish K S | bff8203 | 2013-06-21 11:26:13 +0530 | [diff] [blame] | 1589 | static struct s3c64xx_spi_port_config exynos5440_spi_port_config = { |
| 1590 | .fifo_lvl_mask = { 0x1ff }, |
| 1591 | .rx_lvl_offset = 15, |
| 1592 | .tx_st_done = 25, |
| 1593 | .high_speed = true, |
| 1594 | .clk_from_cmu = true, |
| 1595 | .quirks = S3C64XX_SPI_QUIRK_POLL, |
| 1596 | }; |
| 1597 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1598 | static struct platform_device_id s3c64xx_spi_driver_ids[] = { |
| 1599 | { |
| 1600 | .name = "s3c2443-spi", |
| 1601 | .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config, |
| 1602 | }, { |
| 1603 | .name = "s3c6410-spi", |
| 1604 | .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config, |
| 1605 | }, { |
| 1606 | .name = "s5p64x0-spi", |
| 1607 | .driver_data = (kernel_ulong_t)&s5p64x0_spi_port_config, |
| 1608 | }, { |
| 1609 | .name = "s5pc100-spi", |
| 1610 | .driver_data = (kernel_ulong_t)&s5pc100_spi_port_config, |
| 1611 | }, { |
| 1612 | .name = "s5pv210-spi", |
| 1613 | .driver_data = (kernel_ulong_t)&s5pv210_spi_port_config, |
| 1614 | }, { |
| 1615 | .name = "exynos4210-spi", |
| 1616 | .driver_data = (kernel_ulong_t)&exynos4_spi_port_config, |
| 1617 | }, |
| 1618 | { }, |
| 1619 | }; |
| 1620 | |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1621 | static const struct of_device_id s3c64xx_spi_dt_match[] = { |
| 1622 | { .compatible = "samsung,exynos4210-spi", |
| 1623 | .data = (void *)&exynos4_spi_port_config, |
| 1624 | }, |
Girish K S | bff8203 | 2013-06-21 11:26:13 +0530 | [diff] [blame] | 1625 | { .compatible = "samsung,exynos5440-spi", |
| 1626 | .data = (void *)&exynos5440_spi_port_config, |
| 1627 | }, |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1628 | { }, |
| 1629 | }; |
| 1630 | MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1631 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1632 | static struct platform_driver s3c64xx_spi_driver = { |
| 1633 | .driver = { |
| 1634 | .name = "s3c64xx-spi", |
| 1635 | .owner = THIS_MODULE, |
Mark Brown | e25d0bf | 2011-12-04 00:36:18 +0000 | [diff] [blame] | 1636 | .pm = &s3c64xx_spi_pm, |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1637 | .of_match_table = of_match_ptr(s3c64xx_spi_dt_match), |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1638 | }, |
| 1639 | .remove = s3c64xx_spi_remove, |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1640 | .id_table = s3c64xx_spi_driver_ids, |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1641 | }; |
| 1642 | MODULE_ALIAS("platform:s3c64xx-spi"); |
| 1643 | |
| 1644 | static int __init s3c64xx_spi_init(void) |
| 1645 | { |
| 1646 | return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe); |
| 1647 | } |
Mark Brown | d2a787f | 2010-09-07 11:29:17 +0100 | [diff] [blame] | 1648 | subsys_initcall(s3c64xx_spi_init); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1649 | |
| 1650 | static void __exit s3c64xx_spi_exit(void) |
| 1651 | { |
| 1652 | platform_driver_unregister(&s3c64xx_spi_driver); |
| 1653 | } |
| 1654 | module_exit(s3c64xx_spi_exit); |
| 1655 | |
| 1656 | MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); |
| 1657 | MODULE_DESCRIPTION("S3C64XX SPI Controller Driver"); |
| 1658 | MODULE_LICENSE("GPL"); |