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Feng Tange24c7452009-12-14 14:20:22 -08001/*
Grant Likelyca632f52011-06-06 01:16:30 -06002 * Designware SPI core controller driver (refer pxa2xx_spi.c)
Feng Tange24c7452009-12-14 14:20:22 -08003 *
4 * Copyright (c) 2009, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
Feng Tange24c7452009-12-14 14:20:22 -080014 */
15
16#include <linux/dma-mapping.h>
17#include <linux/interrupt.h>
Paul Gortmakerd7614de2011-07-03 15:44:29 -040018#include <linux/module.h>
Feng Tange24c7452009-12-14 14:20:22 -080019#include <linux/highmem.h>
20#include <linux/delay.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090021#include <linux/slab.h>
Feng Tange24c7452009-12-14 14:20:22 -080022#include <linux/spi/spi.h>
Baruch Siachd9c73bb2014-01-31 12:07:47 +020023#include <linux/gpio.h>
Feng Tange24c7452009-12-14 14:20:22 -080024
Grant Likelyca632f52011-06-06 01:16:30 -060025#include "spi-dw.h"
Grant Likely568a60e2011-02-28 12:47:12 -070026
Feng Tange24c7452009-12-14 14:20:22 -080027#ifdef CONFIG_DEBUG_FS
28#include <linux/debugfs.h>
29#endif
30
Feng Tange24c7452009-12-14 14:20:22 -080031/* Slave spi_dev related */
32struct chip_data {
33 u16 cr0;
34 u8 cs; /* chip select pin */
35 u8 n_bytes; /* current is a 1/2/4 byte op */
36 u8 tmode; /* TR/TO/RO/EEPROM */
37 u8 type; /* SPI/SSP/MicroWire */
38
39 u8 poll_mode; /* 1 means use poll mode */
40
41 u32 dma_width;
42 u32 rx_threshold;
43 u32 tx_threshold;
44 u8 enable_dma;
45 u8 bits_per_word;
46 u16 clk_div; /* baud rate divider */
47 u32 speed_hz; /* baud rate */
Feng Tange24c7452009-12-14 14:20:22 -080048 void (*cs_control)(u32 command);
49};
50
51#ifdef CONFIG_DEBUG_FS
Feng Tange24c7452009-12-14 14:20:22 -080052#define SPI_REGS_BUFSIZE 1024
Andy Shevchenko53288fe2014-09-12 15:11:56 +030053static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
54 size_t count, loff_t *ppos)
Feng Tange24c7452009-12-14 14:20:22 -080055{
Andy Shevchenko53288fe2014-09-12 15:11:56 +030056 struct dw_spi *dws = file->private_data;
Feng Tange24c7452009-12-14 14:20:22 -080057 char *buf;
58 u32 len = 0;
59 ssize_t ret;
60
Feng Tange24c7452009-12-14 14:20:22 -080061 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
62 if (!buf)
63 return 0;
64
65 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
Andy Shevchenko53288fe2014-09-12 15:11:56 +030066 "%s registers:\n", dev_name(&dws->master->dev));
Feng Tange24c7452009-12-14 14:20:22 -080067 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
68 "=================================\n");
69 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070070 "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
Feng Tange24c7452009-12-14 14:20:22 -080071 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070072 "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
Feng Tange24c7452009-12-14 14:20:22 -080073 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070074 "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
Feng Tange24c7452009-12-14 14:20:22 -080075 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070076 "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
Feng Tange24c7452009-12-14 14:20:22 -080077 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070078 "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
Feng Tange24c7452009-12-14 14:20:22 -080079 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070080 "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
Feng Tange24c7452009-12-14 14:20:22 -080081 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070082 "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
Feng Tange24c7452009-12-14 14:20:22 -080083 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070084 "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
Feng Tange24c7452009-12-14 14:20:22 -080085 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070086 "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
Feng Tange24c7452009-12-14 14:20:22 -080087 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070088 "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
Feng Tange24c7452009-12-14 14:20:22 -080089 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070090 "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
Feng Tange24c7452009-12-14 14:20:22 -080091 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070092 "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
Feng Tange24c7452009-12-14 14:20:22 -080093 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070094 "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
Feng Tange24c7452009-12-14 14:20:22 -080095 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070096 "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
Feng Tange24c7452009-12-14 14:20:22 -080097 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070098 "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
Feng Tange24c7452009-12-14 14:20:22 -080099 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
100 "=================================\n");
101
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300102 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
Feng Tange24c7452009-12-14 14:20:22 -0800103 kfree(buf);
104 return ret;
105}
106
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300107static const struct file_operations dw_spi_regs_ops = {
Feng Tange24c7452009-12-14 14:20:22 -0800108 .owner = THIS_MODULE,
Stephen Boyd234e3402012-04-05 14:25:11 -0700109 .open = simple_open,
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300110 .read = dw_spi_show_regs,
Arnd Bergmann6038f372010-08-15 18:52:59 +0200111 .llseek = default_llseek,
Feng Tange24c7452009-12-14 14:20:22 -0800112};
113
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300114static int dw_spi_debugfs_init(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800115{
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300116 dws->debugfs = debugfs_create_dir("dw_spi", NULL);
Feng Tange24c7452009-12-14 14:20:22 -0800117 if (!dws->debugfs)
118 return -ENOMEM;
119
120 debugfs_create_file("registers", S_IFREG | S_IRUGO,
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300121 dws->debugfs, (void *)dws, &dw_spi_regs_ops);
Feng Tange24c7452009-12-14 14:20:22 -0800122 return 0;
123}
124
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300125static void dw_spi_debugfs_remove(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800126{
Jingoo Hanfadcace2014-09-02 11:49:24 +0900127 debugfs_remove_recursive(dws->debugfs);
Feng Tange24c7452009-12-14 14:20:22 -0800128}
129
130#else
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300131static inline int dw_spi_debugfs_init(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800132{
George Shore20a588f2010-01-21 11:40:49 +0000133 return 0;
Feng Tange24c7452009-12-14 14:20:22 -0800134}
135
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300136static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800137{
138}
139#endif /* CONFIG_DEBUG_FS */
140
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200141static void dw_spi_set_cs(struct spi_device *spi, bool enable)
142{
143 struct dw_spi *dws = spi_master_get_devdata(spi->master);
144 struct chip_data *chip = spi_get_ctldata(spi);
145
146 /* Chip select logic is inverted from spi_set_cs() */
147 if (chip->cs_control)
148 chip->cs_control(!enable);
149
150 if (!enable)
151 dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
152}
153
Alek Du2ff271b2011-03-30 23:09:54 +0800154/* Return the max entries we can fill into tx fifo */
155static inline u32 tx_max(struct dw_spi *dws)
156{
157 u32 tx_left, tx_room, rxtx_gap;
158
159 tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700160 tx_room = dws->fifo_len - dw_readw(dws, DW_SPI_TXFLR);
Alek Du2ff271b2011-03-30 23:09:54 +0800161
162 /*
163 * Another concern is about the tx/rx mismatch, we
164 * though to use (dws->fifo_len - rxflr - txflr) as
165 * one maximum value for tx, but it doesn't cover the
166 * data which is out of tx/rx fifo and inside the
167 * shift registers. So a control from sw point of
168 * view is taken.
169 */
170 rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
171 / dws->n_bytes;
172
173 return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
174}
175
176/* Return the max entries we should read out of rx fifo */
177static inline u32 rx_max(struct dw_spi *dws)
178{
179 u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
180
Jingoo Hanfadcace2014-09-02 11:49:24 +0900181 return min_t(u32, rx_left, dw_readw(dws, DW_SPI_RXFLR));
Alek Du2ff271b2011-03-30 23:09:54 +0800182}
183
Alek Du3b8a4dd2011-03-30 23:09:55 +0800184static void dw_writer(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800185{
Alek Du2ff271b2011-03-30 23:09:54 +0800186 u32 max = tx_max(dws);
Feng Tangde6efe02011-03-30 23:09:52 +0800187 u16 txw = 0;
Feng Tange24c7452009-12-14 14:20:22 -0800188
Alek Du2ff271b2011-03-30 23:09:54 +0800189 while (max--) {
190 /* Set the tx word if the transfer's original "tx" is not null */
191 if (dws->tx_end - dws->len) {
192 if (dws->n_bytes == 1)
193 txw = *(u8 *)(dws->tx);
194 else
195 txw = *(u16 *)(dws->tx);
196 }
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700197 dw_writew(dws, DW_SPI_DR, txw);
Alek Du2ff271b2011-03-30 23:09:54 +0800198 dws->tx += dws->n_bytes;
Feng Tange24c7452009-12-14 14:20:22 -0800199 }
Feng Tange24c7452009-12-14 14:20:22 -0800200}
201
Alek Du3b8a4dd2011-03-30 23:09:55 +0800202static void dw_reader(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800203{
Alek Du2ff271b2011-03-30 23:09:54 +0800204 u32 max = rx_max(dws);
Feng Tangde6efe02011-03-30 23:09:52 +0800205 u16 rxw;
Feng Tange24c7452009-12-14 14:20:22 -0800206
Alek Du2ff271b2011-03-30 23:09:54 +0800207 while (max--) {
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700208 rxw = dw_readw(dws, DW_SPI_DR);
Feng Tangde6efe02011-03-30 23:09:52 +0800209 /* Care rx only if the transfer's original "rx" is not null */
210 if (dws->rx_end - dws->len) {
211 if (dws->n_bytes == 1)
212 *(u8 *)(dws->rx) = rxw;
213 else
214 *(u16 *)(dws->rx) = rxw;
215 }
216 dws->rx += dws->n_bytes;
Feng Tange24c7452009-12-14 14:20:22 -0800217 }
Feng Tange24c7452009-12-14 14:20:22 -0800218}
219
Feng Tange24c7452009-12-14 14:20:22 -0800220/*
221 * Note: first step is the protocol driver prepares
222 * a dma-capable memory, and this func just need translate
223 * the virt addr to physical
224 */
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200225static int map_dma_buffers(struct spi_master *master,
226 struct spi_device *spi, struct spi_transfer *transfer)
Feng Tange24c7452009-12-14 14:20:22 -0800227{
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200228 struct dw_spi *dws = spi_master_get_devdata(master);
229 struct chip_data *chip = spi_get_ctldata(spi);
230
231 if (!master->cur_msg->is_dma_mapped
Feng Tang7063c0d2010-12-24 13:59:11 +0800232 || !dws->dma_inited
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200233 || !chip->enable_dma
Feng Tang7063c0d2010-12-24 13:59:11 +0800234 || !dws->dma_ops)
Feng Tange24c7452009-12-14 14:20:22 -0800235 return 0;
236
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200237 if (transfer->tx_dma)
238 dws->tx_dma = transfer->tx_dma;
Feng Tange24c7452009-12-14 14:20:22 -0800239
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200240 if (transfer->rx_dma)
241 dws->rx_dma = transfer->rx_dma;
Feng Tange24c7452009-12-14 14:20:22 -0800242
243 return 1;
244}
245
Feng Tange24c7452009-12-14 14:20:22 -0800246static void int_error_stop(struct dw_spi *dws, const char *msg)
247{
Andy Shevchenko45746e82015-03-02 14:58:55 +0200248 spi_reset_chip(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800249
250 dev_err(&dws->master->dev, "%s\n", msg);
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200251 dws->master->cur_msg->status = -EIO;
252 spi_finalize_current_transfer(dws->master);
Feng Tange24c7452009-12-14 14:20:22 -0800253}
254
Feng Tange24c7452009-12-14 14:20:22 -0800255static irqreturn_t interrupt_transfer(struct dw_spi *dws)
256{
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700257 u16 irq_status = dw_readw(dws, DW_SPI_ISR);
Feng Tange24c7452009-12-14 14:20:22 -0800258
Feng Tange24c7452009-12-14 14:20:22 -0800259 /* Error handling */
260 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700261 dw_readw(dws, DW_SPI_TXOICR);
262 dw_readw(dws, DW_SPI_RXOICR);
263 dw_readw(dws, DW_SPI_RXUICR);
Alek Du3b8a4dd2011-03-30 23:09:55 +0800264 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
Feng Tange24c7452009-12-14 14:20:22 -0800265 return IRQ_HANDLED;
266 }
267
Alek Du3b8a4dd2011-03-30 23:09:55 +0800268 dw_reader(dws);
269 if (dws->rx_end == dws->rx) {
270 spi_mask_intr(dws, SPI_INT_TXEI);
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200271 spi_finalize_current_transfer(dws->master);
Alek Du3b8a4dd2011-03-30 23:09:55 +0800272 return IRQ_HANDLED;
273 }
Feng Tang552e4502010-01-20 13:49:45 -0700274 if (irq_status & SPI_INT_TXEI) {
275 spi_mask_intr(dws, SPI_INT_TXEI);
Alek Du3b8a4dd2011-03-30 23:09:55 +0800276 dw_writer(dws);
277 /* Enable TX irq always, it will be disabled when RX finished */
278 spi_umask_intr(dws, SPI_INT_TXEI);
Feng Tange24c7452009-12-14 14:20:22 -0800279 }
Feng Tang552e4502010-01-20 13:49:45 -0700280
Feng Tange24c7452009-12-14 14:20:22 -0800281 return IRQ_HANDLED;
282}
283
284static irqreturn_t dw_spi_irq(int irq, void *dev_id)
285{
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200286 struct spi_master *master = dev_id;
287 struct dw_spi *dws = spi_master_get_devdata(master);
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700288 u16 irq_status = dw_readw(dws, DW_SPI_ISR) & 0x3f;
Yong Wangcbcc0622010-09-07 15:27:27 +0800289
Yong Wangcbcc0622010-09-07 15:27:27 +0800290 if (!irq_status)
291 return IRQ_NONE;
Feng Tange24c7452009-12-14 14:20:22 -0800292
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200293 if (!master->cur_msg) {
Feng Tange24c7452009-12-14 14:20:22 -0800294 spi_mask_intr(dws, SPI_INT_TXEI);
Feng Tange24c7452009-12-14 14:20:22 -0800295 return IRQ_HANDLED;
296 }
297
298 return dws->transfer_handler(dws);
299}
300
301/* Must be called inside pump_transfers() */
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200302static int poll_transfer(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800303{
Alek Du2ff271b2011-03-30 23:09:54 +0800304 do {
305 dw_writer(dws);
Feng Tangde6efe02011-03-30 23:09:52 +0800306 dw_reader(dws);
Alek Du2ff271b2011-03-30 23:09:54 +0800307 cpu_relax();
308 } while (dws->rx_end > dws->rx);
Feng Tange24c7452009-12-14 14:20:22 -0800309
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200310 return 0;
Feng Tange24c7452009-12-14 14:20:22 -0800311}
312
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200313static int dw_spi_transfer_one(struct spi_master *master,
314 struct spi_device *spi, struct spi_transfer *transfer)
Feng Tange24c7452009-12-14 14:20:22 -0800315{
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200316 struct dw_spi *dws = spi_master_get_devdata(master);
317 struct chip_data *chip = spi_get_ctldata(spi);
Feng Tange24c7452009-12-14 14:20:22 -0800318 u8 bits = 0;
319 u8 imask = 0;
320 u8 cs_change = 0;
Andy Shevchenkoea113702015-02-24 13:32:11 +0200321 u16 txlevel = 0;
Feng Tange24c7452009-12-14 14:20:22 -0800322 u16 clk_div = 0;
323 u32 speed = 0;
324 u32 cr0 = 0;
325
Feng Tange24c7452009-12-14 14:20:22 -0800326 dws->n_bytes = chip->n_bytes;
327 dws->dma_width = chip->dma_width;
Feng Tange24c7452009-12-14 14:20:22 -0800328
329 dws->rx_dma = transfer->rx_dma;
330 dws->tx_dma = transfer->tx_dma;
331 dws->tx = (void *)transfer->tx_buf;
332 dws->tx_end = dws->tx + transfer->len;
333 dws->rx = transfer->rx_buf;
334 dws->rx_end = dws->rx + transfer->len;
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200335 dws->len = transfer->len;
Feng Tange24c7452009-12-14 14:20:22 -0800336 if (chip != dws->prev_chip)
337 cs_change = 1;
338
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200339 spi_enable_chip(dws, 0);
340
Feng Tange24c7452009-12-14 14:20:22 -0800341 cr0 = chip->cr0;
342
343 /* Handle per transfer options for bpw and speed */
344 if (transfer->speed_hz) {
345 speed = chip->speed_hz;
346
Andy Shevchenko341c7dc2015-02-24 13:32:12 +0200347 if ((transfer->speed_hz != speed) || !chip->clk_div) {
Feng Tange24c7452009-12-14 14:20:22 -0800348 speed = transfer->speed_hz;
Feng Tange24c7452009-12-14 14:20:22 -0800349
350 /* clk_div doesn't support odd number */
Andy Shevchenko341c7dc2015-02-24 13:32:12 +0200351 clk_div = (dws->max_freq / speed + 1) & 0xfffe;
Feng Tange24c7452009-12-14 14:20:22 -0800352
353 chip->speed_hz = speed;
354 chip->clk_div = clk_div;
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200355
356 spi_set_clk(dws, chip->clk_div);
Feng Tange24c7452009-12-14 14:20:22 -0800357 }
358 }
359 if (transfer->bits_per_word) {
360 bits = transfer->bits_per_word;
Stephen Warren24778be2013-05-21 20:36:35 -0600361 dws->n_bytes = dws->dma_width = bits >> 3;
Feng Tange24c7452009-12-14 14:20:22 -0800362 cr0 = (bits - 1)
363 | (chip->type << SPI_FRF_OFFSET)
364 | (spi->mode << SPI_MODE_OFFSET)
365 | (chip->tmode << SPI_TMOD_OFFSET);
366 }
Feng Tange24c7452009-12-14 14:20:22 -0800367
George Shore052dc7c2010-01-21 11:40:52 +0000368 /*
369 * Adjust transfer mode if necessary. Requires platform dependent
370 * chipselect mechanism.
371 */
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200372 if (chip->cs_control) {
George Shore052dc7c2010-01-21 11:40:52 +0000373 if (dws->rx && dws->tx)
Feng Tange3e55ff2010-09-07 15:52:06 +0800374 chip->tmode = SPI_TMOD_TR;
George Shore052dc7c2010-01-21 11:40:52 +0000375 else if (dws->rx)
Feng Tange3e55ff2010-09-07 15:52:06 +0800376 chip->tmode = SPI_TMOD_RO;
George Shore052dc7c2010-01-21 11:40:52 +0000377 else
Feng Tange3e55ff2010-09-07 15:52:06 +0800378 chip->tmode = SPI_TMOD_TO;
George Shore052dc7c2010-01-21 11:40:52 +0000379
Feng Tange3e55ff2010-09-07 15:52:06 +0800380 cr0 &= ~SPI_TMOD_MASK;
George Shore052dc7c2010-01-21 11:40:52 +0000381 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
382 }
383
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200384 dw_writew(dws, DW_SPI_CTRL0, cr0);
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200385
Feng Tange24c7452009-12-14 14:20:22 -0800386 /* Check if current transfer is a DMA transaction */
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200387 dws->dma_mapped = map_dma_buffers(master, spi, transfer);
Feng Tange24c7452009-12-14 14:20:22 -0800388
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200389 /* For poll mode just disable all interrupts */
390 spi_mask_intr(dws, 0xff);
391
Feng Tang552e4502010-01-20 13:49:45 -0700392 /*
393 * Interrupt mode
394 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
395 */
Feng Tange24c7452009-12-14 14:20:22 -0800396 if (!dws->dma_mapped && !chip->poll_mode) {
Andy Shevchenkoea113702015-02-24 13:32:11 +0200397 txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200398 dw_writew(dws, DW_SPI_TXFLTR, txlevel);
Feng Tang552e4502010-01-20 13:49:45 -0700399
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200400 /* Set the interrupt mask */
Jingoo Hanfadcace2014-09-02 11:49:24 +0900401 imask |= SPI_INT_TXEI | SPI_INT_TXOI |
402 SPI_INT_RXUI | SPI_INT_RXOI;
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200403 spi_umask_intr(dws, imask);
404
Feng Tange24c7452009-12-14 14:20:22 -0800405 dws->transfer_handler = interrupt_transfer;
406 }
407
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200408 spi_enable_chip(dws, 1);
Feng Tange24c7452009-12-14 14:20:22 -0800409
Andy Shevchenko39bc03b2015-02-24 13:32:10 +0200410 if (cs_change)
411 dws->prev_chip = chip;
412
Feng Tange24c7452009-12-14 14:20:22 -0800413 if (dws->dma_mapped)
Feng Tang7063c0d2010-12-24 13:59:11 +0800414 dws->dma_ops->dma_transfer(dws, cs_change);
Feng Tange24c7452009-12-14 14:20:22 -0800415
416 if (chip->poll_mode)
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200417 return poll_transfer(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800418
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200419 return 1;
Feng Tange24c7452009-12-14 14:20:22 -0800420}
421
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200422static void dw_spi_handle_err(struct spi_master *master,
Baruch Siachec37e8e2014-01-31 12:07:44 +0200423 struct spi_message *msg)
Feng Tange24c7452009-12-14 14:20:22 -0800424{
Baruch Siachec37e8e2014-01-31 12:07:44 +0200425 struct dw_spi *dws = spi_master_get_devdata(master);
Feng Tange24c7452009-12-14 14:20:22 -0800426
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200427 spi_reset_chip(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800428}
429
430/* This may be called twice for each spi dev */
431static int dw_spi_setup(struct spi_device *spi)
432{
433 struct dw_spi_chip *chip_info = NULL;
434 struct chip_data *chip;
Baruch Siachd9c73bb2014-01-31 12:07:47 +0200435 int ret;
Feng Tange24c7452009-12-14 14:20:22 -0800436
Feng Tange24c7452009-12-14 14:20:22 -0800437 /* Only alloc on first setup */
438 chip = spi_get_ctldata(spi);
439 if (!chip) {
Axel Lina97c8832014-08-31 12:47:06 +0800440 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
Feng Tange24c7452009-12-14 14:20:22 -0800441 if (!chip)
442 return -ENOMEM;
Baruch Siach43f627a2013-12-30 20:30:46 +0200443 spi_set_ctldata(spi, chip);
Feng Tange24c7452009-12-14 14:20:22 -0800444 }
445
446 /*
447 * Protocol drivers may change the chip settings, so...
448 * if chip_info exists, use it
449 */
450 chip_info = spi->controller_data;
451
452 /* chip_info doesn't always exist */
453 if (chip_info) {
454 if (chip_info->cs_control)
455 chip->cs_control = chip_info->cs_control;
456
457 chip->poll_mode = chip_info->poll_mode;
458 chip->type = chip_info->type;
459
460 chip->rx_threshold = 0;
461 chip->tx_threshold = 0;
462
463 chip->enable_dma = chip_info->enable_dma;
464 }
465
Stephen Warren24778be2013-05-21 20:36:35 -0600466 if (spi->bits_per_word == 8) {
Feng Tange24c7452009-12-14 14:20:22 -0800467 chip->n_bytes = 1;
468 chip->dma_width = 1;
Stephen Warren24778be2013-05-21 20:36:35 -0600469 } else if (spi->bits_per_word == 16) {
Feng Tange24c7452009-12-14 14:20:22 -0800470 chip->n_bytes = 2;
471 chip->dma_width = 2;
Feng Tange24c7452009-12-14 14:20:22 -0800472 }
473 chip->bits_per_word = spi->bits_per_word;
474
Feng Tang552e4502010-01-20 13:49:45 -0700475 if (!spi->max_speed_hz) {
476 dev_err(&spi->dev, "No max speed HZ parameter\n");
477 return -EINVAL;
478 }
Feng Tange24c7452009-12-14 14:20:22 -0800479
480 chip->tmode = 0; /* Tx & Rx */
481 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
482 chip->cr0 = (chip->bits_per_word - 1)
483 | (chip->type << SPI_FRF_OFFSET)
484 | (spi->mode << SPI_MODE_OFFSET)
485 | (chip->tmode << SPI_TMOD_OFFSET);
486
Andy Shevchenkoc3ce15b2014-09-18 20:08:56 +0300487 if (spi->mode & SPI_LOOP)
488 chip->cr0 |= 1 << SPI_SRL_OFFSET;
489
Baruch Siachd9c73bb2014-01-31 12:07:47 +0200490 if (gpio_is_valid(spi->cs_gpio)) {
491 ret = gpio_direction_output(spi->cs_gpio,
492 !(spi->mode & SPI_CS_HIGH));
493 if (ret)
494 return ret;
495 }
496
Feng Tange24c7452009-12-14 14:20:22 -0800497 return 0;
498}
499
Axel Lina97c8832014-08-31 12:47:06 +0800500static void dw_spi_cleanup(struct spi_device *spi)
501{
502 struct chip_data *chip = spi_get_ctldata(spi);
503
504 kfree(chip);
505 spi_set_ctldata(spi, NULL);
506}
507
Feng Tange24c7452009-12-14 14:20:22 -0800508/* Restart the controller, disable all interrupts, clean rx fifo */
Andy Shevchenko30b4b702015-01-07 16:56:55 +0200509static void spi_hw_init(struct device *dev, struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800510{
Andy Shevchenko45746e82015-03-02 14:58:55 +0200511 spi_reset_chip(dws);
Feng Tangc587b6f2010-01-21 10:41:10 +0800512
513 /*
514 * Try to detect the FIFO depth if not set by interface driver,
515 * the depth could be from 2 to 256 from HW spec
516 */
517 if (!dws->fifo_len) {
518 u32 fifo;
Jingoo Hanfadcace2014-09-02 11:49:24 +0900519
Axel Lind2979332015-01-05 09:32:56 +0800520 for (fifo = 2; fifo <= 256; fifo++) {
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700521 dw_writew(dws, DW_SPI_TXFLTR, fifo);
522 if (fifo != dw_readw(dws, DW_SPI_TXFLTR))
Feng Tangc587b6f2010-01-21 10:41:10 +0800523 break;
524 }
Andy Shevchenko30b4b702015-01-07 16:56:55 +0200525 dw_writew(dws, DW_SPI_TXFLTR, 0);
Feng Tangc587b6f2010-01-21 10:41:10 +0800526
Axel Lind2979332015-01-05 09:32:56 +0800527 dws->fifo_len = (fifo == 2) ? 0 : fifo - 1;
Andy Shevchenko30b4b702015-01-07 16:56:55 +0200528 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
Feng Tangc587b6f2010-01-21 10:41:10 +0800529 }
Feng Tange24c7452009-12-14 14:20:22 -0800530}
531
Baruch Siach04f421e2013-12-30 20:30:44 +0200532int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800533{
534 struct spi_master *master;
535 int ret;
536
537 BUG_ON(dws == NULL);
538
Baruch Siach04f421e2013-12-30 20:30:44 +0200539 master = spi_alloc_master(dev, 0);
540 if (!master)
541 return -ENOMEM;
Feng Tange24c7452009-12-14 14:20:22 -0800542
543 dws->master = master;
544 dws->type = SSI_MOTO_SPI;
545 dws->prev_chip = NULL;
546 dws->dma_inited = 0;
547 dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
Andy Shevchenkoc3c6e232014-09-18 20:08:57 +0300548 snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num);
Feng Tange24c7452009-12-14 14:20:22 -0800549
Baruch Siach04f421e2013-12-30 20:30:44 +0200550 ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED,
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200551 dws->name, master);
Feng Tange24c7452009-12-14 14:20:22 -0800552 if (ret < 0) {
553 dev_err(&master->dev, "can not get IRQ\n");
554 goto err_free_master;
555 }
556
Andy Shevchenkoc3ce15b2014-09-18 20:08:56 +0300557 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
Stephen Warren24778be2013-05-21 20:36:35 -0600558 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
Feng Tange24c7452009-12-14 14:20:22 -0800559 master->bus_num = dws->bus_num;
560 master->num_chipselect = dws->num_cs;
Feng Tange24c7452009-12-14 14:20:22 -0800561 master->setup = dw_spi_setup;
Axel Lina97c8832014-08-31 12:47:06 +0800562 master->cleanup = dw_spi_cleanup;
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200563 master->set_cs = dw_spi_set_cs;
564 master->transfer_one = dw_spi_transfer_one;
565 master->handle_err = dw_spi_handle_err;
Axel Lin765ee702014-02-20 21:37:56 +0800566 master->max_speed_hz = dws->max_freq;
Thor Thayer9c6de472014-10-08 13:51:34 -0500567 master->dev.of_node = dev->of_node;
Feng Tange24c7452009-12-14 14:20:22 -0800568
Feng Tange24c7452009-12-14 14:20:22 -0800569 /* Basic HW init */
Andy Shevchenko30b4b702015-01-07 16:56:55 +0200570 spi_hw_init(dev, dws);
Feng Tange24c7452009-12-14 14:20:22 -0800571
Feng Tang7063c0d2010-12-24 13:59:11 +0800572 if (dws->dma_ops && dws->dma_ops->dma_init) {
573 ret = dws->dma_ops->dma_init(dws);
574 if (ret) {
Andy Shevchenko3dbb3b92015-01-07 16:56:54 +0200575 dev_warn(dev, "DMA init failed\n");
Feng Tang7063c0d2010-12-24 13:59:11 +0800576 dws->dma_inited = 0;
577 }
578 }
579
Feng Tange24c7452009-12-14 14:20:22 -0800580 spi_master_set_devdata(master, dws);
Baruch Siach04f421e2013-12-30 20:30:44 +0200581 ret = devm_spi_register_master(dev, master);
Feng Tange24c7452009-12-14 14:20:22 -0800582 if (ret) {
583 dev_err(&master->dev, "problem registering spi master\n");
Baruch Siachec37e8e2014-01-31 12:07:44 +0200584 goto err_dma_exit;
Feng Tange24c7452009-12-14 14:20:22 -0800585 }
586
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300587 dw_spi_debugfs_init(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800588 return 0;
589
Baruch Siachec37e8e2014-01-31 12:07:44 +0200590err_dma_exit:
Feng Tang7063c0d2010-12-24 13:59:11 +0800591 if (dws->dma_ops && dws->dma_ops->dma_exit)
592 dws->dma_ops->dma_exit(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800593 spi_enable_chip(dws, 0);
Feng Tange24c7452009-12-14 14:20:22 -0800594err_free_master:
595 spi_master_put(master);
Feng Tange24c7452009-12-14 14:20:22 -0800596 return ret;
597}
Feng Tang79290a22010-12-24 13:59:10 +0800598EXPORT_SYMBOL_GPL(dw_spi_add_host);
Feng Tange24c7452009-12-14 14:20:22 -0800599
Grant Likelyfd4a3192012-12-07 16:57:14 +0000600void dw_spi_remove_host(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800601{
Feng Tange24c7452009-12-14 14:20:22 -0800602 if (!dws)
603 return;
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300604 dw_spi_debugfs_remove(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800605
Feng Tang7063c0d2010-12-24 13:59:11 +0800606 if (dws->dma_ops && dws->dma_ops->dma_exit)
607 dws->dma_ops->dma_exit(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800608 spi_enable_chip(dws, 0);
609 /* Disable clk */
610 spi_set_clk(dws, 0);
Feng Tange24c7452009-12-14 14:20:22 -0800611}
Feng Tang79290a22010-12-24 13:59:10 +0800612EXPORT_SYMBOL_GPL(dw_spi_remove_host);
Feng Tange24c7452009-12-14 14:20:22 -0800613
614int dw_spi_suspend_host(struct dw_spi *dws)
615{
616 int ret = 0;
617
Baruch Siachec37e8e2014-01-31 12:07:44 +0200618 ret = spi_master_suspend(dws->master);
Feng Tange24c7452009-12-14 14:20:22 -0800619 if (ret)
620 return ret;
621 spi_enable_chip(dws, 0);
622 spi_set_clk(dws, 0);
623 return ret;
624}
Feng Tang79290a22010-12-24 13:59:10 +0800625EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
Feng Tange24c7452009-12-14 14:20:22 -0800626
627int dw_spi_resume_host(struct dw_spi *dws)
628{
629 int ret;
630
Andy Shevchenko30b4b702015-01-07 16:56:55 +0200631 spi_hw_init(&dws->master->dev, dws);
Baruch Siachec37e8e2014-01-31 12:07:44 +0200632 ret = spi_master_resume(dws->master);
Feng Tange24c7452009-12-14 14:20:22 -0800633 if (ret)
634 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
635 return ret;
636}
Feng Tang79290a22010-12-24 13:59:10 +0800637EXPORT_SYMBOL_GPL(dw_spi_resume_host);
Feng Tange24c7452009-12-14 14:20:22 -0800638
639MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
640MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
641MODULE_LICENSE("GPL v2");