Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel. |
| 3 | * |
| 4 | * David A Rusling |
| 5 | * |
| 6 | * Copyright (C) 2001 ARM Limited |
| 7 | * |
| 8 | * This file is subject to the terms and conditions of the GNU General Public |
| 9 | * License. See the file COPYING in the main directory of this archive |
| 10 | * for more details. |
| 11 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12 | #include <linux/fb.h> |
| 13 | |
| 14 | /* |
| 15 | * CLCD Controller Internal Register addresses |
| 16 | */ |
| 17 | #define CLCD_TIM0 0x00000000 |
| 18 | #define CLCD_TIM1 0x00000004 |
| 19 | #define CLCD_TIM2 0x00000008 |
| 20 | #define CLCD_TIM3 0x0000000c |
| 21 | #define CLCD_UBAS 0x00000010 |
| 22 | #define CLCD_LBAS 0x00000014 |
| 23 | |
Russell King | 3f17522 | 2010-02-12 14:32:01 +0000 | [diff] [blame] | 24 | #define CLCD_PL110_IENB 0x00000018 |
| 25 | #define CLCD_PL110_CNTL 0x0000001c |
| 26 | #define CLCD_PL110_STAT 0x00000020 |
| 27 | #define CLCD_PL110_INTR 0x00000024 |
| 28 | #define CLCD_PL110_UCUR 0x00000028 |
| 29 | #define CLCD_PL110_LCUR 0x0000002C |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | |
Russell King | 3f17522 | 2010-02-12 14:32:01 +0000 | [diff] [blame] | 31 | #define CLCD_PL111_CNTL 0x00000018 |
| 32 | #define CLCD_PL111_IENB 0x0000001c |
| 33 | #define CLCD_PL111_RIS 0x00000020 |
| 34 | #define CLCD_PL111_MIS 0x00000024 |
| 35 | #define CLCD_PL111_ICR 0x00000028 |
| 36 | #define CLCD_PL111_UCUR 0x0000002c |
| 37 | #define CLCD_PL111_LCUR 0x00000030 |
| 38 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | #define CLCD_PALL 0x00000200 |
| 40 | #define CLCD_PALETTE 0x00000200 |
| 41 | |
| 42 | #define TIM2_CLKSEL (1 << 5) |
| 43 | #define TIM2_IVS (1 << 11) |
| 44 | #define TIM2_IHS (1 << 12) |
| 45 | #define TIM2_IPC (1 << 13) |
| 46 | #define TIM2_IOE (1 << 14) |
| 47 | #define TIM2_BCD (1 << 26) |
| 48 | |
| 49 | #define CNTL_LCDEN (1 << 0) |
| 50 | #define CNTL_LCDBPP1 (0 << 1) |
| 51 | #define CNTL_LCDBPP2 (1 << 1) |
| 52 | #define CNTL_LCDBPP4 (2 << 1) |
| 53 | #define CNTL_LCDBPP8 (3 << 1) |
| 54 | #define CNTL_LCDBPP16 (4 << 1) |
Catalin Marinas | 243f196 | 2006-03-16 14:10:19 +0000 | [diff] [blame] | 55 | #define CNTL_LCDBPP16_565 (6 << 1) |
Russell King | 7b4e9ce | 2011-01-21 14:03:28 +0000 | [diff] [blame] | 56 | #define CNTL_LCDBPP16_444 (7 << 1) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 57 | #define CNTL_LCDBPP24 (5 << 1) |
| 58 | #define CNTL_LCDBW (1 << 4) |
| 59 | #define CNTL_LCDTFT (1 << 5) |
| 60 | #define CNTL_LCDMONO8 (1 << 6) |
| 61 | #define CNTL_LCDDUAL (1 << 7) |
| 62 | #define CNTL_BGR (1 << 8) |
| 63 | #define CNTL_BEBO (1 << 9) |
| 64 | #define CNTL_BEPO (1 << 10) |
| 65 | #define CNTL_LCDPWR (1 << 11) |
| 66 | #define CNTL_LCDVCOMP(x) ((x) << 12) |
| 67 | #define CNTL_LDMAFIFOTIME (1 << 15) |
| 68 | #define CNTL_WATERMARK (1 << 16) |
| 69 | |
Russell King | 7b4e9ce | 2011-01-21 14:03:28 +0000 | [diff] [blame] | 70 | enum { |
| 71 | /* individual formats */ |
| 72 | CLCD_CAP_RGB444 = (1 << 0), |
| 73 | CLCD_CAP_RGB5551 = (1 << 1), |
| 74 | CLCD_CAP_RGB565 = (1 << 2), |
| 75 | CLCD_CAP_RGB888 = (1 << 3), |
| 76 | CLCD_CAP_BGR444 = (1 << 4), |
| 77 | CLCD_CAP_BGR5551 = (1 << 5), |
| 78 | CLCD_CAP_BGR565 = (1 << 6), |
| 79 | CLCD_CAP_BGR888 = (1 << 7), |
| 80 | |
| 81 | /* connection layouts */ |
| 82 | CLCD_CAP_444 = CLCD_CAP_RGB444 | CLCD_CAP_BGR444, |
| 83 | CLCD_CAP_5551 = CLCD_CAP_RGB5551 | CLCD_CAP_BGR5551, |
| 84 | CLCD_CAP_565 = CLCD_CAP_RGB565 | CLCD_CAP_BGR565, |
| 85 | CLCD_CAP_888 = CLCD_CAP_RGB888 | CLCD_CAP_BGR888, |
| 86 | |
| 87 | /* red/blue ordering */ |
| 88 | CLCD_CAP_RGB = CLCD_CAP_RGB444 | CLCD_CAP_RGB5551 | |
| 89 | CLCD_CAP_RGB565 | CLCD_CAP_RGB888, |
| 90 | CLCD_CAP_BGR = CLCD_CAP_BGR444 | CLCD_CAP_BGR5551 | |
| 91 | CLCD_CAP_BGR565 | CLCD_CAP_BGR888, |
| 92 | |
| 93 | CLCD_CAP_ALL = CLCD_CAP_BGR | CLCD_CAP_RGB, |
| 94 | }; |
| 95 | |
Linus Walleij | c38162b | 2016-06-16 11:36:13 +0200 | [diff] [blame^] | 96 | struct backlight_device; |
| 97 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 98 | struct clcd_panel { |
| 99 | struct fb_videomode mode; |
| 100 | signed short width; /* width in mm */ |
| 101 | signed short height; /* height in mm */ |
| 102 | u32 tim2; |
| 103 | u32 tim3; |
| 104 | u32 cntl; |
Russell King | 7b4e9ce | 2011-01-21 14:03:28 +0000 | [diff] [blame] | 105 | u32 caps; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 106 | unsigned int bpp:8, |
| 107 | fixedtimings:1, |
| 108 | grayscale:1; |
| 109 | unsigned int connector; |
Linus Walleij | c38162b | 2016-06-16 11:36:13 +0200 | [diff] [blame^] | 110 | struct backlight_device *backlight; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 111 | }; |
| 112 | |
| 113 | struct clcd_regs { |
| 114 | u32 tim0; |
| 115 | u32 tim1; |
| 116 | u32 tim2; |
| 117 | u32 tim3; |
| 118 | u32 cntl; |
| 119 | unsigned long pixclock; |
| 120 | }; |
| 121 | |
| 122 | struct clcd_fb; |
| 123 | |
| 124 | /* |
| 125 | * the board-type specific routines |
| 126 | */ |
| 127 | struct clcd_board { |
| 128 | const char *name; |
| 129 | |
| 130 | /* |
Russell King | 7b4e9ce | 2011-01-21 14:03:28 +0000 | [diff] [blame] | 131 | * Optional. Hardware capability flags. |
| 132 | */ |
| 133 | u32 caps; |
| 134 | |
| 135 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 136 | * Optional. Check whether the var structure is acceptable |
| 137 | * for this display. |
| 138 | */ |
| 139 | int (*check)(struct clcd_fb *fb, struct fb_var_screeninfo *var); |
| 140 | |
| 141 | /* |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 142 | * Compulsory. Decode fb->fb.var into regs->*. In the case of |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 143 | * fixed timing, set regs->* to the register values required. |
| 144 | */ |
| 145 | void (*decode)(struct clcd_fb *fb, struct clcd_regs *regs); |
| 146 | |
| 147 | /* |
| 148 | * Optional. Disable any extra display hardware. |
| 149 | */ |
| 150 | void (*disable)(struct clcd_fb *); |
| 151 | |
| 152 | /* |
| 153 | * Optional. Enable any extra display hardware. |
| 154 | */ |
| 155 | void (*enable)(struct clcd_fb *); |
| 156 | |
| 157 | /* |
| 158 | * Setup platform specific parts of CLCD driver |
| 159 | */ |
| 160 | int (*setup)(struct clcd_fb *); |
| 161 | |
| 162 | /* |
| 163 | * mmap the framebuffer memory |
| 164 | */ |
| 165 | int (*mmap)(struct clcd_fb *, struct vm_area_struct *); |
| 166 | |
| 167 | /* |
| 168 | * Remove platform specific parts of CLCD driver |
| 169 | */ |
| 170 | void (*remove)(struct clcd_fb *); |
| 171 | }; |
| 172 | |
| 173 | struct amba_device; |
| 174 | struct clk; |
| 175 | |
| 176 | /* this data structure describes each frame buffer device we find */ |
| 177 | struct clcd_fb { |
| 178 | struct fb_info fb; |
| 179 | struct amba_device *dev; |
| 180 | struct clk *clk; |
| 181 | struct clcd_panel *panel; |
| 182 | struct clcd_board *board; |
| 183 | void *board_data; |
| 184 | void __iomem *regs; |
Russell King | 3f17522 | 2010-02-12 14:32:01 +0000 | [diff] [blame] | 185 | u16 off_ienb; |
| 186 | u16 off_cntl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 187 | u32 clcd_cntl; |
| 188 | u32 cmap[16]; |
Russell King | 99c796d | 2010-08-17 22:13:22 +0100 | [diff] [blame] | 189 | bool clk_enabled; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 190 | }; |
| 191 | |
| 192 | static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs) |
| 193 | { |
Russell King | 7b4e9ce | 2011-01-21 14:03:28 +0000 | [diff] [blame] | 194 | struct fb_var_screeninfo *var = &fb->fb.var; |
Russell King | c4d12b9 | 2005-04-28 10:38:19 +0100 | [diff] [blame] | 195 | u32 val, cpl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 196 | |
| 197 | /* |
| 198 | * Program the CLCD controller registers and start the CLCD |
| 199 | */ |
Russell King | 7b4e9ce | 2011-01-21 14:03:28 +0000 | [diff] [blame] | 200 | val = ((var->xres / 16) - 1) << 2; |
| 201 | val |= (var->hsync_len - 1) << 8; |
| 202 | val |= (var->right_margin - 1) << 16; |
| 203 | val |= (var->left_margin - 1) << 24; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 204 | regs->tim0 = val; |
| 205 | |
Russell King | 7b4e9ce | 2011-01-21 14:03:28 +0000 | [diff] [blame] | 206 | val = var->yres; |
Russell King | c4d12b9 | 2005-04-28 10:38:19 +0100 | [diff] [blame] | 207 | if (fb->panel->cntl & CNTL_LCDDUAL) |
| 208 | val /= 2; |
| 209 | val -= 1; |
Russell King | 7b4e9ce | 2011-01-21 14:03:28 +0000 | [diff] [blame] | 210 | val |= (var->vsync_len - 1) << 10; |
| 211 | val |= var->lower_margin << 16; |
| 212 | val |= var->upper_margin << 24; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 213 | regs->tim1 = val; |
| 214 | |
| 215 | val = fb->panel->tim2; |
Russell King | 7b4e9ce | 2011-01-21 14:03:28 +0000 | [diff] [blame] | 216 | val |= var->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : TIM2_IHS; |
| 217 | val |= var->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : TIM2_IVS; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 218 | |
Russell King | 7b4e9ce | 2011-01-21 14:03:28 +0000 | [diff] [blame] | 219 | cpl = var->xres_virtual; |
Russell King | c4d12b9 | 2005-04-28 10:38:19 +0100 | [diff] [blame] | 220 | if (fb->panel->cntl & CNTL_LCDTFT) /* TFT */ |
| 221 | /* / 1 */; |
Russell King | 7b4e9ce | 2011-01-21 14:03:28 +0000 | [diff] [blame] | 222 | else if (!var->grayscale) /* STN color */ |
Russell King | c4d12b9 | 2005-04-28 10:38:19 +0100 | [diff] [blame] | 223 | cpl = cpl * 8 / 3; |
| 224 | else if (fb->panel->cntl & CNTL_LCDMONO8) /* STN monochrome, 8bit */ |
| 225 | cpl /= 8; |
| 226 | else /* STN monochrome, 4bit */ |
| 227 | cpl /= 4; |
| 228 | |
| 229 | regs->tim2 = val | ((cpl - 1) << 16); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 230 | |
| 231 | regs->tim3 = fb->panel->tim3; |
| 232 | |
| 233 | val = fb->panel->cntl; |
Russell King | 7b4e9ce | 2011-01-21 14:03:28 +0000 | [diff] [blame] | 234 | if (var->grayscale) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 235 | val |= CNTL_LCDBW; |
| 236 | |
Russell King | 7b4e9ce | 2011-01-21 14:03:28 +0000 | [diff] [blame] | 237 | if (fb->panel->caps && fb->board->caps && |
| 238 | var->bits_per_pixel >= 16) { |
| 239 | /* |
| 240 | * if board and panel supply capabilities, we can support |
| 241 | * changing BGR/RGB depending on supplied parameters |
| 242 | */ |
| 243 | if (var->red.offset == 0) |
| 244 | val &= ~CNTL_BGR; |
| 245 | else |
| 246 | val |= CNTL_BGR; |
| 247 | } |
| 248 | |
| 249 | switch (var->bits_per_pixel) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 250 | case 1: |
| 251 | val |= CNTL_LCDBPP1; |
| 252 | break; |
| 253 | case 2: |
| 254 | val |= CNTL_LCDBPP2; |
| 255 | break; |
| 256 | case 4: |
| 257 | val |= CNTL_LCDBPP4; |
| 258 | break; |
| 259 | case 8: |
| 260 | val |= CNTL_LCDBPP8; |
| 261 | break; |
| 262 | case 16: |
Catalin Marinas | 243f196 | 2006-03-16 14:10:19 +0000 | [diff] [blame] | 263 | /* |
Russell King | 9c49e4a | 2011-01-19 21:13:33 +0000 | [diff] [blame] | 264 | * PL110 cannot choose between 5551 and 565 modes in its |
| 265 | * control register. It is possible to use 565 with |
| 266 | * custom external wiring. |
Catalin Marinas | 243f196 | 2006-03-16 14:10:19 +0000 | [diff] [blame] | 267 | */ |
Russell King | 9c49e4a | 2011-01-19 21:13:33 +0000 | [diff] [blame] | 268 | if (amba_part(fb->dev) == 0x110 || |
Russell King | 7b4e9ce | 2011-01-21 14:03:28 +0000 | [diff] [blame] | 269 | var->green.length == 5) |
Catalin Marinas | 243f196 | 2006-03-16 14:10:19 +0000 | [diff] [blame] | 270 | val |= CNTL_LCDBPP16; |
Russell King | 7b4e9ce | 2011-01-21 14:03:28 +0000 | [diff] [blame] | 271 | else if (var->green.length == 6) |
Catalin Marinas | 243f196 | 2006-03-16 14:10:19 +0000 | [diff] [blame] | 272 | val |= CNTL_LCDBPP16_565; |
Russell King | 7b4e9ce | 2011-01-21 14:03:28 +0000 | [diff] [blame] | 273 | else |
| 274 | val |= CNTL_LCDBPP16_444; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 275 | break; |
Russell King | 82235e9 | 2005-04-28 10:43:52 +0100 | [diff] [blame] | 276 | case 32: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 277 | val |= CNTL_LCDBPP24; |
| 278 | break; |
| 279 | } |
| 280 | |
| 281 | regs->cntl = val; |
Russell King | 7b4e9ce | 2011-01-21 14:03:28 +0000 | [diff] [blame] | 282 | regs->pixclock = var->pixclock; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 283 | } |
| 284 | |
| 285 | static inline int clcdfb_check(struct clcd_fb *fb, struct fb_var_screeninfo *var) |
| 286 | { |
Russell King | 0f7ad45 | 2005-04-28 10:46:15 +0100 | [diff] [blame] | 287 | var->xres_virtual = var->xres = (var->xres + 15) & ~15; |
Russell King | c4d12b9 | 2005-04-28 10:38:19 +0100 | [diff] [blame] | 288 | var->yres_virtual = var->yres = (var->yres + 1) & ~1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 289 | |
| 290 | #define CHECK(e,l,h) (var->e < l || var->e > h) |
| 291 | if (CHECK(right_margin, (5+1), 256) || /* back porch */ |
| 292 | CHECK(left_margin, (5+1), 256) || /* front porch */ |
| 293 | CHECK(hsync_len, (5+1), 256) || |
| 294 | var->xres > 4096 || |
| 295 | var->lower_margin > 255 || /* back porch */ |
| 296 | var->upper_margin > 255 || /* front porch */ |
| 297 | var->vsync_len > 32 || |
| 298 | var->yres > 1024) |
| 299 | return -EINVAL; |
| 300 | #undef CHECK |
| 301 | |
| 302 | /* single panel mode: PCD = max(PCD, 1) */ |
| 303 | /* dual panel mode: PCD = max(PCD, 5) */ |
| 304 | |
| 305 | /* |
| 306 | * You can't change the grayscale setting, and |
| 307 | * we can only do non-interlaced video. |
| 308 | */ |
| 309 | if (var->grayscale != fb->fb.var.grayscale || |
| 310 | (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED) |
| 311 | return -EINVAL; |
| 312 | |
| 313 | #define CHECK(e) (var->e != fb->fb.var.e) |
| 314 | if (fb->panel->fixedtimings && |
| 315 | (CHECK(xres) || |
| 316 | CHECK(yres) || |
| 317 | CHECK(bits_per_pixel) || |
| 318 | CHECK(pixclock) || |
| 319 | CHECK(left_margin) || |
| 320 | CHECK(right_margin) || |
| 321 | CHECK(upper_margin) || |
| 322 | CHECK(lower_margin) || |
| 323 | CHECK(hsync_len) || |
| 324 | CHECK(vsync_len) || |
| 325 | CHECK(sync))) |
| 326 | return -EINVAL; |
| 327 | #undef CHECK |
| 328 | |
| 329 | var->nonstd = 0; |
| 330 | var->accel_flags = 0; |
| 331 | |
| 332 | return 0; |
| 333 | } |