blob: c5305e3ee4346932b44cc73074cb6718bd3a38ad [file] [log] [blame]
Tim Small5a2c6752007-07-19 01:49:42 -07001/*
2 * Intel 82443BX/GX (440BX/GX chipset) Memory Controller EDAC kernel
3 * module (C) 2006 Tim Small
4 *
5 * This file may be distributed under the terms of the GNU General
6 * Public License.
7 *
8 * Written by Tim Small <tim@buttersideup.com>, based on work by Linux
9 * Networx, Thayne Harbaugh, Dan Hollis <goemon at anime dot net> and
10 * others.
11 *
12 * 440GX fix by Jason Uhlenkott <juhlenko@akamai.com>.
13 *
14 * Written with reference to 82443BX Host Bridge Datasheet:
15 * http://www.intel.com/design/chipsets/440/documentation.htm
16 * references to this document given in [].
17 *
18 * This module doesn't support the 440LX, but it may be possible to
19 * make it do so (the 440LX's register definitions are different, but
20 * not completely so - I haven't studied them in enough detail to know
21 * how easy this would be).
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26
27#include <linux/pci.h>
28#include <linux/pci_ids.h>
29
30#include <linux/slab.h>
31
Hitoshi Mitakec3c52bc2008-04-29 01:03:18 -070032#include <linux/edac.h>
Douglas Thompson20bcb7a2007-07-19 01:49:47 -070033#include "edac_core.h"
Tim Small5a2c6752007-07-19 01:49:42 -070034
35#define I82443_REVISION "0.1"
36
37#define EDAC_MOD_STR "i82443bxgx_edac"
38
Tim Small5a2c6752007-07-19 01:49:42 -070039/* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memory
40 * Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory
41 * rows" "The 82443BX supports multiple-bit error detection and
42 * single-bit error correction when ECC mode is enabled and
43 * single/multi-bit error detection when correction is disabled.
44 * During writes to the DRAM, the 82443BX generates ECC for the data
45 * on a QWord basis. Partial QWord writes require a read-modify-write
46 * cycle when ECC is enabled."
47*/
48
49/* "Additionally, the 82443BX ensures that the data is corrected in
50 * main memory so that accumulation of errors is prevented. Another
51 * error within the same QWord would result in a double-bit error
52 * which is unrecoverable. This is known as hardware scrubbing since
53 * it requires no software intervention to correct the data in memory."
54 */
55
56/* [Also see page 100 (section 4.3), "DRAM Interface"]
57 * [Also see page 112 (section 4.6.1.4), ECC]
58 */
59
60#define I82443BXGX_NR_CSROWS 8
61#define I82443BXGX_NR_CHANS 1
62#define I82443BXGX_NR_DIMMS 4
63
Tim Small5a2c6752007-07-19 01:49:42 -070064/* 82443 PCI Device 0 */
Douglas Thompson11116602007-07-19 01:50:07 -070065#define I82443BXGX_NBXCFG 0x50 /* 32bit register starting at this PCI
66 * config space offset */
67#define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24 /* Array of bits, zero if
68 * row is non-ECC */
69#define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12 /* 2 bits,00=100MHz,10=66 MHz */
Tim Small5a2c6752007-07-19 01:49:42 -070070
Douglas Thompson11116602007-07-19 01:50:07 -070071#define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY 7 /* 2 bits: */
72#define I82443BXGX_NBXCFG_INTEGRITY_NONE 0x0 /* 00 = Non-ECC */
73#define I82443BXGX_NBXCFG_INTEGRITY_EC 0x1 /* 01 = EC (only) */
74#define I82443BXGX_NBXCFG_INTEGRITY_ECC 0x2 /* 10 = ECC */
75#define I82443BXGX_NBXCFG_INTEGRITY_SCRUB 0x3 /* 11 = ECC + HW Scrub */
Tim Small5a2c6752007-07-19 01:49:42 -070076
77#define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE 6
78
Tim Small5a2c6752007-07-19 01:49:42 -070079/* 82443 PCI Device 0 */
Douglas Thompson11116602007-07-19 01:50:07 -070080#define I82443BXGX_EAP 0x80 /* 32bit register starting at this PCI
81 * config space offset, Error Address
82 * Pointer Register */
83#define I82443BXGX_EAP_OFFSET_EAP 12 /* High 20 bits of error address */
84#define I82443BXGX_EAP_OFFSET_MBE BIT(1) /* Err at EAP was multi-bit (W1TC) */
85#define I82443BXGX_EAP_OFFSET_SBE BIT(0) /* Err at EAP was single-bit (W1TC) */
Tim Small5a2c6752007-07-19 01:49:42 -070086
Douglas Thompson11116602007-07-19 01:50:07 -070087#define I82443BXGX_ERRCMD 0x90 /* 8bit register starting at this PCI
Tim Small5a2c6752007-07-19 01:49:42 -070088 * config space offset. */
Douglas Thompson11116602007-07-19 01:50:07 -070089#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1) /* 1 = enable */
90#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0) /* 1 = enable */
Tim Small5a2c6752007-07-19 01:49:42 -070091
Douglas Thompson11116602007-07-19 01:50:07 -070092#define I82443BXGX_ERRSTS 0x91 /* 16bit register starting at this PCI
Tim Small5a2c6752007-07-19 01:49:42 -070093 * config space offset. */
Douglas Thompson11116602007-07-19 01:50:07 -070094#define I82443BXGX_ERRSTS_OFFSET_MBFRE 5 /* 3 bits - first err row multibit */
95#define I82443BXGX_ERRSTS_OFFSET_MEF BIT(4) /* 1 = MBE occurred */
96#define I82443BXGX_ERRSTS_OFFSET_SBFRE 1 /* 3 bits - first err row singlebit */
97#define I82443BXGX_ERRSTS_OFFSET_SEF BIT(0) /* 1 = SBE occurred */
Tim Small5a2c6752007-07-19 01:49:42 -070098
Douglas Thompson11116602007-07-19 01:50:07 -070099#define I82443BXGX_DRAMC 0x57 /* 8bit register starting at this PCI
100 * config space offset. */
101#define I82443BXGX_DRAMC_OFFSET_DT 3 /* 2 bits, DRAM Type */
102#define I82443BXGX_DRAMC_DRAM_IS_EDO 0 /* 00 = EDO */
Tim Small5a2c6752007-07-19 01:49:42 -0700103#define I82443BXGX_DRAMC_DRAM_IS_SDRAM 1 /* 01 = SDRAM */
Douglas Thompson11116602007-07-19 01:50:07 -0700104#define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2 /* 10 = Registered SDRAM */
Tim Small5a2c6752007-07-19 01:49:42 -0700105
Douglas Thompson11116602007-07-19 01:50:07 -0700106#define I82443BXGX_DRB 0x60 /* 8x 8bit registers starting at this PCI
107 * config space offset. */
Tim Small5a2c6752007-07-19 01:49:42 -0700108
109/* FIXME - don't poll when ECC disabled? */
110
Tim Small5a2c6752007-07-19 01:49:42 -0700111struct i82443bxgx_edacmc_error_info {
112 u32 eap;
113};
114
Dave Jiang456a2f92007-07-19 01:50:10 -0700115static struct edac_pci_ctl_info *i82443bxgx_pci;
116
Douglas Thompson11116602007-07-19 01:50:07 -0700117static void i82443bxgx_edacmc_get_error_info(struct mem_ctl_info *mci,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700118 struct i82443bxgx_edacmc_error_info
119 *info)
Tim Small5a2c6752007-07-19 01:49:42 -0700120{
121 struct pci_dev *pdev;
122 pdev = to_pci_dev(mci->dev);
123 pci_read_config_dword(pdev, I82443BXGX_EAP, &info->eap);
124 if (info->eap & I82443BXGX_EAP_OFFSET_SBE)
125 /* Clear error to allow next error to be reported [p.61] */
126 pci_write_bits32(pdev, I82443BXGX_EAP,
127 I82443BXGX_EAP_OFFSET_SBE,
128 I82443BXGX_EAP_OFFSET_SBE);
129
130 if (info->eap & I82443BXGX_EAP_OFFSET_MBE)
131 /* Clear error to allow next error to be reported [p.61] */
132 pci_write_bits32(pdev, I82443BXGX_EAP,
133 I82443BXGX_EAP_OFFSET_MBE,
134 I82443BXGX_EAP_OFFSET_MBE);
135}
136
Douglas Thompson11116602007-07-19 01:50:07 -0700137static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info *mci,
138 struct
139 i82443bxgx_edacmc_error_info
140 *info, int handle_errors)
Tim Small5a2c6752007-07-19 01:49:42 -0700141{
142 int error_found = 0;
143 u32 eapaddr, page, pageoffset;
144
145 /* bits 30:12 hold the 4kb block in which the error occurred
146 * [p.61] */
147 eapaddr = (info->eap & 0xfffff000);
148 page = eapaddr >> PAGE_SHIFT;
149 pageoffset = eapaddr - (page << PAGE_SHIFT);
150
Douglas Thompson11116602007-07-19 01:50:07 -0700151 if (info->eap & I82443BXGX_EAP_OFFSET_SBE) {
Tim Small5a2c6752007-07-19 01:49:42 -0700152 error_found = 1;
153 if (handle_errors)
Douglas Thompson11116602007-07-19 01:50:07 -0700154 edac_mc_handle_ce(mci, page, pageoffset,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700155 /* 440BX/GX don't make syndrome information
156 * available */
157 0, edac_mc_find_csrow_by_page(mci, page), 0,
158 mci->ctl_name);
Tim Small5a2c6752007-07-19 01:49:42 -0700159 }
160
Douglas Thompson11116602007-07-19 01:50:07 -0700161 if (info->eap & I82443BXGX_EAP_OFFSET_MBE) {
Tim Small5a2c6752007-07-19 01:49:42 -0700162 error_found = 1;
163 if (handle_errors)
Douglas Thompson11116602007-07-19 01:50:07 -0700164 edac_mc_handle_ue(mci, page, pageoffset,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700165 edac_mc_find_csrow_by_page(mci, page),
166 mci->ctl_name);
Tim Small5a2c6752007-07-19 01:49:42 -0700167 }
168
169 return error_found;
170}
171
Tim Small5a2c6752007-07-19 01:49:42 -0700172static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci)
173{
174 struct i82443bxgx_edacmc_error_info info;
175
176 debugf1("MC%d: " __FILE__ ": %s()\n", mci->mc_idx, __func__);
177 i82443bxgx_edacmc_get_error_info(mci, &info);
178 i82443bxgx_edacmc_process_error_info(mci, &info, 1);
179}
180
Tim Small5a2c6752007-07-19 01:49:42 -0700181static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700182 struct pci_dev *pdev,
183 enum edac_type edac_mode,
184 enum mem_type mtype)
Tim Small5a2c6752007-07-19 01:49:42 -0700185{
186 struct csrow_info *csrow;
187 int index;
188 u8 drbar, dramc;
189 u32 row_base, row_high_limit, row_high_limit_last;
190
191 pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
192 row_high_limit_last = 0;
193 for (index = 0; index < mci->nr_csrows; index++) {
194 csrow = &mci->csrows[index];
195 pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar);
196 debugf1("MC%d: " __FILE__ ": %s() Row=%d DRB = %#0x\n",
197 mci->mc_idx, __func__, index, drbar);
198 row_high_limit = ((u32) drbar << 23);
199 /* find the DRAM Chip Select Base address and mask */
200 debugf1("MC%d: " __FILE__ ": %s() Row=%d, "
201 "Boundry Address=%#0x, Last = %#0x \n",
202 mci->mc_idx, __func__, index, row_high_limit,
203 row_high_limit_last);
204
205 /* 440GX goes to 2GB, represented with a DRB of 0. */
206 if (row_high_limit_last && !row_high_limit)
207 row_high_limit = 1UL << 31;
208
209 /* This row is empty [p.49] */
210 if (row_high_limit == row_high_limit_last)
211 continue;
212 row_base = row_high_limit_last;
213 csrow->first_page = row_base >> PAGE_SHIFT;
214 csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
215 csrow->nr_pages = csrow->last_page - csrow->first_page + 1;
216 /* EAP reports in 4kilobyte granularity [61] */
217 csrow->grain = 1 << 12;
218 csrow->mtype = mtype;
219 /* I don't think 440BX can tell you device type? FIXME? */
220 csrow->dtype = DEV_UNKNOWN;
221 /* Mode is global to all rows on 440BX */
222 csrow->edac_mode = edac_mode;
223 row_high_limit_last = row_high_limit;
224 }
225}
226
Douglas Thompson11116602007-07-19 01:50:07 -0700227static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
Tim Small5a2c6752007-07-19 01:49:42 -0700228{
229 struct mem_ctl_info *mci;
230 u8 dramc;
231 u32 nbxcfg, ecc_mode;
232 enum mem_type mtype;
233 enum edac_type edac_mode;
234
235 debugf0("MC: " __FILE__ ": %s()\n", __func__);
236
237 /* Something is really hosed if PCI config space reads from
Douglas Thompson052dfb42007-07-19 01:50:13 -0700238 * the MC aren't working.
239 */
Tim Small5a2c6752007-07-19 01:49:42 -0700240 if (pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg))
241 return -EIO;
242
Doug Thompsonb8f6f972007-07-19 01:50:26 -0700243 mci = edac_mc_alloc(0, I82443BXGX_NR_CSROWS, I82443BXGX_NR_CHANS, 0);
Tim Small5a2c6752007-07-19 01:49:42 -0700244
245 if (mci == NULL)
246 return -ENOMEM;
247
248 debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
249 mci->dev = &pdev->dev;
250 mci->mtype_cap = MEM_FLAG_EDO | MEM_FLAG_SDR | MEM_FLAG_RDR;
251 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
252 pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
253 switch ((dramc >> I82443BXGX_DRAMC_OFFSET_DT) & (BIT(0) | BIT(1))) {
Douglas Thompson11116602007-07-19 01:50:07 -0700254 case I82443BXGX_DRAMC_DRAM_IS_EDO:
Tim Small5a2c6752007-07-19 01:49:42 -0700255 mtype = MEM_EDO;
256 break;
257 case I82443BXGX_DRAMC_DRAM_IS_SDRAM:
258 mtype = MEM_SDR;
259 break;
260 case I82443BXGX_DRAMC_DRAM_IS_RSDRAM:
261 mtype = MEM_RDR;
262 break;
263 default:
Douglas Thompson052dfb42007-07-19 01:50:13 -0700264 debugf0("Unknown/reserved DRAM type value "
265 "in DRAMC register!\n");
Tim Small5a2c6752007-07-19 01:49:42 -0700266 mtype = -MEM_UNKNOWN;
267 }
268
269 if ((mtype == MEM_SDR) || (mtype == MEM_RDR))
270 mci->edac_cap = mci->edac_ctl_cap;
271 else
272 mci->edac_cap = EDAC_FLAG_NONE;
273
274 mci->scrub_cap = SCRUB_FLAG_HW_SRC;
275 pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg);
276 ecc_mode = ((nbxcfg >> I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY) &
Douglas Thompson052dfb42007-07-19 01:50:13 -0700277 (BIT(0) | BIT(1)));
Tim Small5a2c6752007-07-19 01:49:42 -0700278
279 mci->scrub_mode = (ecc_mode == I82443BXGX_NBXCFG_INTEGRITY_SCRUB)
Douglas Thompson052dfb42007-07-19 01:50:13 -0700280 ? SCRUB_HW_SRC : SCRUB_NONE;
Tim Small5a2c6752007-07-19 01:49:42 -0700281
Douglas Thompson11116602007-07-19 01:50:07 -0700282 switch (ecc_mode) {
Tim Small5a2c6752007-07-19 01:49:42 -0700283 case I82443BXGX_NBXCFG_INTEGRITY_NONE:
284 edac_mode = EDAC_NONE;
285 break;
286 case I82443BXGX_NBXCFG_INTEGRITY_EC:
287 edac_mode = EDAC_EC;
288 break;
289 case I82443BXGX_NBXCFG_INTEGRITY_ECC:
290 case I82443BXGX_NBXCFG_INTEGRITY_SCRUB:
291 edac_mode = EDAC_SECDED;
292 break;
293 default:
Douglas Thompson052dfb42007-07-19 01:50:13 -0700294 debugf0("%s(): Unknown/reserved ECC state "
295 "in NBXCFG register!\n", __func__);
Tim Small5a2c6752007-07-19 01:49:42 -0700296 edac_mode = EDAC_UNKNOWN;
297 break;
298 }
299
300 i82443bxgx_init_csrows(mci, pdev, edac_mode, mtype);
301
302 /* Many BIOSes don't clear error flags on boot, so do this
303 * here, or we get "phantom" errors occuring at module-load
304 * time. */
305 pci_write_bits32(pdev, I82443BXGX_EAP,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700306 (I82443BXGX_EAP_OFFSET_SBE |
307 I82443BXGX_EAP_OFFSET_MBE),
308 (I82443BXGX_EAP_OFFSET_SBE |
309 I82443BXGX_EAP_OFFSET_MBE));
Tim Small5a2c6752007-07-19 01:49:42 -0700310
311 mci->mod_name = EDAC_MOD_STR;
312 mci->mod_ver = I82443_REVISION;
313 mci->ctl_name = "I82443BXGX";
Dave Jiangc4192702007-07-19 01:49:47 -0700314 mci->dev_name = pci_name(pdev);
Tim Small5a2c6752007-07-19 01:49:42 -0700315 mci->edac_check = i82443bxgx_edacmc_check;
316 mci->ctl_page_to_phys = NULL;
317
Doug Thompsonb8f6f972007-07-19 01:50:26 -0700318 if (edac_mc_add_mc(mci)) {
Tim Small5a2c6752007-07-19 01:49:42 -0700319 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
320 goto fail;
321 }
322
Dave Jiang456a2f92007-07-19 01:50:10 -0700323 /* allocating generic PCI control info */
324 i82443bxgx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
325 if (!i82443bxgx_pci) {
326 printk(KERN_WARNING
327 "%s(): Unable to create PCI control\n",
328 __func__);
329 printk(KERN_WARNING
330 "%s(): PCI error report via EDAC not setup\n",
331 __func__);
332 }
333
Tim Small5a2c6752007-07-19 01:49:42 -0700334 debugf3("MC: " __FILE__ ": %s(): success\n", __func__);
335 return 0;
336
Douglas Thompson052dfb42007-07-19 01:50:13 -0700337fail:
Tim Small5a2c6752007-07-19 01:49:42 -0700338 edac_mc_free(mci);
339 return -ENODEV;
340}
Douglas Thompson11116602007-07-19 01:50:07 -0700341
Tim Small5a2c6752007-07-19 01:49:42 -0700342EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_probe1);
343
344/* returns count (>= 0), or negative on error */
345static int __devinit i82443bxgx_edacmc_init_one(struct pci_dev *pdev,
Douglas Thompson11116602007-07-19 01:50:07 -0700346 const struct pci_device_id *ent)
Tim Small5a2c6752007-07-19 01:49:42 -0700347{
348 debugf0("MC: " __FILE__ ": %s()\n", __func__);
349
350 /* don't need to call pci_device_enable() */
Douglas Thompson11116602007-07-19 01:50:07 -0700351 return i82443bxgx_edacmc_probe1(pdev, ent->driver_data);
Tim Small5a2c6752007-07-19 01:49:42 -0700352}
353
Tim Small5a2c6752007-07-19 01:49:42 -0700354static void __devexit i82443bxgx_edacmc_remove_one(struct pci_dev *pdev)
355{
356 struct mem_ctl_info *mci;
357
358 debugf0(__FILE__ ": %s()\n", __func__);
359
Dave Jiang456a2f92007-07-19 01:50:10 -0700360 if (i82443bxgx_pci)
361 edac_pci_release_generic_ctl(i82443bxgx_pci);
362
Douglas Thompson11116602007-07-19 01:50:07 -0700363 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
Tim Small5a2c6752007-07-19 01:49:42 -0700364 return;
365
366 edac_mc_free(mci);
367}
Tim Small5a2c6752007-07-19 01:49:42 -0700368
Douglas Thompson11116602007-07-19 01:50:07 -0700369EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_remove_one);
Tim Small5a2c6752007-07-19 01:49:42 -0700370
371static const struct pci_device_id i82443bxgx_pci_tbl[] __devinitdata = {
372 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0)},
373 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2)},
374 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0)},
375 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2)},
376 {0,} /* 0 terminated list. */
377};
378
379MODULE_DEVICE_TABLE(pci, i82443bxgx_pci_tbl);
380
Tim Small5a2c6752007-07-19 01:49:42 -0700381static struct pci_driver i82443bxgx_edacmc_driver = {
382 .name = EDAC_MOD_STR,
383 .probe = i82443bxgx_edacmc_init_one,
384 .remove = __devexit_p(i82443bxgx_edacmc_remove_one),
385 .id_table = i82443bxgx_pci_tbl,
386};
387
Tim Small5a2c6752007-07-19 01:49:42 -0700388static int __init i82443bxgx_edacmc_init(void)
389{
Hitoshi Mitakec3c52bc2008-04-29 01:03:18 -0700390 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
391 opstate_init();
392
Tim Small5a2c6752007-07-19 01:49:42 -0700393 return pci_register_driver(&i82443bxgx_edacmc_driver);
394}
395
Tim Small5a2c6752007-07-19 01:49:42 -0700396static void __exit i82443bxgx_edacmc_exit(void)
397{
398 pci_unregister_driver(&i82443bxgx_edacmc_driver);
399}
400
Tim Small5a2c6752007-07-19 01:49:42 -0700401module_init(i82443bxgx_edacmc_init);
402module_exit(i82443bxgx_edacmc_exit);
403
Tim Small5a2c6752007-07-19 01:49:42 -0700404MODULE_LICENSE("GPL");
405MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD");
406MODULE_DESCRIPTION("EDAC MC support for Intel 82443BX/GX memory controllers");
Hitoshi Mitakec3c52bc2008-04-29 01:03:18 -0700407
408module_param(edac_op_state, int, 0444);
409MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");