blob: 910b97e813faf744e1a9928931a304ed810d7653 [file] [log] [blame]
Ben Skeggs6ee73862009-12-11 19:24:15 +10001/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#include <linux/console.h>
Paul Gortmakere0cd3602011-08-30 11:04:30 -040026#include <linux/module.h>
Ben Skeggs6ee73862009-12-11 19:24:15 +100027
28#include "drmP.h"
29#include "drm.h"
30#include "drm_crtc_helper.h"
31#include "nouveau_drv.h"
32#include "nouveau_hw.h"
33#include "nouveau_fb.h"
34#include "nouveau_fbcon.h"
Ben Skeggs64f1c112010-09-17 13:35:25 +100035#include "nouveau_pm.h"
Ben Skeggs6ee73862009-12-11 19:24:15 +100036#include "nv50_display.h"
37
38#include "drm_pciids.h"
39
Francisco Jerezde5899b2010-09-08 02:28:23 +020040MODULE_PARM_DESC(agpmode, "AGP mode (0 to disable AGP)");
41int nouveau_agpmode = -1;
42module_param_named(agpmode, nouveau_agpmode, int, 0400);
Ben Skeggs6ee73862009-12-11 19:24:15 +100043
44MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
Ben Skeggs03bc9672011-07-04 13:14:05 +100045int nouveau_modeset = -1;
Ben Skeggs6ee73862009-12-11 19:24:15 +100046module_param_named(modeset, nouveau_modeset, int, 0400);
47
48MODULE_PARM_DESC(vbios, "Override default VBIOS location");
49char *nouveau_vbios;
50module_param_named(vbios, nouveau_vbios, charp, 0400);
51
52MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
53int nouveau_vram_pushbuf;
54module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
55
56MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
Ben Skeggs2dfe36b2010-06-01 09:47:43 +100057int nouveau_vram_notify = 0;
Ben Skeggs6ee73862009-12-11 19:24:15 +100058module_param_named(vram_notify, nouveau_vram_notify, int, 0400);
59
Ben Skeggs7ad2d312011-12-11 00:30:05 +100060MODULE_PARM_DESC(vram_type, "Override detected VRAM type");
61char *nouveau_vram_type;
62module_param_named(vram_type, nouveau_vram_type, charp, 0400);
63
Ben Skeggs6ee73862009-12-11 19:24:15 +100064MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
65int nouveau_duallink = 1;
66module_param_named(duallink, nouveau_duallink, int, 0400);
67
68MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
69int nouveau_uscript_lvds = -1;
70module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);
71
72MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
73int nouveau_uscript_tmds = -1;
74module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
75
Ben Skeggsa1470892010-01-18 11:42:37 +100076MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
77int nouveau_ignorelid = 0;
78module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
79
Marcin Kościelnicki81e2d422010-02-25 00:54:04 +000080MODULE_PARM_DESC(noaccel, "Disable all acceleration");
Ben Skeggsaba99a82011-05-25 14:48:50 +100081int nouveau_noaccel = -1;
Marcin Kościelnickia32ed692010-01-26 14:00:42 +000082module_param_named(noaccel, nouveau_noaccel, int, 0400);
83
Marcin Kościelnicki81e2d422010-02-25 00:54:04 +000084MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
Marcin Kościelnickia32ed692010-01-26 14:00:42 +000085int nouveau_nofbaccel = 0;
86module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);
87
Marcin Kościelnicki0cba1b72010-09-29 11:15:01 +000088MODULE_PARM_DESC(force_post, "Force POST");
89int nouveau_force_post = 0;
90module_param_named(force_post, nouveau_force_post, int, 0400);
91
Ben Skeggsda647d52010-03-04 12:00:39 +100092MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
93int nouveau_override_conntype = 0;
94module_param_named(override_conntype, nouveau_override_conntype, int, 0400);
95
Jean Delvare1a5f9852011-11-30 17:23:55 +010096MODULE_PARM_DESC(tv_disable, "Disable TV-out detection");
Ben Skeggsf4053502010-03-15 09:43:51 +100097int nouveau_tv_disable = 0;
98module_param_named(tv_disable, nouveau_tv_disable, int, 0400);
99
Ben Skeggs6ee73862009-12-11 19:24:15 +1000100MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
101 "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
102 "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
103 "\t\tDefault: PAL\n"
104 "\t\t*NOTE* Ignored for cards with external TV encoders.");
105char *nouveau_tv_norm;
106module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
107
108MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
109 "\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
110 "\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
Jean Delvare1a5f9852011-11-30 17:23:55 +0100111 "\t\t0x100 vgaattr, 0x200 EVO (G80+)");
Ben Skeggs6ee73862009-12-11 19:24:15 +1000112int nouveau_reg_debug;
113module_param_named(reg_debug, nouveau_reg_debug, int, 0600);
114
Jean Delvare1a5f9852011-11-30 17:23:55 +0100115MODULE_PARM_DESC(perflvl, "Performance level (default: boot)");
Ben Skeggs6f876982010-09-16 16:47:14 +1000116char *nouveau_perflvl;
117module_param_named(perflvl, nouveau_perflvl, charp, 0400);
118
Jean Delvare1a5f9852011-11-30 17:23:55 +0100119MODULE_PARM_DESC(perflvl_wr, "Allow perflvl changes (warning: dangerous!)");
Ben Skeggs6f876982010-09-16 16:47:14 +1000120int nouveau_perflvl_wr;
121module_param_named(perflvl_wr, nouveau_perflvl_wr, int, 0400);
122
Jean Delvare1a5f9852011-11-30 17:23:55 +0100123MODULE_PARM_DESC(msi, "Enable MSI (default: off)");
Ben Skeggs35fa2f22010-10-21 14:07:03 +1000124int nouveau_msi;
125module_param_named(msi, nouveau_msi, int, 0400);
126
Jean Delvare1a5f9852011-11-30 17:23:55 +0100127MODULE_PARM_DESC(ctxfw, "Use external HUB/GPC ucode (fermi)");
Ben Skeggs0411de82011-05-25 18:32:44 +1000128int nouveau_ctxfw;
129module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
130
Jean Delvare1a5f9852011-11-30 17:23:55 +0100131MODULE_PARM_DESC(mxmdcb, "Santise DCB table according to MXM-SIS");
Ben Skeggsb4c26812011-10-12 16:36:42 +1000132int nouveau_mxmdcb = 1;
133module_param_named(mxmdcb, nouveau_mxmdcb, int, 0400);
134
Ben Skeggs6ee73862009-12-11 19:24:15 +1000135int nouveau_fbpercrtc;
136#if 0
137module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
138#endif
139
140static struct pci_device_id pciidlist[] = {
141 {
142 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
143 .class = PCI_BASE_CLASS_DISPLAY << 16,
144 .class_mask = 0xff << 16,
145 },
146 {
147 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
148 .class = PCI_BASE_CLASS_DISPLAY << 16,
149 .class_mask = 0xff << 16,
150 },
151 {}
152};
153
154MODULE_DEVICE_TABLE(pci, pciidlist);
155
156static struct drm_driver driver;
157
158static int __devinit
159nouveau_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
160{
Jordan Crousedcdb1672010-05-27 13:40:25 -0600161 return drm_get_pci_dev(pdev, ent, &driver);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000162}
163
164static void
165nouveau_pci_remove(struct pci_dev *pdev)
166{
167 struct drm_device *dev = pci_get_drvdata(pdev);
168
169 drm_put_dev(dev);
170}
171
Dave Airlie6a9ee8a2010-02-01 15:38:10 +1000172int
Ben Skeggs6ee73862009-12-11 19:24:15 +1000173nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
174{
175 struct drm_device *dev = pci_get_drvdata(pdev);
176 struct drm_nouveau_private *dev_priv = dev->dev_private;
177 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000178 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
179 struct nouveau_channel *chan;
180 struct drm_crtc *crtc;
Ben Skeggs92abe742011-04-01 13:26:35 +1000181 int ret, i, e;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000182
Ben Skeggs6ee73862009-12-11 19:24:15 +1000183 if (pm_state.event == PM_EVENT_PRETHAW)
184 return 0;
185
Dave Airlie5bcf7192010-12-07 09:20:40 +1000186 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
187 return 0;
188
Ben Skeggsf62b27d2011-11-09 15:18:47 +1000189 NV_INFO(dev, "Disabling display...\n");
190 nouveau_display_fini(dev);
Maxim Levitsky4bfb94a2011-10-09 22:58:33 +0200191
Ben Skeggscf41d532011-11-09 14:31:16 +1000192 NV_INFO(dev, "Disabling fbcon...\n");
193 nouveau_fbcon_set_suspend(dev, 1);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000194
Maarten Maathuis814415702010-02-21 13:28:35 +0100195 NV_INFO(dev, "Unpinning framebuffer(s)...\n");
Ben Skeggs6ee73862009-12-11 19:24:15 +1000196 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
197 struct nouveau_framebuffer *nouveau_fb;
198
199 nouveau_fb = nouveau_framebuffer(crtc->fb);
200 if (!nouveau_fb || !nouveau_fb->nvbo)
201 continue;
202
203 nouveau_bo_unpin(nouveau_fb->nvbo);
204 }
205
Maarten Maathuisb334f2b2010-05-09 14:49:52 +0200206 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
207 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
208
209 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
210 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
211 }
212
Ben Skeggs6ee73862009-12-11 19:24:15 +1000213 NV_INFO(dev, "Evicting buffers...\n");
214 ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
215
216 NV_INFO(dev, "Idling channels...\n");
217 for (i = 0; i < pfifo->channels; i++) {
Ben Skeggscff5c132010-10-06 16:16:59 +1000218 chan = dev_priv->channels.ptr[i];
Ben Skeggs6ee73862009-12-11 19:24:15 +1000219
Francisco Jerez6dccd312010-11-18 23:57:46 +0100220 if (chan && chan->pushbuf_bo)
221 nouveau_channel_idle(chan);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000222 }
223
Ben Skeggs03bd6ef2012-05-01 16:33:37 +1000224 if (dev_priv->card_type < NV_50) {
Ben Skeggs67b342e2012-05-01 10:14:07 +1000225 nv_wr32(dev, NV03_PFIFO_CACHES, 0);
226 nv_mask(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0);
227 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 0);
228 nv_mask(dev, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0);
229 }
Ben Skeggs6ee73862009-12-11 19:24:15 +1000230 pfifo->unload_context(dev);
Ben Skeggs92abe742011-04-01 13:26:35 +1000231
232 for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
Ben Skeggs6c320fe2011-07-20 11:22:33 +1000233 if (!dev_priv->eng[e])
234 continue;
235
236 ret = dev_priv->eng[e]->fini(dev, e, true);
237 if (ret) {
Marcin Slusarz13f90122011-11-06 20:32:03 +0100238 NV_ERROR(dev, "... engine %d failed: %d\n", e, ret);
Ben Skeggs6c320fe2011-07-20 11:22:33 +1000239 goto out_abort;
Ben Skeggs92abe742011-04-01 13:26:35 +1000240 }
241 }
Ben Skeggs6ee73862009-12-11 19:24:15 +1000242
Ben Skeggsdc1e5c02010-10-25 15:23:59 +1000243 ret = pinstmem->suspend(dev);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000244 if (ret) {
245 NV_ERROR(dev, "... failed: %d\n", ret);
246 goto out_abort;
247 }
248
Ben Skeggsdc1e5c02010-10-25 15:23:59 +1000249 NV_INFO(dev, "Suspending GPU objects...\n");
250 ret = nouveau_gpuobj_suspend(dev);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000251 if (ret) {
252 NV_ERROR(dev, "... failed: %d\n", ret);
Ben Skeggsdc1e5c02010-10-25 15:23:59 +1000253 pinstmem->resume(dev);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000254 goto out_abort;
255 }
256
257 NV_INFO(dev, "And we're gone!\n");
258 pci_save_state(pdev);
259 if (pm_state.event == PM_EVENT_SUSPEND) {
260 pci_disable_device(pdev);
261 pci_set_power_state(pdev, PCI_D3hot);
262 }
263
Ben Skeggs6ee73862009-12-11 19:24:15 +1000264 return 0;
265
266out_abort:
267 NV_INFO(dev, "Re-enabling acceleration..\n");
Ben Skeggs92abe742011-04-01 13:26:35 +1000268 for (e = e + 1; e < NVOBJ_ENGINE_NR; e++) {
269 if (dev_priv->eng[e])
270 dev_priv->eng[e]->init(dev, e);
271 }
Ben Skeggs03bd6ef2012-05-01 16:33:37 +1000272 if (dev_priv->card_type < NV_50) {
Ben Skeggs67b342e2012-05-01 10:14:07 +1000273 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 1);
274 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
275 nv_wr32(dev, NV03_PFIFO_CACHES, 1);
276 }
Ben Skeggs6ee73862009-12-11 19:24:15 +1000277 return ret;
278}
279
Dave Airlie6a9ee8a2010-02-01 15:38:10 +1000280int
Ben Skeggs6ee73862009-12-11 19:24:15 +1000281nouveau_pci_resume(struct pci_dev *pdev)
282{
283 struct drm_device *dev = pci_get_drvdata(pdev);
284 struct drm_nouveau_private *dev_priv = dev->dev_private;
285 struct nouveau_engine *engine = &dev_priv->engine;
286 struct drm_crtc *crtc;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000287 int ret, i;
288
Dave Airlie5bcf7192010-12-07 09:20:40 +1000289 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
290 return 0;
291
Ben Skeggs6ee73862009-12-11 19:24:15 +1000292 NV_INFO(dev, "We're back, enabling device...\n");
293 pci_set_power_state(pdev, PCI_D0);
294 pci_restore_state(pdev);
295 if (pci_enable_device(pdev))
296 return -1;
297 pci_set_master(dev->pdev);
298
Francisco Jereze04d8e82010-07-23 20:29:13 +0200299 /* Make sure the AGP controller is in a consistent state */
300 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP)
301 nouveau_mem_reset_agp(dev);
302
Francisco Jerezc88c2e02010-07-24 17:37:33 +0200303 /* Make the CRTCs accessible */
304 engine->display.early_init(dev);
305
Ben Skeggs6ee73862009-12-11 19:24:15 +1000306 NV_INFO(dev, "POSTing device...\n");
307 ret = nouveau_run_vbios_init(dev);
308 if (ret)
309 return ret;
310
311 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
312 ret = nouveau_mem_init_agp(dev);
313 if (ret) {
314 NV_ERROR(dev, "error reinitialising AGP: %d\n", ret);
315 return ret;
316 }
317 }
318
Ben Skeggsdc1e5c02010-10-25 15:23:59 +1000319 NV_INFO(dev, "Restoring GPU objects...\n");
320 nouveau_gpuobj_resume(dev);
321
Ben Skeggs6ee73862009-12-11 19:24:15 +1000322 NV_INFO(dev, "Reinitialising engines...\n");
323 engine->instmem.resume(dev);
324 engine->mc.init(dev);
325 engine->timer.init(dev);
326 engine->fb.init(dev);
Ben Skeggs6dfdd7a2011-03-31 15:40:43 +1000327 for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
328 if (dev_priv->eng[i])
329 dev_priv->eng[i]->init(dev, i);
330 }
Ben Skeggs6ee73862009-12-11 19:24:15 +1000331 engine->fifo.init(dev);
332
Ben Skeggs6ee73862009-12-11 19:24:15 +1000333 nouveau_irq_postinstall(dev);
334
335 /* Re-write SKIPS, they'll have been lost over the suspend */
336 if (nouveau_vram_pushbuf) {
337 struct nouveau_channel *chan;
338 int j;
339
340 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
Ben Skeggscff5c132010-10-06 16:16:59 +1000341 chan = dev_priv->channels.ptr[i];
Ben Skeggs3c8868d2009-12-16 14:51:13 +1000342 if (!chan || !chan->pushbuf_bo)
Ben Skeggs6ee73862009-12-11 19:24:15 +1000343 continue;
344
345 for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
346 nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
347 }
348 }
349
Maxim Levitsky71d91f62011-10-09 22:58:35 +0200350 nouveau_pm_resume(dev);
351
Ben Skeggs6ee73862009-12-11 19:24:15 +1000352 NV_INFO(dev, "Restoring mode...\n");
353 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
354 struct nouveau_framebuffer *nouveau_fb;
355
356 nouveau_fb = nouveau_framebuffer(crtc->fb);
357 if (!nouveau_fb || !nouveau_fb->nvbo)
358 continue;
359
360 nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
361 }
362
Maarten Maathuisb334f2b2010-05-09 14:49:52 +0200363 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
364 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
Maarten Maathuisb334f2b2010-05-09 14:49:52 +0200365
366 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
367 if (!ret)
368 ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
369 if (ret)
370 NV_ERROR(dev, "Could not pin/map cursor.\n");
371 }
372
Ben Skeggscf41d532011-11-09 14:31:16 +1000373 nouveau_fbcon_set_suspend(dev, 0);
374 nouveau_fbcon_zfill_all(dev);
375
Ben Skeggsf62b27d2011-11-09 15:18:47 +1000376 nouveau_display_init(dev);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000377
378 /* Force CLUT to get re-loaded during modeset */
379 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
380 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
381
382 nv_crtc->lut.depth = 0;
383 }
384
Ben Skeggs6ee73862009-12-11 19:24:15 +1000385 drm_helper_resume_force_mode(dev);
Dave Airlie38651672010-03-30 05:34:13 +0000386
Maxim Levitskya4eaa0a2011-10-09 22:58:34 +0200387 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
388 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
389 u32 offset = nv_crtc->cursor.nvbo->bo.offset;
390
391 nv_crtc->cursor.set_offset(nv_crtc, offset);
392 nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x,
393 nv_crtc->cursor_saved_y);
394 }
395
Ben Skeggs6ee73862009-12-11 19:24:15 +1000396 return 0;
397}
398
Arjan van de Vene08e96d2011-10-31 07:28:57 -0700399static const struct file_operations nouveau_driver_fops = {
400 .owner = THIS_MODULE,
401 .open = drm_open,
402 .release = drm_release,
403 .unlocked_ioctl = drm_ioctl,
404 .mmap = nouveau_ttm_mmap,
405 .poll = drm_poll,
406 .fasync = drm_fasync,
407 .read = drm_read,
408#if defined(CONFIG_COMPAT)
409 .compat_ioctl = nouveau_compat_ioctl,
410#endif
411 .llseek = noop_llseek,
412};
413
Ben Skeggs6ee73862009-12-11 19:24:15 +1000414static struct drm_driver driver = {
415 .driver_features =
416 DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
Ben Skeggscd0b0722010-06-01 15:56:22 +1000417 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
Dave Airlie22b33e82012-04-02 11:53:06 +0100418 DRIVER_MODESET | DRIVER_PRIME,
Ben Skeggs6ee73862009-12-11 19:24:15 +1000419 .load = nouveau_load,
420 .firstopen = nouveau_firstopen,
421 .lastclose = nouveau_lastclose,
422 .unload = nouveau_unload,
Ben Skeggs3f0a68d2011-05-31 11:11:28 +1000423 .open = nouveau_open,
Ben Skeggs6ee73862009-12-11 19:24:15 +1000424 .preclose = nouveau_preclose,
Ben Skeggs3f0a68d2011-05-31 11:11:28 +1000425 .postclose = nouveau_postclose,
Ben Skeggs6ee73862009-12-11 19:24:15 +1000426#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
427 .debugfs_init = nouveau_debugfs_init,
428 .debugfs_cleanup = nouveau_debugfs_takedown,
429#endif
430 .irq_preinstall = nouveau_irq_preinstall,
431 .irq_postinstall = nouveau_irq_postinstall,
432 .irq_uninstall = nouveau_irq_uninstall,
433 .irq_handler = nouveau_irq_handler,
Francisco Jerez042206c2010-10-21 18:19:29 +0200434 .get_vblank_counter = drm_vblank_count,
435 .enable_vblank = nouveau_vblank_enable,
436 .disable_vblank = nouveau_vblank_disable,
Ben Skeggs6ee73862009-12-11 19:24:15 +1000437 .reclaim_buffers = drm_core_reclaim_buffers,
Ben Skeggs6ee73862009-12-11 19:24:15 +1000438 .ioctls = nouveau_ioctls,
Arjan van de Vene08e96d2011-10-31 07:28:57 -0700439 .fops = &nouveau_driver_fops,
Dave Airlie22b33e82012-04-02 11:53:06 +0100440
441 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
442 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
443 .gem_prime_export = nouveau_gem_prime_export,
444 .gem_prime_import = nouveau_gem_prime_import,
445
Ben Skeggs6ee73862009-12-11 19:24:15 +1000446 .gem_init_object = nouveau_gem_object_new,
447 .gem_free_object = nouveau_gem_object_del,
Ben Skeggs639212d2011-06-03 16:18:26 +1000448 .gem_open_object = nouveau_gem_object_open,
449 .gem_close_object = nouveau_gem_object_close,
Ben Skeggs6ee73862009-12-11 19:24:15 +1000450
Ben Skeggs33dbc272011-09-30 08:55:50 +1000451 .dumb_create = nouveau_display_dumb_create,
452 .dumb_map_offset = nouveau_display_dumb_map_offset,
453 .dumb_destroy = nouveau_display_dumb_destroy,
454
Ben Skeggs6ee73862009-12-11 19:24:15 +1000455 .name = DRIVER_NAME,
456 .desc = DRIVER_DESC,
457#ifdef GIT_REVISION
458 .date = GIT_REVISION,
459#else
460 .date = DRIVER_DATE,
461#endif
462 .major = DRIVER_MAJOR,
463 .minor = DRIVER_MINOR,
464 .patchlevel = DRIVER_PATCHLEVEL,
465};
466
Dave Airlie8410ea32010-12-15 03:16:38 +1000467static struct pci_driver nouveau_pci_driver = {
468 .name = DRIVER_NAME,
469 .id_table = pciidlist,
470 .probe = nouveau_pci_probe,
471 .remove = nouveau_pci_remove,
472 .suspend = nouveau_pci_suspend,
473 .resume = nouveau_pci_resume
474};
475
Ben Skeggs6ee73862009-12-11 19:24:15 +1000476static int __init nouveau_init(void)
477{
478 driver.num_ioctls = nouveau_max_ioctl;
479
480 if (nouveau_modeset == -1) {
481#ifdef CONFIG_VGA_CONSOLE
482 if (vgacon_text_force())
483 nouveau_modeset = 0;
484 else
485#endif
486 nouveau_modeset = 1;
487 }
488
Ben Skeggscd0b0722010-06-01 15:56:22 +1000489 if (!nouveau_modeset)
490 return 0;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000491
Ben Skeggscd0b0722010-06-01 15:56:22 +1000492 nouveau_register_dsm_handler();
Dave Airlie8410ea32010-12-15 03:16:38 +1000493 return drm_pci_init(&driver, &nouveau_pci_driver);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000494}
495
496static void __exit nouveau_exit(void)
497{
Ben Skeggscd0b0722010-06-01 15:56:22 +1000498 if (!nouveau_modeset)
499 return;
500
Dave Airlie8410ea32010-12-15 03:16:38 +1000501 drm_pci_exit(&driver, &nouveau_pci_driver);
Dave Airlie6a9ee8a2010-02-01 15:38:10 +1000502 nouveau_unregister_dsm_handler();
Ben Skeggs6ee73862009-12-11 19:24:15 +1000503}
504
505module_init(nouveau_init);
506module_exit(nouveau_exit);
507
508MODULE_AUTHOR(DRIVER_AUTHOR);
509MODULE_DESCRIPTION(DRIVER_DESC);
510MODULE_LICENSE("GPL and additional rights");