Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Texas Instruments |
| 3 | * Author: Rob Clark <robdclark@gmail.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License version 2 as published by |
| 7 | * the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along with |
| 15 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 16 | */ |
| 17 | |
| 18 | |
| 19 | |
| 20 | #include <linux/module.h> |
| 21 | |
| 22 | #include <drm/drmP.h> |
| 23 | #include <drm/drm_crtc_helper.h> |
| 24 | #include <drm/drm_encoder_slave.h> |
| 25 | #include <drm/drm_edid.h> |
Russell King | c4c11dd | 2013-08-14 21:43:30 +0200 | [diff] [blame^] | 26 | #include <drm/i2c/tda998x.h> |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 27 | |
| 28 | #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) |
| 29 | |
| 30 | struct tda998x_priv { |
| 31 | struct i2c_client *cec; |
| 32 | uint16_t rev; |
| 33 | uint8_t current_page; |
| 34 | int dpms; |
Russell King | c4c11dd | 2013-08-14 21:43:30 +0200 | [diff] [blame^] | 35 | bool is_hdmi_sink; |
Russell King | 5e74c22 | 2013-08-14 21:43:29 +0200 | [diff] [blame] | 36 | u8 vip_cntrl_0; |
| 37 | u8 vip_cntrl_1; |
| 38 | u8 vip_cntrl_2; |
Russell King | c4c11dd | 2013-08-14 21:43:30 +0200 | [diff] [blame^] | 39 | struct tda998x_encoder_params params; |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 40 | }; |
| 41 | |
| 42 | #define to_tda998x_priv(x) ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv) |
| 43 | |
| 44 | /* The TDA9988 series of devices use a paged register scheme.. to simplify |
| 45 | * things we encode the page # in upper bits of the register #. To read/ |
| 46 | * write a given register, we need to make sure CURPAGE register is set |
| 47 | * appropriately. Which implies reads/writes are not atomic. Fun! |
| 48 | */ |
| 49 | |
| 50 | #define REG(page, addr) (((page) << 8) | (addr)) |
| 51 | #define REG2ADDR(reg) ((reg) & 0xff) |
| 52 | #define REG2PAGE(reg) (((reg) >> 8) & 0xff) |
| 53 | |
| 54 | #define REG_CURPAGE 0xff /* write */ |
| 55 | |
| 56 | |
| 57 | /* Page 00h: General Control */ |
| 58 | #define REG_VERSION_LSB REG(0x00, 0x00) /* read */ |
| 59 | #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */ |
| 60 | # define MAIN_CNTRL0_SR (1 << 0) |
| 61 | # define MAIN_CNTRL0_DECS (1 << 1) |
| 62 | # define MAIN_CNTRL0_DEHS (1 << 2) |
| 63 | # define MAIN_CNTRL0_CECS (1 << 3) |
| 64 | # define MAIN_CNTRL0_CEHS (1 << 4) |
| 65 | # define MAIN_CNTRL0_SCALER (1 << 7) |
| 66 | #define REG_VERSION_MSB REG(0x00, 0x02) /* read */ |
| 67 | #define REG_SOFTRESET REG(0x00, 0x0a) /* write */ |
| 68 | # define SOFTRESET_AUDIO (1 << 0) |
| 69 | # define SOFTRESET_I2C_MASTER (1 << 1) |
| 70 | #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */ |
| 71 | #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */ |
| 72 | #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */ |
| 73 | # define I2C_MASTER_DIS_MM (1 << 0) |
| 74 | # define I2C_MASTER_DIS_FILT (1 << 1) |
| 75 | # define I2C_MASTER_APP_STRT_LAT (1 << 2) |
Russell King | c4c11dd | 2013-08-14 21:43:30 +0200 | [diff] [blame^] | 76 | #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */ |
| 77 | # define FEAT_POWERDOWN_SPDIF (1 << 3) |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 78 | #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */ |
| 79 | #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */ |
| 80 | #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */ |
| 81 | # define INT_FLAGS_2_EDID_BLK_RD (1 << 1) |
Russell King | c4c11dd | 2013-08-14 21:43:30 +0200 | [diff] [blame^] | 82 | #define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */ |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 83 | #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */ |
| 84 | #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */ |
| 85 | #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */ |
| 86 | #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */ |
| 87 | #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */ |
| 88 | # define VIP_CNTRL_0_MIRR_A (1 << 7) |
| 89 | # define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4) |
| 90 | # define VIP_CNTRL_0_MIRR_B (1 << 3) |
| 91 | # define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0) |
| 92 | #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */ |
| 93 | # define VIP_CNTRL_1_MIRR_C (1 << 7) |
| 94 | # define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4) |
| 95 | # define VIP_CNTRL_1_MIRR_D (1 << 3) |
| 96 | # define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0) |
| 97 | #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */ |
| 98 | # define VIP_CNTRL_2_MIRR_E (1 << 7) |
| 99 | # define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4) |
| 100 | # define VIP_CNTRL_2_MIRR_F (1 << 3) |
| 101 | # define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0) |
| 102 | #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */ |
| 103 | # define VIP_CNTRL_3_X_TGL (1 << 0) |
| 104 | # define VIP_CNTRL_3_H_TGL (1 << 1) |
| 105 | # define VIP_CNTRL_3_V_TGL (1 << 2) |
| 106 | # define VIP_CNTRL_3_EMB (1 << 3) |
| 107 | # define VIP_CNTRL_3_SYNC_DE (1 << 4) |
| 108 | # define VIP_CNTRL_3_SYNC_HS (1 << 5) |
| 109 | # define VIP_CNTRL_3_DE_INT (1 << 6) |
| 110 | # define VIP_CNTRL_3_EDGE (1 << 7) |
| 111 | #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */ |
| 112 | # define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0) |
| 113 | # define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2) |
| 114 | # define VIP_CNTRL_4_CCIR656 (1 << 4) |
| 115 | # define VIP_CNTRL_4_656_ALT (1 << 5) |
| 116 | # define VIP_CNTRL_4_TST_656 (1 << 6) |
| 117 | # define VIP_CNTRL_4_TST_PAT (1 << 7) |
| 118 | #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */ |
| 119 | # define VIP_CNTRL_5_CKCASE (1 << 0) |
| 120 | # define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1) |
Russell King | c4c11dd | 2013-08-14 21:43:30 +0200 | [diff] [blame^] | 121 | #define REG_MUX_AP REG(0x00, 0x26) /* read/write */ |
Russell King | bcb2481 | 2013-08-14 21:43:27 +0200 | [diff] [blame] | 122 | #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */ |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 123 | #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */ |
| 124 | # define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0) |
| 125 | # define MAT_CONTRL_MAT_BP (1 << 2) |
| 126 | #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */ |
| 127 | #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */ |
| 128 | #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */ |
| 129 | #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */ |
| 130 | #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */ |
| 131 | #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */ |
| 132 | #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */ |
| 133 | #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */ |
| 134 | #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */ |
| 135 | #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */ |
| 136 | #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */ |
| 137 | #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */ |
| 138 | #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */ |
| 139 | #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */ |
| 140 | #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */ |
| 141 | #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */ |
| 142 | #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */ |
| 143 | #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */ |
| 144 | #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */ |
| 145 | #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */ |
| 146 | #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */ |
| 147 | #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */ |
| 148 | #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */ |
| 149 | #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */ |
| 150 | #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */ |
| 151 | #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */ |
| 152 | #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */ |
| 153 | #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */ |
| 154 | #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */ |
| 155 | #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */ |
| 156 | #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */ |
| 157 | #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */ |
| 158 | #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */ |
| 159 | #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */ |
| 160 | # define TBG_CNTRL_0_FRAME_DIS (1 << 5) |
| 161 | # define TBG_CNTRL_0_SYNC_MTHD (1 << 6) |
| 162 | # define TBG_CNTRL_0_SYNC_ONCE (1 << 7) |
| 163 | #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */ |
| 164 | # define TBG_CNTRL_1_VH_TGL_0 (1 << 0) |
| 165 | # define TBG_CNTRL_1_VH_TGL_1 (1 << 1) |
| 166 | # define TBG_CNTRL_1_VH_TGL_2 (1 << 2) |
| 167 | # define TBG_CNTRL_1_VHX_EXT_DE (1 << 3) |
| 168 | # define TBG_CNTRL_1_VHX_EXT_HS (1 << 4) |
| 169 | # define TBG_CNTRL_1_VHX_EXT_VS (1 << 5) |
| 170 | # define TBG_CNTRL_1_DWIN_DIS (1 << 6) |
| 171 | #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */ |
| 172 | #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */ |
| 173 | # define HVF_CNTRL_0_SM (1 << 7) |
| 174 | # define HVF_CNTRL_0_RWB (1 << 6) |
| 175 | # define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2) |
| 176 | # define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0) |
| 177 | #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */ |
| 178 | # define HVF_CNTRL_1_FOR (1 << 0) |
| 179 | # define HVF_CNTRL_1_YUVBLK (1 << 1) |
| 180 | # define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2) |
| 181 | # define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4) |
| 182 | # define HVF_CNTRL_1_SEMI_PLANAR (1 << 6) |
| 183 | #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */ |
Russell King | c4c11dd | 2013-08-14 21:43:30 +0200 | [diff] [blame^] | 184 | #define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */ |
| 185 | # define I2S_FORMAT(x) (((x) & 3) << 0) |
| 186 | #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */ |
| 187 | # define AIP_CLKSEL_FS(x) (((x) & 3) << 0) |
| 188 | # define AIP_CLKSEL_CLK_POL(x) (((x) & 1) << 2) |
| 189 | # define AIP_CLKSEL_AIP(x) (((x) & 7) << 3) |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 190 | |
| 191 | |
| 192 | /* Page 02h: PLL settings */ |
| 193 | #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */ |
| 194 | # define PLL_SERIAL_1_SRL_FDN (1 << 0) |
| 195 | # define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1) |
| 196 | # define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6) |
| 197 | #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */ |
| 198 | # define PLL_SERIAL_2_SRL_NOSC(x) (((x) & 3) << 0) |
| 199 | # define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) |
| 200 | #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */ |
| 201 | # define PLL_SERIAL_3_SRL_CCIR (1 << 0) |
| 202 | # define PLL_SERIAL_3_SRL_DE (1 << 2) |
| 203 | # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4) |
| 204 | #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */ |
| 205 | #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */ |
| 206 | #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */ |
| 207 | #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */ |
| 208 | #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */ |
| 209 | #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */ |
| 210 | #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */ |
| 211 | #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */ |
| 212 | #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */ |
Russell King | c4c11dd | 2013-08-14 21:43:30 +0200 | [diff] [blame^] | 213 | # define AUDIO_DIV_SERCLK_1 0 |
| 214 | # define AUDIO_DIV_SERCLK_2 1 |
| 215 | # define AUDIO_DIV_SERCLK_4 2 |
| 216 | # define AUDIO_DIV_SERCLK_8 3 |
| 217 | # define AUDIO_DIV_SERCLK_16 4 |
| 218 | # define AUDIO_DIV_SERCLK_32 5 |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 219 | #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */ |
| 220 | # define SEL_CLK_SEL_CLK1 (1 << 0) |
| 221 | # define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1) |
| 222 | # define SEL_CLK_ENA_SC_CLK (1 << 3) |
| 223 | #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */ |
| 224 | |
| 225 | |
| 226 | /* Page 09h: EDID Control */ |
| 227 | #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */ |
| 228 | /* next 127 successive registers are the EDID block */ |
| 229 | #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */ |
| 230 | #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */ |
| 231 | #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */ |
| 232 | #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */ |
| 233 | #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */ |
| 234 | |
| 235 | |
| 236 | /* Page 10h: information frames and packets */ |
Russell King | c4c11dd | 2013-08-14 21:43:30 +0200 | [diff] [blame^] | 237 | #define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */ |
| 238 | #define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */ |
| 239 | #define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */ |
| 240 | #define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */ |
| 241 | #define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */ |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 242 | |
| 243 | |
| 244 | /* Page 11h: audio settings and content info packets */ |
| 245 | #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */ |
| 246 | # define AIP_CNTRL_0_RST_FIFO (1 << 0) |
| 247 | # define AIP_CNTRL_0_SWAP (1 << 1) |
| 248 | # define AIP_CNTRL_0_LAYOUT (1 << 2) |
| 249 | # define AIP_CNTRL_0_ACR_MAN (1 << 5) |
| 250 | # define AIP_CNTRL_0_RST_CTS (1 << 6) |
Russell King | c4c11dd | 2013-08-14 21:43:30 +0200 | [diff] [blame^] | 251 | #define REG_CA_I2S REG(0x11, 0x01) /* read/write */ |
| 252 | # define CA_I2S_CA_I2S(x) (((x) & 31) << 0) |
| 253 | # define CA_I2S_HBR_CHSTAT (1 << 6) |
| 254 | #define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */ |
| 255 | #define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */ |
| 256 | #define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */ |
| 257 | #define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */ |
| 258 | #define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */ |
| 259 | #define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */ |
| 260 | #define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */ |
| 261 | #define REG_CTS_N REG(0x11, 0x0c) /* read/write */ |
| 262 | # define CTS_N_K(x) (((x) & 7) << 0) |
| 263 | # define CTS_N_M(x) (((x) & 3) << 4) |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 264 | #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */ |
| 265 | # define ENC_CNTRL_RST_ENC (1 << 0) |
| 266 | # define ENC_CNTRL_RST_SEL (1 << 1) |
| 267 | # define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2) |
Russell King | c4c11dd | 2013-08-14 21:43:30 +0200 | [diff] [blame^] | 268 | #define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */ |
| 269 | # define DIP_FLAGS_ACR (1 << 0) |
| 270 | # define DIP_FLAGS_GC (1 << 1) |
| 271 | #define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */ |
| 272 | # define DIP_IF_FLAGS_IF1 (1 << 1) |
| 273 | # define DIP_IF_FLAGS_IF2 (1 << 2) |
| 274 | # define DIP_IF_FLAGS_IF3 (1 << 3) |
| 275 | # define DIP_IF_FLAGS_IF4 (1 << 4) |
| 276 | # define DIP_IF_FLAGS_IF5 (1 << 5) |
| 277 | #define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */ |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 278 | |
| 279 | |
| 280 | /* Page 12h: HDCP and OTP */ |
| 281 | #define REG_TX3 REG(0x12, 0x9a) /* read/write */ |
Russell King | 063b472 | 2013-08-14 21:43:26 +0200 | [diff] [blame] | 282 | #define REG_TX4 REG(0x12, 0x9b) /* read/write */ |
| 283 | # define TX4_PD_RAM (1 << 1) |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 284 | #define REG_TX33 REG(0x12, 0xb8) /* read/write */ |
| 285 | # define TX33_HDMI (1 << 1) |
| 286 | |
| 287 | |
| 288 | /* Page 13h: Gamut related metadata packets */ |
| 289 | |
| 290 | |
| 291 | |
| 292 | /* CEC registers: (not paged) |
| 293 | */ |
| 294 | #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */ |
| 295 | # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7) |
| 296 | # define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6) |
| 297 | # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1) |
| 298 | # define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0) |
| 299 | #define REG_CEC_RXSHPDLEV 0xfe /* read */ |
| 300 | # define CEC_RXSHPDLEV_RXSENS (1 << 0) |
| 301 | # define CEC_RXSHPDLEV_HPD (1 << 1) |
| 302 | |
| 303 | #define REG_CEC_ENAMODS 0xff /* read/write */ |
| 304 | # define CEC_ENAMODS_DIS_FRO (1 << 6) |
| 305 | # define CEC_ENAMODS_DIS_CCLK (1 << 5) |
| 306 | # define CEC_ENAMODS_EN_RXSENS (1 << 2) |
| 307 | # define CEC_ENAMODS_EN_HDMI (1 << 1) |
| 308 | # define CEC_ENAMODS_EN_CEC (1 << 0) |
| 309 | |
| 310 | |
| 311 | /* Device versions: */ |
| 312 | #define TDA9989N2 0x0101 |
| 313 | #define TDA19989 0x0201 |
| 314 | #define TDA19989N2 0x0202 |
| 315 | #define TDA19988 0x0301 |
| 316 | |
| 317 | static void |
| 318 | cec_write(struct drm_encoder *encoder, uint16_t addr, uint8_t val) |
| 319 | { |
| 320 | struct i2c_client *client = to_tda998x_priv(encoder)->cec; |
| 321 | uint8_t buf[] = {addr, val}; |
| 322 | int ret; |
| 323 | |
| 324 | ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); |
| 325 | if (ret < 0) |
| 326 | dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr); |
| 327 | } |
| 328 | |
| 329 | static uint8_t |
| 330 | cec_read(struct drm_encoder *encoder, uint8_t addr) |
| 331 | { |
| 332 | struct i2c_client *client = to_tda998x_priv(encoder)->cec; |
| 333 | uint8_t val; |
| 334 | int ret; |
| 335 | |
| 336 | ret = i2c_master_send(client, &addr, sizeof(addr)); |
| 337 | if (ret < 0) |
| 338 | goto fail; |
| 339 | |
| 340 | ret = i2c_master_recv(client, &val, sizeof(val)); |
| 341 | if (ret < 0) |
| 342 | goto fail; |
| 343 | |
| 344 | return val; |
| 345 | |
| 346 | fail: |
| 347 | dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr); |
| 348 | return 0; |
| 349 | } |
| 350 | |
| 351 | static void |
| 352 | set_page(struct drm_encoder *encoder, uint16_t reg) |
| 353 | { |
| 354 | struct tda998x_priv *priv = to_tda998x_priv(encoder); |
| 355 | |
| 356 | if (REG2PAGE(reg) != priv->current_page) { |
| 357 | struct i2c_client *client = drm_i2c_encoder_get_client(encoder); |
| 358 | uint8_t buf[] = { |
| 359 | REG_CURPAGE, REG2PAGE(reg) |
| 360 | }; |
| 361 | int ret = i2c_master_send(client, buf, sizeof(buf)); |
| 362 | if (ret < 0) |
| 363 | dev_err(&client->dev, "Error %d writing to REG_CURPAGE\n", ret); |
| 364 | |
| 365 | priv->current_page = REG2PAGE(reg); |
| 366 | } |
| 367 | } |
| 368 | |
| 369 | static int |
| 370 | reg_read_range(struct drm_encoder *encoder, uint16_t reg, char *buf, int cnt) |
| 371 | { |
| 372 | struct i2c_client *client = drm_i2c_encoder_get_client(encoder); |
| 373 | uint8_t addr = REG2ADDR(reg); |
| 374 | int ret; |
| 375 | |
| 376 | set_page(encoder, reg); |
| 377 | |
| 378 | ret = i2c_master_send(client, &addr, sizeof(addr)); |
| 379 | if (ret < 0) |
| 380 | goto fail; |
| 381 | |
| 382 | ret = i2c_master_recv(client, buf, cnt); |
| 383 | if (ret < 0) |
| 384 | goto fail; |
| 385 | |
| 386 | return ret; |
| 387 | |
| 388 | fail: |
| 389 | dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg); |
| 390 | return ret; |
| 391 | } |
| 392 | |
Russell King | c4c11dd | 2013-08-14 21:43:30 +0200 | [diff] [blame^] | 393 | static void |
| 394 | reg_write_range(struct drm_encoder *encoder, uint16_t reg, uint8_t *p, int cnt) |
| 395 | { |
| 396 | struct i2c_client *client = drm_i2c_encoder_get_client(encoder); |
| 397 | uint8_t buf[cnt+1]; |
| 398 | int ret; |
| 399 | |
| 400 | buf[0] = REG2ADDR(reg); |
| 401 | memcpy(&buf[1], p, cnt); |
| 402 | |
| 403 | set_page(encoder, reg); |
| 404 | |
| 405 | ret = i2c_master_send(client, buf, cnt + 1); |
| 406 | if (ret < 0) |
| 407 | dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); |
| 408 | } |
| 409 | |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 410 | static uint8_t |
| 411 | reg_read(struct drm_encoder *encoder, uint16_t reg) |
| 412 | { |
| 413 | uint8_t val = 0; |
| 414 | reg_read_range(encoder, reg, &val, sizeof(val)); |
| 415 | return val; |
| 416 | } |
| 417 | |
| 418 | static void |
| 419 | reg_write(struct drm_encoder *encoder, uint16_t reg, uint8_t val) |
| 420 | { |
| 421 | struct i2c_client *client = drm_i2c_encoder_get_client(encoder); |
| 422 | uint8_t buf[] = {REG2ADDR(reg), val}; |
| 423 | int ret; |
| 424 | |
| 425 | set_page(encoder, reg); |
| 426 | |
| 427 | ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); |
| 428 | if (ret < 0) |
| 429 | dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); |
| 430 | } |
| 431 | |
| 432 | static void |
| 433 | reg_write16(struct drm_encoder *encoder, uint16_t reg, uint16_t val) |
| 434 | { |
| 435 | struct i2c_client *client = drm_i2c_encoder_get_client(encoder); |
| 436 | uint8_t buf[] = {REG2ADDR(reg), val >> 8, val}; |
| 437 | int ret; |
| 438 | |
| 439 | set_page(encoder, reg); |
| 440 | |
| 441 | ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); |
| 442 | if (ret < 0) |
| 443 | dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); |
| 444 | } |
| 445 | |
| 446 | static void |
| 447 | reg_set(struct drm_encoder *encoder, uint16_t reg, uint8_t val) |
| 448 | { |
| 449 | reg_write(encoder, reg, reg_read(encoder, reg) | val); |
| 450 | } |
| 451 | |
| 452 | static void |
| 453 | reg_clear(struct drm_encoder *encoder, uint16_t reg, uint8_t val) |
| 454 | { |
| 455 | reg_write(encoder, reg, reg_read(encoder, reg) & ~val); |
| 456 | } |
| 457 | |
| 458 | static void |
| 459 | tda998x_reset(struct drm_encoder *encoder) |
| 460 | { |
| 461 | /* reset audio and i2c master: */ |
| 462 | reg_set(encoder, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); |
| 463 | msleep(50); |
| 464 | reg_clear(encoder, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); |
| 465 | msleep(50); |
| 466 | |
| 467 | /* reset transmitter: */ |
| 468 | reg_set(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); |
| 469 | reg_clear(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); |
| 470 | |
| 471 | /* PLL registers common configuration */ |
| 472 | reg_write(encoder, REG_PLL_SERIAL_1, 0x00); |
| 473 | reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); |
| 474 | reg_write(encoder, REG_PLL_SERIAL_3, 0x00); |
| 475 | reg_write(encoder, REG_SERIALIZER, 0x00); |
| 476 | reg_write(encoder, REG_BUFFER_OUT, 0x00); |
| 477 | reg_write(encoder, REG_PLL_SCG1, 0x00); |
Russell King | c4c11dd | 2013-08-14 21:43:30 +0200 | [diff] [blame^] | 478 | reg_write(encoder, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8); |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 479 | reg_write(encoder, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); |
| 480 | reg_write(encoder, REG_PLL_SCGN1, 0xfa); |
| 481 | reg_write(encoder, REG_PLL_SCGN2, 0x00); |
| 482 | reg_write(encoder, REG_PLL_SCGR1, 0x5b); |
| 483 | reg_write(encoder, REG_PLL_SCGR2, 0x00); |
| 484 | reg_write(encoder, REG_PLL_SCG2, 0x10); |
Russell King | bcb2481 | 2013-08-14 21:43:27 +0200 | [diff] [blame] | 485 | |
| 486 | /* Write the default value MUX register */ |
| 487 | reg_write(encoder, REG_MUX_VP_VIP_OUT, 0x24); |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 488 | } |
| 489 | |
Russell King | c4c11dd | 2013-08-14 21:43:30 +0200 | [diff] [blame^] | 490 | static uint8_t tda998x_cksum(uint8_t *buf, size_t bytes) |
| 491 | { |
| 492 | uint8_t sum = 0; |
| 493 | |
| 494 | while (bytes--) |
| 495 | sum += *buf++; |
| 496 | return (255 - sum) + 1; |
| 497 | } |
| 498 | |
| 499 | #define HB(x) (x) |
| 500 | #define PB(x) (HB(2) + 1 + (x)) |
| 501 | |
| 502 | static void |
| 503 | tda998x_write_if(struct drm_encoder *encoder, uint8_t bit, uint16_t addr, |
| 504 | uint8_t *buf, size_t size) |
| 505 | { |
| 506 | buf[PB(0)] = tda998x_cksum(buf, size); |
| 507 | |
| 508 | reg_clear(encoder, REG_DIP_IF_FLAGS, bit); |
| 509 | reg_write_range(encoder, addr, buf, size); |
| 510 | reg_set(encoder, REG_DIP_IF_FLAGS, bit); |
| 511 | } |
| 512 | |
| 513 | static void |
| 514 | tda998x_write_aif(struct drm_encoder *encoder, struct tda998x_encoder_params *p) |
| 515 | { |
| 516 | uint8_t buf[PB(5) + 1]; |
| 517 | |
| 518 | buf[HB(0)] = 0x84; |
| 519 | buf[HB(1)] = 0x01; |
| 520 | buf[HB(2)] = 10; |
| 521 | buf[PB(0)] = 0; |
| 522 | buf[PB(1)] = p->audio_frame[1] & 0x07; /* CC */ |
| 523 | buf[PB(2)] = p->audio_frame[2] & 0x1c; /* SF */ |
| 524 | buf[PB(4)] = p->audio_frame[4]; |
| 525 | buf[PB(5)] = p->audio_frame[5] & 0xf8; /* DM_INH + LSV */ |
| 526 | |
| 527 | tda998x_write_if(encoder, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf, |
| 528 | sizeof(buf)); |
| 529 | } |
| 530 | |
| 531 | static void |
| 532 | tda998x_write_avi(struct drm_encoder *encoder, struct drm_display_mode *mode) |
| 533 | { |
| 534 | uint8_t buf[PB(13) + 1]; |
| 535 | |
| 536 | memset(buf, 0, sizeof(buf)); |
| 537 | buf[HB(0)] = 0x82; |
| 538 | buf[HB(1)] = 0x02; |
| 539 | buf[HB(2)] = 13; |
| 540 | buf[PB(4)] = drm_match_cea_mode(mode); |
| 541 | |
| 542 | tda998x_write_if(encoder, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf, |
| 543 | sizeof(buf)); |
| 544 | } |
| 545 | |
| 546 | static void tda998x_audio_mute(struct drm_encoder *encoder, bool on) |
| 547 | { |
| 548 | if (on) { |
| 549 | reg_set(encoder, REG_SOFTRESET, SOFTRESET_AUDIO); |
| 550 | reg_clear(encoder, REG_SOFTRESET, SOFTRESET_AUDIO); |
| 551 | reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); |
| 552 | } else { |
| 553 | reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); |
| 554 | } |
| 555 | } |
| 556 | |
| 557 | static void |
| 558 | tda998x_configure_audio(struct drm_encoder *encoder, |
| 559 | struct drm_display_mode *mode, struct tda998x_encoder_params *p) |
| 560 | { |
| 561 | uint8_t buf[6], clksel_aip, clksel_fs, ca_i2s, cts_n, adiv; |
| 562 | uint32_t n; |
| 563 | |
| 564 | /* Enable audio ports */ |
| 565 | reg_write(encoder, REG_ENA_AP, p->audio_cfg); |
| 566 | reg_write(encoder, REG_ENA_ACLK, p->audio_clk_cfg); |
| 567 | |
| 568 | /* Set audio input source */ |
| 569 | switch (p->audio_format) { |
| 570 | case AFMT_SPDIF: |
| 571 | reg_write(encoder, REG_MUX_AP, 0x40); |
| 572 | clksel_aip = AIP_CLKSEL_AIP(0); |
| 573 | /* FS64SPDIF */ |
| 574 | clksel_fs = AIP_CLKSEL_FS(2); |
| 575 | cts_n = CTS_N_M(3) | CTS_N_K(3); |
| 576 | ca_i2s = 0; |
| 577 | break; |
| 578 | |
| 579 | case AFMT_I2S: |
| 580 | reg_write(encoder, REG_MUX_AP, 0x64); |
| 581 | clksel_aip = AIP_CLKSEL_AIP(1); |
| 582 | /* ACLK */ |
| 583 | clksel_fs = AIP_CLKSEL_FS(0); |
| 584 | cts_n = CTS_N_M(3) | CTS_N_K(3); |
| 585 | ca_i2s = CA_I2S_CA_I2S(0); |
| 586 | break; |
| 587 | } |
| 588 | |
| 589 | reg_write(encoder, REG_AIP_CLKSEL, clksel_aip); |
| 590 | reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT); |
| 591 | |
| 592 | /* Enable automatic CTS generation */ |
| 593 | reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_ACR_MAN); |
| 594 | reg_write(encoder, REG_CTS_N, cts_n); |
| 595 | |
| 596 | /* |
| 597 | * Audio input somehow depends on HDMI line rate which is |
| 598 | * related to pixclk. Testing showed that modes with pixclk |
| 599 | * >100MHz need a larger divider while <40MHz need the default. |
| 600 | * There is no detailed info in the datasheet, so we just |
| 601 | * assume 100MHz requires larger divider. |
| 602 | */ |
| 603 | if (mode->clock > 100000) |
| 604 | adiv = AUDIO_DIV_SERCLK_16; |
| 605 | else |
| 606 | adiv = AUDIO_DIV_SERCLK_8; |
| 607 | reg_write(encoder, REG_AUDIO_DIV, adiv); |
| 608 | |
| 609 | /* |
| 610 | * This is the approximate value of N, which happens to be |
| 611 | * the recommended values for non-coherent clocks. |
| 612 | */ |
| 613 | n = 128 * p->audio_sample_rate / 1000; |
| 614 | |
| 615 | /* Write the CTS and N values */ |
| 616 | buf[0] = 0x44; |
| 617 | buf[1] = 0x42; |
| 618 | buf[2] = 0x01; |
| 619 | buf[3] = n; |
| 620 | buf[4] = n >> 8; |
| 621 | buf[5] = n >> 16; |
| 622 | reg_write_range(encoder, REG_ACR_CTS_0, buf, 6); |
| 623 | |
| 624 | /* Set CTS clock reference */ |
| 625 | reg_write(encoder, REG_AIP_CLKSEL, clksel_aip | clksel_fs); |
| 626 | |
| 627 | /* Reset CTS generator */ |
| 628 | reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); |
| 629 | reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); |
| 630 | |
| 631 | /* Write the channel status */ |
| 632 | buf[0] = 0x04; |
| 633 | buf[1] = 0x00; |
| 634 | buf[2] = 0x00; |
| 635 | buf[3] = 0xf1; |
| 636 | reg_write_range(encoder, REG_CH_STAT_B(0), buf, 4); |
| 637 | |
| 638 | tda998x_audio_mute(encoder, true); |
| 639 | mdelay(20); |
| 640 | tda998x_audio_mute(encoder, false); |
| 641 | |
| 642 | /* Write the audio information packet */ |
| 643 | tda998x_write_aif(encoder, p); |
| 644 | } |
| 645 | |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 646 | /* DRM encoder functions */ |
| 647 | |
| 648 | static void |
| 649 | tda998x_encoder_set_config(struct drm_encoder *encoder, void *params) |
| 650 | { |
Russell King | c4c11dd | 2013-08-14 21:43:30 +0200 | [diff] [blame^] | 651 | struct tda998x_priv *priv = to_tda998x_priv(encoder); |
| 652 | struct tda998x_encoder_params *p = params; |
| 653 | |
| 654 | priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) | |
| 655 | (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) | |
| 656 | VIP_CNTRL_0_SWAP_B(p->swap_b) | |
| 657 | (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0); |
| 658 | priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) | |
| 659 | (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) | |
| 660 | VIP_CNTRL_1_SWAP_D(p->swap_d) | |
| 661 | (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0); |
| 662 | priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) | |
| 663 | (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) | |
| 664 | VIP_CNTRL_2_SWAP_F(p->swap_f) | |
| 665 | (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0); |
| 666 | |
| 667 | priv->params = *p; |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 668 | } |
| 669 | |
| 670 | static void |
| 671 | tda998x_encoder_dpms(struct drm_encoder *encoder, int mode) |
| 672 | { |
| 673 | struct tda998x_priv *priv = to_tda998x_priv(encoder); |
| 674 | |
| 675 | /* we only care about on or off: */ |
| 676 | if (mode != DRM_MODE_DPMS_ON) |
| 677 | mode = DRM_MODE_DPMS_OFF; |
| 678 | |
| 679 | if (mode == priv->dpms) |
| 680 | return; |
| 681 | |
| 682 | switch (mode) { |
| 683 | case DRM_MODE_DPMS_ON: |
Russell King | c4c11dd | 2013-08-14 21:43:30 +0200 | [diff] [blame^] | 684 | /* enable video ports, audio will be enabled later */ |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 685 | reg_write(encoder, REG_ENA_VP_0, 0xff); |
| 686 | reg_write(encoder, REG_ENA_VP_1, 0xff); |
| 687 | reg_write(encoder, REG_ENA_VP_2, 0xff); |
| 688 | /* set muxing after enabling ports: */ |
Russell King | 5e74c22 | 2013-08-14 21:43:29 +0200 | [diff] [blame] | 689 | reg_write(encoder, REG_VIP_CNTRL_0, priv->vip_cntrl_0); |
| 690 | reg_write(encoder, REG_VIP_CNTRL_1, priv->vip_cntrl_1); |
| 691 | reg_write(encoder, REG_VIP_CNTRL_2, priv->vip_cntrl_2); |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 692 | break; |
| 693 | case DRM_MODE_DPMS_OFF: |
| 694 | /* disable audio and video ports */ |
| 695 | reg_write(encoder, REG_ENA_AP, 0x00); |
| 696 | reg_write(encoder, REG_ENA_VP_0, 0x00); |
| 697 | reg_write(encoder, REG_ENA_VP_1, 0x00); |
| 698 | reg_write(encoder, REG_ENA_VP_2, 0x00); |
| 699 | break; |
| 700 | } |
| 701 | |
| 702 | priv->dpms = mode; |
| 703 | } |
| 704 | |
| 705 | static void |
| 706 | tda998x_encoder_save(struct drm_encoder *encoder) |
| 707 | { |
| 708 | DBG(""); |
| 709 | } |
| 710 | |
| 711 | static void |
| 712 | tda998x_encoder_restore(struct drm_encoder *encoder) |
| 713 | { |
| 714 | DBG(""); |
| 715 | } |
| 716 | |
| 717 | static bool |
| 718 | tda998x_encoder_mode_fixup(struct drm_encoder *encoder, |
| 719 | const struct drm_display_mode *mode, |
| 720 | struct drm_display_mode *adjusted_mode) |
| 721 | { |
| 722 | return true; |
| 723 | } |
| 724 | |
| 725 | static int |
| 726 | tda998x_encoder_mode_valid(struct drm_encoder *encoder, |
| 727 | struct drm_display_mode *mode) |
| 728 | { |
| 729 | return MODE_OK; |
| 730 | } |
| 731 | |
| 732 | static void |
| 733 | tda998x_encoder_mode_set(struct drm_encoder *encoder, |
| 734 | struct drm_display_mode *mode, |
| 735 | struct drm_display_mode *adjusted_mode) |
| 736 | { |
| 737 | struct tda998x_priv *priv = to_tda998x_priv(encoder); |
| 738 | uint16_t hs_start, hs_end, line_start, line_end; |
| 739 | uint16_t vwin_start, vwin_end, de_start, de_end; |
| 740 | uint16_t ref_pix, ref_line, pix_start2; |
| 741 | uint8_t reg, div, rep; |
| 742 | |
| 743 | hs_start = mode->hsync_start - mode->hdisplay; |
| 744 | hs_end = mode->hsync_end - mode->hdisplay; |
| 745 | line_start = 1; |
| 746 | line_end = 1 + mode->vsync_end - mode->vsync_start; |
| 747 | vwin_start = mode->vtotal - mode->vsync_start; |
| 748 | vwin_end = vwin_start + mode->vdisplay; |
| 749 | de_start = mode->htotal - mode->hdisplay; |
| 750 | de_end = mode->htotal; |
| 751 | |
| 752 | pix_start2 = 0; |
| 753 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 754 | pix_start2 = (mode->htotal / 2) + hs_start; |
| 755 | |
| 756 | /* TODO how is this value calculated? It is 2 for all common |
| 757 | * formats in the tables in out of tree nxp driver (assuming |
| 758 | * I've properly deciphered their byzantine table system) |
| 759 | */ |
| 760 | ref_line = 2; |
| 761 | |
| 762 | /* this might changes for other color formats from the CRTC: */ |
| 763 | ref_pix = 3 + hs_start; |
| 764 | |
| 765 | div = 148500 / mode->clock; |
| 766 | |
| 767 | DBG("clock=%d, div=%u", mode->clock, div); |
| 768 | DBG("hs_start=%u, hs_end=%u, line_start=%u, line_end=%u", |
| 769 | hs_start, hs_end, line_start, line_end); |
| 770 | DBG("vwin_start=%u, vwin_end=%u, de_start=%u, de_end=%u", |
| 771 | vwin_start, vwin_end, de_start, de_end); |
| 772 | DBG("ref_line=%u, ref_pix=%u, pix_start2=%u", |
| 773 | ref_line, ref_pix, pix_start2); |
| 774 | |
| 775 | /* mute the audio FIFO: */ |
| 776 | reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); |
| 777 | |
| 778 | /* set HDMI HDCP mode off: */ |
| 779 | reg_set(encoder, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); |
| 780 | reg_clear(encoder, REG_TX33, TX33_HDMI); |
| 781 | |
| 782 | reg_write(encoder, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0)); |
| 783 | /* no pre-filter or interpolator: */ |
| 784 | reg_write(encoder, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) | |
| 785 | HVF_CNTRL_0_INTPOL(0)); |
| 786 | reg_write(encoder, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); |
| 787 | reg_write(encoder, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) | |
| 788 | VIP_CNTRL_4_BLC(0)); |
| 789 | reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR); |
| 790 | |
| 791 | reg_clear(encoder, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ); |
| 792 | reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_DE); |
| 793 | reg_write(encoder, REG_SERIALIZER, 0); |
| 794 | reg_write(encoder, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0)); |
| 795 | |
| 796 | /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */ |
| 797 | rep = 0; |
| 798 | reg_write(encoder, REG_RPT_CNTRL, 0); |
| 799 | reg_write(encoder, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) | |
| 800 | SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); |
| 801 | |
| 802 | reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) | |
| 803 | PLL_SERIAL_2_SRL_PR(rep)); |
| 804 | |
| 805 | reg_write16(encoder, REG_VS_PIX_STRT_2_MSB, pix_start2); |
| 806 | reg_write16(encoder, REG_VS_PIX_END_2_MSB, pix_start2); |
| 807 | |
| 808 | /* set color matrix bypass flag: */ |
| 809 | reg_set(encoder, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP); |
| 810 | |
| 811 | /* set BIAS tmds value: */ |
| 812 | reg_write(encoder, REG_ANA_GENERAL, 0x09); |
| 813 | |
| 814 | reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_MTHD); |
| 815 | |
| 816 | reg_write(encoder, REG_VIP_CNTRL_3, 0); |
| 817 | reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_SYNC_HS); |
| 818 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 819 | reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_V_TGL); |
| 820 | |
| 821 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 822 | reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_H_TGL); |
| 823 | |
| 824 | reg_write(encoder, REG_VIDFORMAT, 0x00); |
Russell King | 20c1767 | 2013-08-14 21:43:28 +0200 | [diff] [blame] | 825 | reg_write16(encoder, REG_NPIX_MSB, mode->htotal); |
| 826 | reg_write16(encoder, REG_NLINE_MSB, mode->vtotal); |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 827 | reg_write16(encoder, REG_VS_LINE_STRT_1_MSB, line_start); |
| 828 | reg_write16(encoder, REG_VS_LINE_END_1_MSB, line_end); |
| 829 | reg_write16(encoder, REG_VS_PIX_STRT_1_MSB, hs_start); |
| 830 | reg_write16(encoder, REG_VS_PIX_END_1_MSB, hs_start); |
| 831 | reg_write16(encoder, REG_HS_PIX_START_MSB, hs_start); |
| 832 | reg_write16(encoder, REG_HS_PIX_STOP_MSB, hs_end); |
| 833 | reg_write16(encoder, REG_VWIN_START_1_MSB, vwin_start); |
| 834 | reg_write16(encoder, REG_VWIN_END_1_MSB, vwin_end); |
| 835 | reg_write16(encoder, REG_DE_START_MSB, de_start); |
| 836 | reg_write16(encoder, REG_DE_STOP_MSB, de_end); |
| 837 | |
| 838 | if (priv->rev == TDA19988) { |
| 839 | /* let incoming pixels fill the active space (if any) */ |
| 840 | reg_write(encoder, REG_ENABLE_SPACE, 0x01); |
| 841 | } |
| 842 | |
| 843 | reg_write16(encoder, REG_REFPIX_MSB, ref_pix); |
| 844 | reg_write16(encoder, REG_REFLINE_MSB, ref_line); |
| 845 | |
Russell King | c4c11dd | 2013-08-14 21:43:30 +0200 | [diff] [blame^] | 846 | reg = TBG_CNTRL_1_DWIN_DIS | /* HDCP off */ |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 847 | TBG_CNTRL_1_VH_TGL_2; |
Russell King | c4c11dd | 2013-08-14 21:43:30 +0200 | [diff] [blame^] | 848 | /* |
| 849 | * It is questionable whether this is correct - the nxp driver |
| 850 | * does not set VH_TGL_2 and the below for all display modes. |
| 851 | */ |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 852 | if (mode->flags & (DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC)) |
| 853 | reg |= TBG_CNTRL_1_VH_TGL_0; |
| 854 | reg_set(encoder, REG_TBG_CNTRL_1, reg); |
| 855 | |
| 856 | /* must be last register set: */ |
| 857 | reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE); |
Russell King | c4c11dd | 2013-08-14 21:43:30 +0200 | [diff] [blame^] | 858 | |
| 859 | /* Only setup the info frames if the sink is HDMI */ |
| 860 | if (priv->is_hdmi_sink) { |
| 861 | /* We need to turn HDMI HDCP stuff on to get audio through */ |
| 862 | reg_clear(encoder, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); |
| 863 | reg_write(encoder, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1)); |
| 864 | reg_set(encoder, REG_TX33, TX33_HDMI); |
| 865 | |
| 866 | tda998x_write_avi(encoder, adjusted_mode); |
| 867 | |
| 868 | if (priv->params.audio_cfg) |
| 869 | tda998x_configure_audio(encoder, adjusted_mode, |
| 870 | &priv->params); |
| 871 | } |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 872 | } |
| 873 | |
| 874 | static enum drm_connector_status |
| 875 | tda998x_encoder_detect(struct drm_encoder *encoder, |
| 876 | struct drm_connector *connector) |
| 877 | { |
| 878 | uint8_t val = cec_read(encoder, REG_CEC_RXSHPDLEV); |
| 879 | return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected : |
| 880 | connector_status_disconnected; |
| 881 | } |
| 882 | |
| 883 | static int |
| 884 | read_edid_block(struct drm_encoder *encoder, uint8_t *buf, int blk) |
| 885 | { |
| 886 | uint8_t offset, segptr; |
| 887 | int ret, i; |
| 888 | |
| 889 | /* enable EDID read irq: */ |
| 890 | reg_set(encoder, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); |
| 891 | |
| 892 | offset = (blk & 1) ? 128 : 0; |
| 893 | segptr = blk / 2; |
| 894 | |
| 895 | reg_write(encoder, REG_DDC_ADDR, 0xa0); |
| 896 | reg_write(encoder, REG_DDC_OFFS, offset); |
| 897 | reg_write(encoder, REG_DDC_SEGM_ADDR, 0x60); |
| 898 | reg_write(encoder, REG_DDC_SEGM, segptr); |
| 899 | |
| 900 | /* enable reading EDID: */ |
| 901 | reg_write(encoder, REG_EDID_CTRL, 0x1); |
| 902 | |
| 903 | /* flag must be cleared by sw: */ |
| 904 | reg_write(encoder, REG_EDID_CTRL, 0x0); |
| 905 | |
| 906 | /* wait for block read to complete: */ |
| 907 | for (i = 100; i > 0; i--) { |
| 908 | uint8_t val = reg_read(encoder, REG_INT_FLAGS_2); |
| 909 | if (val & INT_FLAGS_2_EDID_BLK_RD) |
| 910 | break; |
| 911 | msleep(1); |
| 912 | } |
| 913 | |
| 914 | if (i == 0) |
| 915 | return -ETIMEDOUT; |
| 916 | |
| 917 | ret = reg_read_range(encoder, REG_EDID_DATA_0, buf, EDID_LENGTH); |
| 918 | if (ret != EDID_LENGTH) { |
| 919 | dev_err(encoder->dev->dev, "failed to read edid block %d: %d", |
| 920 | blk, ret); |
| 921 | return ret; |
| 922 | } |
| 923 | |
| 924 | reg_clear(encoder, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); |
| 925 | |
| 926 | return 0; |
| 927 | } |
| 928 | |
| 929 | static uint8_t * |
| 930 | do_get_edid(struct drm_encoder *encoder) |
| 931 | { |
Russell King | 063b472 | 2013-08-14 21:43:26 +0200 | [diff] [blame] | 932 | struct tda998x_priv *priv = to_tda998x_priv(encoder); |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 933 | int j = 0, valid_extensions = 0; |
| 934 | uint8_t *block, *new; |
| 935 | bool print_bad_edid = drm_debug & DRM_UT_KMS; |
| 936 | |
| 937 | if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) |
| 938 | return NULL; |
| 939 | |
Russell King | 063b472 | 2013-08-14 21:43:26 +0200 | [diff] [blame] | 940 | if (priv->rev == TDA19988) |
| 941 | reg_clear(encoder, REG_TX4, TX4_PD_RAM); |
| 942 | |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 943 | /* base block fetch */ |
| 944 | if (read_edid_block(encoder, block, 0)) |
| 945 | goto fail; |
| 946 | |
| 947 | if (!drm_edid_block_valid(block, 0, print_bad_edid)) |
| 948 | goto fail; |
| 949 | |
| 950 | /* if there's no extensions, we're done */ |
| 951 | if (block[0x7e] == 0) |
Russell King | 063b472 | 2013-08-14 21:43:26 +0200 | [diff] [blame] | 952 | goto done; |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 953 | |
| 954 | new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); |
| 955 | if (!new) |
| 956 | goto fail; |
| 957 | block = new; |
| 958 | |
| 959 | for (j = 1; j <= block[0x7e]; j++) { |
| 960 | uint8_t *ext_block = block + (valid_extensions + 1) * EDID_LENGTH; |
| 961 | if (read_edid_block(encoder, ext_block, j)) |
| 962 | goto fail; |
| 963 | |
| 964 | if (!drm_edid_block_valid(ext_block, j, print_bad_edid)) |
| 965 | goto fail; |
| 966 | |
| 967 | valid_extensions++; |
| 968 | } |
| 969 | |
| 970 | if (valid_extensions != block[0x7e]) { |
| 971 | block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; |
| 972 | block[0x7e] = valid_extensions; |
| 973 | new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); |
| 974 | if (!new) |
| 975 | goto fail; |
| 976 | block = new; |
| 977 | } |
| 978 | |
Russell King | 063b472 | 2013-08-14 21:43:26 +0200 | [diff] [blame] | 979 | done: |
| 980 | if (priv->rev == TDA19988) |
| 981 | reg_set(encoder, REG_TX4, TX4_PD_RAM); |
| 982 | |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 983 | return block; |
| 984 | |
| 985 | fail: |
Russell King | 063b472 | 2013-08-14 21:43:26 +0200 | [diff] [blame] | 986 | if (priv->rev == TDA19988) |
| 987 | reg_set(encoder, REG_TX4, TX4_PD_RAM); |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 988 | dev_warn(encoder->dev->dev, "failed to read EDID\n"); |
| 989 | kfree(block); |
| 990 | return NULL; |
| 991 | } |
| 992 | |
| 993 | static int |
| 994 | tda998x_encoder_get_modes(struct drm_encoder *encoder, |
| 995 | struct drm_connector *connector) |
| 996 | { |
Russell King | c4c11dd | 2013-08-14 21:43:30 +0200 | [diff] [blame^] | 997 | struct tda998x_priv *priv = to_tda998x_priv(encoder); |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 998 | struct edid *edid = (struct edid *)do_get_edid(encoder); |
| 999 | int n = 0; |
| 1000 | |
| 1001 | if (edid) { |
| 1002 | drm_mode_connector_update_edid_property(connector, edid); |
| 1003 | n = drm_add_edid_modes(connector, edid); |
Russell King | c4c11dd | 2013-08-14 21:43:30 +0200 | [diff] [blame^] | 1004 | priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid); |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 1005 | kfree(edid); |
| 1006 | } |
| 1007 | |
| 1008 | return n; |
| 1009 | } |
| 1010 | |
| 1011 | static int |
| 1012 | tda998x_encoder_create_resources(struct drm_encoder *encoder, |
| 1013 | struct drm_connector *connector) |
| 1014 | { |
| 1015 | DBG(""); |
| 1016 | return 0; |
| 1017 | } |
| 1018 | |
| 1019 | static int |
| 1020 | tda998x_encoder_set_property(struct drm_encoder *encoder, |
| 1021 | struct drm_connector *connector, |
| 1022 | struct drm_property *property, |
| 1023 | uint64_t val) |
| 1024 | { |
| 1025 | DBG(""); |
| 1026 | return 0; |
| 1027 | } |
| 1028 | |
| 1029 | static void |
| 1030 | tda998x_encoder_destroy(struct drm_encoder *encoder) |
| 1031 | { |
| 1032 | struct tda998x_priv *priv = to_tda998x_priv(encoder); |
| 1033 | drm_i2c_encoder_destroy(encoder); |
| 1034 | kfree(priv); |
| 1035 | } |
| 1036 | |
| 1037 | static struct drm_encoder_slave_funcs tda998x_encoder_funcs = { |
| 1038 | .set_config = tda998x_encoder_set_config, |
| 1039 | .destroy = tda998x_encoder_destroy, |
| 1040 | .dpms = tda998x_encoder_dpms, |
| 1041 | .save = tda998x_encoder_save, |
| 1042 | .restore = tda998x_encoder_restore, |
| 1043 | .mode_fixup = tda998x_encoder_mode_fixup, |
| 1044 | .mode_valid = tda998x_encoder_mode_valid, |
| 1045 | .mode_set = tda998x_encoder_mode_set, |
| 1046 | .detect = tda998x_encoder_detect, |
| 1047 | .get_modes = tda998x_encoder_get_modes, |
| 1048 | .create_resources = tda998x_encoder_create_resources, |
| 1049 | .set_property = tda998x_encoder_set_property, |
| 1050 | }; |
| 1051 | |
| 1052 | /* I2C driver functions */ |
| 1053 | |
| 1054 | static int |
| 1055 | tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id) |
| 1056 | { |
| 1057 | return 0; |
| 1058 | } |
| 1059 | |
| 1060 | static int |
| 1061 | tda998x_remove(struct i2c_client *client) |
| 1062 | { |
| 1063 | return 0; |
| 1064 | } |
| 1065 | |
| 1066 | static int |
| 1067 | tda998x_encoder_init(struct i2c_client *client, |
| 1068 | struct drm_device *dev, |
| 1069 | struct drm_encoder_slave *encoder_slave) |
| 1070 | { |
| 1071 | struct drm_encoder *encoder = &encoder_slave->base; |
| 1072 | struct tda998x_priv *priv; |
| 1073 | |
| 1074 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
| 1075 | if (!priv) |
| 1076 | return -ENOMEM; |
| 1077 | |
Russell King | 5e74c22 | 2013-08-14 21:43:29 +0200 | [diff] [blame] | 1078 | priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3); |
| 1079 | priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1); |
| 1080 | priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5); |
| 1081 | |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 1082 | priv->current_page = 0; |
| 1083 | priv->cec = i2c_new_dummy(client->adapter, 0x34); |
| 1084 | priv->dpms = DRM_MODE_DPMS_OFF; |
| 1085 | |
| 1086 | encoder_slave->slave_priv = priv; |
| 1087 | encoder_slave->slave_funcs = &tda998x_encoder_funcs; |
| 1088 | |
| 1089 | /* wake up the device: */ |
| 1090 | cec_write(encoder, REG_CEC_ENAMODS, |
| 1091 | CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI); |
| 1092 | |
| 1093 | tda998x_reset(encoder); |
| 1094 | |
| 1095 | /* read version: */ |
| 1096 | priv->rev = reg_read(encoder, REG_VERSION_LSB) | |
| 1097 | reg_read(encoder, REG_VERSION_MSB) << 8; |
| 1098 | |
| 1099 | /* mask off feature bits: */ |
| 1100 | priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */ |
| 1101 | |
| 1102 | switch (priv->rev) { |
| 1103 | case TDA9989N2: dev_info(dev->dev, "found TDA9989 n2"); break; |
| 1104 | case TDA19989: dev_info(dev->dev, "found TDA19989"); break; |
| 1105 | case TDA19989N2: dev_info(dev->dev, "found TDA19989 n2"); break; |
| 1106 | case TDA19988: dev_info(dev->dev, "found TDA19988"); break; |
| 1107 | default: |
| 1108 | DBG("found unsupported device: %04x", priv->rev); |
| 1109 | goto fail; |
| 1110 | } |
| 1111 | |
| 1112 | /* after reset, enable DDC: */ |
| 1113 | reg_write(encoder, REG_DDC_DISABLE, 0x00); |
| 1114 | |
| 1115 | /* set clock on DDC channel: */ |
| 1116 | reg_write(encoder, REG_TX3, 39); |
| 1117 | |
| 1118 | /* if necessary, disable multi-master: */ |
| 1119 | if (priv->rev == TDA19989) |
| 1120 | reg_set(encoder, REG_I2C_MASTER, I2C_MASTER_DIS_MM); |
| 1121 | |
| 1122 | cec_write(encoder, REG_CEC_FRO_IM_CLK_CTRL, |
| 1123 | CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL); |
| 1124 | |
| 1125 | return 0; |
| 1126 | |
| 1127 | fail: |
| 1128 | /* if encoder_init fails, the encoder slave is never registered, |
| 1129 | * so cleanup here: |
| 1130 | */ |
| 1131 | if (priv->cec) |
| 1132 | i2c_unregister_device(priv->cec); |
| 1133 | kfree(priv); |
| 1134 | encoder_slave->slave_priv = NULL; |
| 1135 | encoder_slave->slave_funcs = NULL; |
| 1136 | return -ENXIO; |
| 1137 | } |
| 1138 | |
| 1139 | static struct i2c_device_id tda998x_ids[] = { |
| 1140 | { "tda998x", 0 }, |
| 1141 | { } |
| 1142 | }; |
| 1143 | MODULE_DEVICE_TABLE(i2c, tda998x_ids); |
| 1144 | |
| 1145 | static struct drm_i2c_encoder_driver tda998x_driver = { |
| 1146 | .i2c_driver = { |
| 1147 | .probe = tda998x_probe, |
| 1148 | .remove = tda998x_remove, |
| 1149 | .driver = { |
| 1150 | .name = "tda998x", |
| 1151 | }, |
| 1152 | .id_table = tda998x_ids, |
| 1153 | }, |
| 1154 | .encoder_init = tda998x_encoder_init, |
| 1155 | }; |
| 1156 | |
| 1157 | /* Module initialization */ |
| 1158 | |
| 1159 | static int __init |
| 1160 | tda998x_init(void) |
| 1161 | { |
| 1162 | DBG(""); |
| 1163 | return drm_i2c_encoder_register(THIS_MODULE, &tda998x_driver); |
| 1164 | } |
| 1165 | |
| 1166 | static void __exit |
| 1167 | tda998x_exit(void) |
| 1168 | { |
| 1169 | DBG(""); |
| 1170 | drm_i2c_encoder_unregister(&tda998x_driver); |
| 1171 | } |
| 1172 | |
| 1173 | MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); |
| 1174 | MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder"); |
| 1175 | MODULE_LICENSE("GPL"); |
| 1176 | |
| 1177 | module_init(tda998x_init); |
| 1178 | module_exit(tda998x_exit); |